f3f5f1b5-029 Verification Engineer You are an experienced verification engineer passionate about developing reliable and robust SoC and ASIC solutions. You thrive in collaborative environments, are skilled with SystemVerilog (UVM preferred), and enjoy tackling complex debugging and coverage challenges.

What you'll do

Develop reusable verification environments and testbenches using UVM.

  • Plan, maintain, and execute verification strategies for ASIC/SoC projects.
  • Create test cases, set up and run regressions, and close coverage.

What you need

Minimum 6 years' SoC/ASIC verification experience.

  • Strong SystemVerilog (UVM preferred) skills.

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]]> full-time senior onsite SystemVerilog, UVM, SoC/ASIC verification experience, Perl, Tcl, csh, Python Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. https://careers.synopsys.com https://careers.synopsys.com/job/ho-chi-minh-city/asic-digital-design-sr-staff-engineer-verification/44408/89065656800 Ho Chi Minh City 2025-12-22 08387f80-a4f Verification Engineer You Are an accomplished verification engineer with deep expertise in mixed-signal systems, passionate about real number modeling (RNM) you will translate the nuanced behavior of leading-edge analog circuits into high-fidelity, scalable behavioural models.

What you'll do

Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data.

  • Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator).

What you need

BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience.

  • Advanced proficiency in RNM, mixed-signal verification, and high-speed SerDes design.

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]]> full-time senior onsite $181,000-$271,000 RNM, mixed-signal verification, high-speed SerDes design, analog circuit design, SPICE-level simulations, silicon data analysis, behavioural modelling, mixed-signal verification tools, high-speed SerDes design methodologies Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. https://careers.synopsys.com https://careers.synopsys.com/job/chandler/analog-models-and-verification-engineer-architect-13485/44408/88700860768 Chandler, AZ, Markham or Mississauga, Canada 2025-12-22