{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/verification-engineer"},"x-facet":{"type":"title","slug":"verification-engineer","display":"Verification Engineer","count":2},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f3f5f1b5-029"},"title":"Verification Engineer","description":"<p>You are an experienced verification engineer passionate about developing reliable and robust SoC and ASIC solutions. You thrive in collaborative environments, are skilled with SystemVerilog (UVM preferred), and enjoy tackling complex debugging and coverage challenges.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop reusable verification environments and testbenches using UVM.</p>\n<ul>\n<li>Plan, maintain, and execute verification strategies for ASIC/SoC projects.</li>\n</ul>\n<ul>\n<li>Create test cases, set up and run regressions, and close coverage.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<p>Minimum 6 years&#39; SoC/ASIC verification experience.</p>\n<ul>\n<li>Strong SystemVerilog (UVM preferred) skills.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f3f5f1b5-029","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-digital-design-sr-staff-engineer-verification/44408/89065656800","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SystemVerilog","UVM","SoC/ASIC verification experience"],"x-skills-preferred":["Perl","Tcl","csh","Python"],"datePosted":"2025-12-22T12:02:19.714Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SystemVerilog, UVM, SoC/ASIC verification experience, Perl, Tcl, csh, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_08387f80-a4f"},"title":"Verification Engineer","description":"<p>You Are an accomplished verification engineer with deep expertise in mixed-signal systems, passionate about real number modeling (RNM) you will translate the nuanced behavior of leading-edge analog circuits into high-fidelity, scalable behavioural models.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data.</p>\n<ul>\n<li>Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator).</li>\n</ul>\n<p><strong>What you need</strong></p>\n<p>BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience.</p>\n<ul>\n<li>Advanced proficiency in RNM, mixed-signal verification, and high-speed SerDes design.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_08387f80-a4f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/chandler/analog-models-and-verification-engineer-architect-13485/44408/88700860768","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$181,000-$271,000","x-skills-required":["RNM","mixed-signal verification","high-speed SerDes design","analog circuit design","SPICE-level simulations","silicon data analysis"],"x-skills-preferred":[" behavioural modelling","mixed-signal verification tools","high-speed SerDes design methodologies"],"datePosted":"2025-12-22T12:00:59.973Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Chandler, AZ, Markham or Mississauga, Canada"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RNM, mixed-signal verification, high-speed SerDes design, analog circuit design, SPICE-level simulations, silicon data analysis,  behavioural modelling, mixed-signal verification tools, high-speed SerDes design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":181000,"maxValue":271000,"unitText":"YEAR"}}}]}