{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/verification-design-lead"},"x-facet":{"type":"title","slug":"verification-design-lead","display":"Verification Design Lead","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f7e7aee-bc7"},"title":"Verification Design Lead","description":"<p>At Synopsys, we drive innovations that shape how we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. As leaders in chip design, verification, and IP integration, we empower the creation of high-performance silicon chips and software.</p>\n<p>You are an experienced verification architect who thrives on technical leadership and mentoring others. You excel in digital design and verification, enjoy collaborating with global teams, and are motivated by delivering high-quality solutions. Your expertise includes System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. You’re proactive, inclusive, and passionate about process improvement and innovation.</p>\n<p>Responsibilities:\nProvide technical leadership and mentor junior engineers.\nCollaborate with cross-functional, global teams.\nDefine and implement advanced verification plans and methodologies.\nDevelop and maintain UVM-based testbenches.\nDrive process improvements for verification efficiency.\nAutomate verification flows using scripting and programming skills.</p>\n<p>The Impact You Will Have:\nEnsure robust verification for complex ASIC and IP designs.\nSupport first-silicon success and faster time-to-market.\nElevate team skills and technical excellence.\nChampion best verification practices and tools.\nEnhance collaboration across global teams.\nPromote continuous improvement in verification processes.</p>\n<p>What You’ll Need:\nBSEE or MSEE with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL.\nExpertise in UVM and coverage-driven RTL verification.\nProficiency in scripting and programming (Python, Perl, C/C++).\nAbility to define verification plans and architect testbenches.\nExperience with 200G SerDes verification is an asset.</p>\n<p>Who You Are:\nCollaborative leader and effective communicator.\nMentor who empowers others.\nAnalytical, detail-oriented problem solver.\nAdaptable and innovative.</p>\n<p>The Team You’ll Be A Part Of:\nJoin a diverse, world-class engineering team dedicated to delivering industry-leading verification solutions for next-generation semiconductor products.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2f7e7aee-bc7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ottawa/verification-design-lead-14733/44408/91320791920","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["System Verilog","Verilog","VHDL","UVM","C/C++"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:41.079Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ottawa"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, Verilog, VHDL, UVM, C/C++"}]}