{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/staff-asic-digital-design-engineer"},"x-facet":{"type":"title","slug":"staff-asic-digital-design-engineer","display":"Staff Asic Digital Design Engineer","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e40da191-421"},"title":"Staff ASIC Digital Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff ASIC Digital Design Engineer, you will be part of our R&amp;D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.</p>\n<p>Key responsibilities include:</p>\n<p>Creating and debugging test benches and test cases\nRunning RTL and gate-level simulations\nSupporting application engineers and customers on HBM/DDR PHY topics\nContributing to technical documentation\nDriving product improvements based on customer feedback</p>\n<p>The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:</p>\n<p>ASIC RTL design and verification experience\nVerilog, PERL, TCL, Python skills\nStatic timing analysis and synthesis knowledge\nSimulation and debugging abilities\nHBM/DDR protocol experience is an asset</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e40da191-421","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/staff-asic-digital-design-engineer-15996/44408/93015824864","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design and verification experience","Verilog, PERL, TCL, Python skills","Static timing analysis and synthesis knowledge","Simulation and debugging abilities","HBM/DDR protocol experience"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:45.947Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design and verification experience, Verilog, PERL, TCL, Python skills, Static timing analysis and synthesis knowledge, Simulation and debugging abilities, HBM/DDR protocol experience"}]}