We are hiring in Ottawa, ON and Mississauga, ON.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars, machine learning to artificial intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

We develop and deliver industry-leading high-speed interface IP and system solutions, enabling customers to build reliable, high-performance products across advanced nodes and packaging technologies. Our Signal & Power Integrity (SIPI) team partners across silicon design, package design, board design, and validation teams to ensure robust SerDes links and power delivery in complex system environments.

You are a highly skilled and passionate engineer with a deep understanding of high-speed signal and power integrity, particularly in the realm of SerDes interfaces. With a proven track record in end-to-end SIPI for advanced links such as PCI Express (Gen6/7/8), E224G, E448G, and CXL (over PCIe), you thrive on solving complex engineering challenges and collaborating across cross-functional teams.

As a technical leader, you mentor others, drive technical reviews, and are committed to sharing your knowledge and standardizing best practices. Your disciplined approach to documentation and reproducibility ensures that learnings are captured and reused.

Responsibilities

• Lead end-to-end SIPI for high-speed interfaces including PCI Express (Gen6/7/8), E224G, E448G, CXL (over PCIe), and other SerDes interfaces, spanning on-die, interposer, package, PCB, connectors, and compliance fixtures.

• Drive channel modeling and correlation across time- and frequency-domain analysis: S-parameters, TDR, crosstalk, ICN/ccICN, ERL/dERL, jitter/noise budgeting, equalization tradeoffs (TX/RX FFE/DFE/CTLE), eye margin simulation, and link margining.

• Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI model extraction/model quality checks, de-embedding, and ensuring models are bandwidth-appropriate for target data rates.

• Partner with circuit/PHY, interposer/package, board, and product teams to diagnose bring-up and lab issues; propose design fixes and quantify risk/benefit via simulation and measurement.

• Plan and run correlation experiments (bench characterization, compliance testing support, fixture design guidance) and document learnings as reusable design guidelines.

• Define, improve, and document SIPI flows, requirements, and checklists for internal teams and (where applicable) customers; mentor engineers and lead technical reviews.

• Provide technical leadership across programs: set priorities, identify cross-project reuse opportunities, and influence architecture choices impacting signal integrity and power integrity.

Impact

• Enable first-pass success of high-speed SerDes IP and system integrations by defining robust SIPI signoff criteria and delivering validated, correlated methodologies.

• Reduce schedule risk by rapidly diagnosing complex cross-domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis.

• Raise the technical bar by mentoring others, standardizing best practices, and influencing architectural decisions for next-generation interconnects.

• Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments.

• Drive innovation in SIPI methodologies, enabling scalable, reusable flows across multiple programs and product lines.

• Foster a culture of collaboration and continuous improvement within the team and across partnering organizations.

Requirements

• B.S. (M.S./Ph.D. preferred) in Electrical/Electronics Engineering or related field.

• 10+ years of relevant experience in high-speed SI/PI for SerDes links (silicon + package + board), preferably in interface IP or high-volume product development.

• Strong fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; comfortable translating system requirements into measurable/signoff criteria.

• Expertise with high-speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER, etc.

• Hands-on experience with modeling, simulation, and EM tools (HSPICE, Keysight ADS/SysteVue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, Mathworks SIMULINK) and model formats (Touchstone, IBIS-AMI, SPICE, EM-based RLGC).

• Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working alongside validation/compliance teams.

• Proficiency in scripting/automation for flow enablement (Python preferred; MATLAB/TCL a plus) and a disciplined approach to documentation and reproducibility.

• Demonstrated technical leadership: mentoring, design reviews, influencing cross-functional decisions, and communicating complex topics clearly to mixed audiences.

Who You Are

• Analytical and detail-oriented, with a passion for tackling complex engineering challenges.

• Collaborative and communicative, able to work effectively across multi-disciplinary teams.

• Proactive and resourceful, constantly seeking opportunities to optimize processes and drive innovation.

• Mentor and leader, committed to sharing knowledge and empowering others.

• Disciplined and organized, with a strong focus on documentation, reproducibility, and best practices.

• Adaptable, able to thrive in fast-paced, dynamic environments.

The Team You’ll Be Part Of

You will join a global SIPI team that works closely with SerDes/PHY design, package and board engineering, validation, and product teams to deliver high-performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment. Together, we drive innovation and enable our customers to create high-performance silicon chips and software content.

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