You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion for verification and a keen eye for detail. With a strong background in architecting verification environments for complex serial protocols, you are proficient in HVL (System Verilog) and have hands-on experience with industry-standard simulators. Your extensive experience includes developing and implementing test plans, extracting verification metrics, and coding for functional coverage. You are well-versed in verification methodologies such as VMM, OVM, and UVM, and have a solid understanding of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. Your familiarity with HDLs like Verilog and scripting languages such as Perl, TCL, and Python enhances your verification processes. You possess exceptional problem-solving skills, demonstrate high levels of initiative, and excel in written and oral communication. Your collaborative spirit enables you to work closely with RTL designers and seamlessly integrate into a global team of professional verification engineers, driving the next generation of connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you'll do
\nSpecifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.
\nPerforming verification tasks for IP cores, including test planning and environment coding at both unit and system levels.
\nDeveloping and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.
\nManaging regression and ensuring adherence to verification methodologies.
\nCollaborating closely with RTL designers and a global team of verification engineers.
\nWorking on next-generation connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you need
\nBSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.
\nExperience in architecting verification environments for complex serial protocols.
\nProficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.
\nExpertise in verification methodologies such as VMM, OVM, and UVM.
\nKnowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.
\nFamiliarity with Verilog and scripting languages such as Perl, TCL, and Python.
\nExperience with IP design and verification processes, including VIP development.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_e21ac2ad-394","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-verification-principal-engineer/44408/77023412560","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["HVL (System Verilog)","industry-standard simulators","verification methodologies","protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB","HDLs like Verilog","scripting languages such as Perl, TCL, and Python"],"x-skills-preferred":["VIP development"],"datePosted":"2025-12-22T12:04:28.502Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"HVL (System Verilog), industry-standard simulators, verification methodologies, protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB, HDLs like Verilog, scripting languages such as Perl, TCL, and Python, VIP development"}]}