98785e57-1a3 Principal ASIC Verification Engineer As a Principal ASIC Verification Engineer at Synopsys, you will be responsible for partnering with design teams to define verification requirements, developing test plans from specifications, and building and maintaining UVM testbenches and agents.

What you'll do

  • Partnering with design teams to define verification requirements
  • Developing test plans from specifications
  • Building and maintaining UVM testbenches and agents

What you need

  • B.Sc./M.Sc. in a relevant engineering field
  • 10+ years in ASIC/UVM verification

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]]> full-time senior onsite SystemVerilog, C, Python, TCL/Perl, UVM, SVA, Formal verification, Interface IPs (PCIe, CXL), AI tools Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a global leader in chip design and verification, empowering the creation of high-performance silicon and software. They drive innovations that shape the world, from self-driving cars to AI and the cloud. https://careers.synopsys.com https://careers.synopsys.com/job/munich/principal-asic-verification-engineer/44408/91377529600 Munich 2026-03-06