What you'll do

• Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.
• Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.
• Carry out experiments to validate modeling and methodologies.
• Develop and document signal and power integrity requirements and flows for internal and external customer use.

What you need

• Possesses excellent communication skills, both verbal and written.
• Familiarity with both Windows and Linux operating system is required.
• An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.
• Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.
• Some experience in programming languages such as Python, TCL and Matlab is desired.
• A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. Experience with Redhawk, Totem, Ansys AEDT, Keysight ADS, etc. is a plus.
• Practical experience with package and pcb design 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.
• Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
• Bachelor's or Master's degree in Electrical or Electronics Engineering, with a minimum of 6 years of relevant experience in supporting interface IP product development (preferably DDR), system integration and Signal and Power verifications flow/methodologies.

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