You are an accomplished engineer with a passion for digital design and verification, eager to make a lasting impact in advanced semiconductor technology. With over a decade of hands-on experience, you bring technical mastery and strategic vision to every project. You thrive in dynamic environments, seamlessly balancing architectural planning with hands-on execution. Your expertise spans RTL development, mixed-signal IPs, and advanced verification methodologies, making you a go-to authority for complex challenges.

As a Lead RTL Verification Engineer, you will be responsible for architecting and implementing SystemVerilog/UVM-based testbenches and verification flows for mixed signal IPs such as UCIe/DDR/Die-to-Die interfaces. You will develop, execute, and drive closure for comprehensive verification plans and coverage metrics. You will also debug RTL issues, manage regressions, and lead root cause analysis for failures.

Guiding and mentoring junior engineers, establishing verification standards and best practices, collaborating with design, software, and validation teams to ensure seamless project delivery and integration, evaluating and championing new verification tools, automation scripts, and methodologies to drive innovation.

Elevate the quality and reliability of Synopsys' mixed signal IPs, directly impacting the success of global semiconductor partners. Accelerate innovation in chip design and verification, contributing to industry-leading products and solutions. Mentor and empower the next generation of engineers, fostering a culture of excellence and growth. Drive adoption of best-in-class verification standards, enhancing productivity and efficiency across teams. Enable seamless integration of complex IPs by bridging design, software, and validation disciplines. Champion advanced verification technologies, positioning Synopsys as a leader in digital design automation.

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