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    <job>
      <externalid>08696b6c-bd8</externalid>
      <Title>Lead RTL Design Engineer</Title>
      <Description><![CDATA[<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>
<p>As a Lead RTL Design Engineer, you will be responsible for leading RTL design and implementation for high-performance mixed signal IPs including UCIe, DDR, and Die-to-Die interfaces. You will take technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews.</p>
<p>Key responsibilities include:</p>
<ul>
<li>Leading RTL design and implementation for high-performance mixed signal IPs</li>
<li>Taking technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews</li>
<li>Specifying, architecting, and implementing digital logic using Verilog/SystemVerilog</li>
<li>Collaborating with circuit design, verification, physical design, and validation teams to ensure design closure and integration</li>
<li>Driving logic synthesis, lint, clock domain crossing (CDC), design-for-test (DFT), and timing closure for your blocks</li>
<li>Analyzing coverage, debugging functional and timing issues, supporting integration, and authoring technical documentation</li>
</ul>
<p>In this role, you will contribute to Synopsys&#39; reputation as a leader in advanced semiconductor design solutions. You will drive innovation in digital design and architecture, influencing key product features and capabilities. You will ensure the delivery of high-quality, reliable, and scalable IPs that meet stringent market requirements.</p>
<p>As a leader, you will foster a culture of continuous learning, inclusivity, and creative thinking, empowering your peers and advancing the team&#39;s collective success. You will be motivated by working on cutting-edge IPs such as UCIe, DDR, and Die-to-Die interfaces, and you will stay current with industry trends and emerging technologies, including AI/ML.</p>
<p>You will join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange>$120,000 - $180,000 per year</Salaryrange>
      <Skills>RTL design, Verilog/SystemVerilog, Digital logic, Clock domain crossing (CDC), Design-for-test (DFT), Timing closure, AI/ML, UCIe, DDR, Die-to-Die interfaces, Python, TCL, Perl</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and services used in the design, verification, and manufacturing of advanced semiconductors.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/bengaluru/lead-rtl-design-engineer/44408/93647959712</Applyto>
      <Location>Bengaluru</Location>
      <Country></Country>
      <Postedate>2026-04-24</Postedate>
    </job>
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