{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/lead-rtl-design-engineer"},"x-facet":{"type":"title","slug":"lead-rtl-design-engineer","display":"Lead RTL Design Engineer","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_08696b6c-bd8"},"title":"Lead RTL Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Lead RTL Design Engineer, you will be responsible for leading RTL design and implementation for high-performance mixed signal IPs including UCIe, DDR, and Die-to-Die interfaces. You will take technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading RTL design and implementation for high-performance mixed signal IPs</li>\n<li>Taking technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews</li>\n<li>Specifying, architecting, and implementing digital logic using Verilog/SystemVerilog</li>\n<li>Collaborating with circuit design, verification, physical design, and validation teams to ensure design closure and integration</li>\n<li>Driving logic synthesis, lint, clock domain crossing (CDC), design-for-test (DFT), and timing closure for your blocks</li>\n<li>Analyzing coverage, debugging functional and timing issues, supporting integration, and authoring technical documentation</li>\n</ul>\n<p>In this role, you will contribute to Synopsys&#39; reputation as a leader in advanced semiconductor design solutions. You will drive innovation in digital design and architecture, influencing key product features and capabilities. You will ensure the delivery of high-quality, reliable, and scalable IPs that meet stringent market requirements.</p>\n<p>As a leader, you will foster a culture of continuous learning, inclusivity, and creative thinking, empowering your peers and advancing the team&#39;s collective success. You will be motivated by working on cutting-edge IPs such as UCIe, DDR, and Die-to-Die interfaces, and you will stay current with industry trends and emerging technologies, including AI/ML.</p>\n<p>You will join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_08696b6c-bd8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/lead-rtl-design-engineer/44408/93647959712","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$120,000 - $180,000 per year","x-skills-required":["RTL design","Verilog/SystemVerilog","Digital logic","Clock domain crossing (CDC)","Design-for-test (DFT)","Timing closure","AI/ML"],"x-skills-preferred":["UCIe","DDR","Die-to-Die interfaces","Python","TCL","Perl"],"datePosted":"2026-04-24T14:18:40.609Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog/SystemVerilog, Digital logic, Clock domain crossing (CDC), Design-for-test (DFT), Timing closure, AI/ML, UCIe, DDR, Die-to-Die interfaces, Python, TCL, Perl","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":120000,"maxValue":180000,"unitText":"YEAR"}}}]}