The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.

The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.

To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).

You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.

Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.

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