ASIC Physical Design, Sr Staff

509e3a3b-0fb ASIC Physical Design, Sr Staff Opening. This role is a key member of the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. The team is responsible for next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

What you'll do

Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.

Work with leading edge designs and teams to drive the industry best PPA for IP designs.

Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.

Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.

Work as a liaison between EDAG tool and IP design teams.

Continuously improve and refine design processes to enhance efficiency and performance.

What you need

BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.

Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.

Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

Good analysis, debugging, and problem-solving skills.

Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.

Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

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]]> full-time senior onsite BS or MS in EE, 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs, Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions, Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools, Ability to facilitate cross-functional collaboration, Good analysis, debugging, and problem-solving skills, Solid written and verbal communication skills, Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools), Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. https://careers.synopsys.com https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-staff/44408/91568840304?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hyderabad 2026-02-11