Opening. This role is a key member of the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. The team is responsible for next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWhat you'll do
\nDevelop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.
\nWork with leading edge designs and teams to drive the industry best PPA for IP designs.
\nEvaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.
\nDevelop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
\nWork as a liaison between EDAG tool and IP design teams.
\nContinuously improve and refine design processes to enhance efficiency and performance.
\nWhat you need
\nBS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.
\nKnowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
\nDirect hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.
\nAbility to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
\nGood analysis, debugging, and problem-solving skills.
\nSolid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nFamiliarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.
\nWorking knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nXML job scraping automation by YubHub
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