At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. Join us to transform the future through technological innovation.

You are a skilled ASIC Digital Design Engineer with over 5 years of design verification experience. You thrive in collaborative settings, communicate clearly, and have a strong technical foundation in simulation tools and scripting. Driven by curiosity and a passion for technology, you’re eager to make an impact on Data Center, AI/ML, and 5G solutions.

Developing and validating high-speed interface IP in digital/mixed-signal environments. Planning tests, coverage, and assertions for robust verification. Building verification environments from specifications. Applying advanced techniques: constrained random, coverage, assertions, formal verification. Debugging simulations and performing RTL, GLS, and co-simulations. Supporting customers and improving development processes.

Advance Synopsys’ IP quality and reliability. Accelerate development for Data Center, AI/ML, and 5G. Drive innovation through modern verification methods. Ensure customer success with seamless IP integration. Enhance team collaboration and workflow.

BS/MS/PhD in Electronics Engineering or related field. 6+ years in design verification. Experience with VCS/Verdi and formal verification tools. Knowledge of UPF, UVM, SVA is a plus. Debugging and Perl/TCL/Python scripting skills.

Responsible, results-driven, and a strong communicator. Team-oriented and supportive. Self-motivated and enthusiastic about technology.

Work with a talented group of engineers developing high-performance IP for cutting-edge applications, in a collaborative and inclusive environment.

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details during the hiring process.

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