{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/asic-digital-verification-principal-engineer"},"x-facet":{"type":"title","slug":"asic-digital-verification-principal-engineer","display":"ASIC Digital Verification- Principal Engineer","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f92780ee-f5d"},"title":"ASIC Digital Verification- Principal Engineer","description":"<p>We are seeking a highly skilled Principal Engineer to lead our ASIC Digital Verification team. As a Principal Engineer, you will be responsible for developing and maintaining high-quality digital verification environments, including UVM, SystemVerilog, and C++.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Develop and maintain high-quality digital verification environments, including UVM, SystemVerilog, and C++.</li>\n<li>Collaborate with cross-functional teams to develop and verify complex digital designs.</li>\n<li>Identify and prioritize verification tasks to meet project timelines and quality standards.</li>\n<li>Develop and execute verification plans, including testbenches, test cases, and coverage metrics.</li>\n<li>Collaborate with design teams to develop and verify complex digital designs.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Computer Science, Electrical Engineering, or related field.</li>\n<li>10+ years of experience in digital verification, including UVM, SystemVerilog, and C++.</li>\n<li>Strong understanding of digital design principles and verification methodologies.</li>\n<li>Excellent communication and collaboration skills.</li>\n<li>Experience with Agile development methodologies and version control systems.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f92780ee-f5d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/principal-asic-digital-verification-engineer-ip-development/44408/87859219360?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["UVM","SystemVerilog","C++","digital verification","verification environments","testbenches","test cases","coverage metrics","Agile development methodologies","version control systems"],"x-skills-preferred":["Agile development methodologies","version control systems"],"datePosted":"2025-12-22T12:02:09.199Z","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"UVM, SystemVerilog, C++, digital verification, verification environments, testbenches, test cases, coverage metrics, Agile development methodologies, version control systems, Agile development methodologies, version control systems"}]}