{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/title/analog-layout-engineer-staff"},"x-facet":{"type":"title","slug":"analog-layout-engineer-staff","display":"Analog Layout Engineer, Staff","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_88ccbb95-393"},"title":"Analog Layout Engineer, Staff","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As an experienced Analog Layout Senior Engineer, you will be working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Working on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.</li>\n<li>Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.</li>\n<li>Applying Analog Layout techniques to ensure design meets performance with minimum area and good yield.</li>\n<li>Building and enhancing layout flow for faster, higher quality design processes.</li>\n<li>Performing layout verification for DRC/LVS/ERC/ANT/ESD/DFM.</li>\n<li>Conducting PERC verification for ESD/LUP checks.</li>\n<li>Completing all design quality checks and data quality checks.</li>\n<li>Collaborating with Place and Route engineers to integrate analog layouts into the top level.</li>\n<li>Working with the Package team to ensure the integration of top die and package.</li>\n<li>Participating in design reviews across the global team.</li>\n<li>Engaging in package design, including interposer and RDL design.</li>\n<li>Collaborating closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.</li>\n<li>Joining research programs to implement new ideas for future products and flows.</li>\n<li>Leading a layout team to complete a full design block.</li>\n<li>Mentoring junior layout engineers or interns.</li>\n</ul>\n<p>The impact you will have includes driving the development of high-performance Analog IPs that power cutting-edge technologies, enhancing the layout design process for improved efficiency and quality, ensuring the robustness and reliability of our designs through meticulous verification processes, contributing to the integration of complex layouts into top-level designs, fostering collaboration and knowledge sharing across global teams, and mentoring and developing the next generation of layout engineers.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_88ccbb95-393","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/analog-layout-engineer-staff/44408/93685544192","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Cadence","Synopsys","Mentor Calibre","Synopsys ICV","Basic semiconductor fabrication processes","MOSFET fundamentals","High-speed layout techniques","ESD","Latchup","Antenna","EMIR"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:10:57.905Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence, Synopsys, Mentor Calibre, Synopsys ICV, Basic semiconductor fabrication processes, MOSFET fundamentals, High-speed layout techniques, ESD, Latchup, Antenna, EMIR"}]}