In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>200Gbps) analog integrated circuits in the latest FinFET process nodes.

Responsibilities:

• Reviewing SerDes standards and architecture documents to develop comprehensive analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing and executing design and verification strategies that leverage advanced simulator features for highest-quality design outcomes.
• Overseeing physical layout to minimize parasitic effects, device stress, and process variation, ensuring robust silicon performance.
• Collaborating closely with digital RTL engineers to develop calibration, adaptation, and control algorithms for analog circuits.
• Presenting simulation data for peer and customer reviews, effectively communicating design decisions and results.
• Mentoring and reviewing the progress of junior engineers, fostering a high-performance team environment.
• Documenting design features, test plans, and methodologies to ensure traceability and reproducibility.
• Consulting on the electrical characterization of analog circuits within the SerDes IP product portfolio.

Impact:

• Drive the development of industry-leading SerDes solutions that enable next-generation high-speed communication interfaces.
• Enhance product competitiveness by delivering robust, low-power, and high-performance analog blocks for global customers.
• Accelerate time-to-market by proposing efficient design and verification strategies that streamline development cycles.
• Champion best practices in layout and design for reliability, contributing to high-yield and manufacturable solutions.
• Advance the technical expertise of the broader team through mentorship and technical leadership.
• Strengthen customer trust by delivering well-documented, silicon-proven solutions and providing expert technical support.
• Contribute to the continuous evolution of Synopsys’ analog and mixed-signal IP portfolio, ensuring ongoing leadership in the semiconductor industry.

Requirements:

• BS/BTech degree and 8+ years of experience in IC design, or MS/MTech/PhD with 6+ years of experience.
• In-depth familiarity with transistor-level circuit design and solid CMOS fundamentals.
• Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.
• Detailed design experience with several of the following: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillators, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
• Expertise in optimizing FinFET CMOS layout to minimize parasitic effects and local device mismatch.
• Awareness of ESD issues and design for reliability, including electromigration, IR-drop, and aging.
• Experience using EDA tools for schematic entry, physical layout, and design verification.
• Strong knowledge of SPICE simulators and simulation methodologies.
• Proficiency in Verilog-A for analog behavioral modeling and simulation control/data capture.
• Programming experience in TCL, Perl, C, Python, or MATLAB.

Team: You will join a high-impact analog/mixed-signal design team renowned for delivering state-of-the-art SerDes IP solutions. The team’s focus is on innovation, quality, and collaboration, working closely with digital design, layout, verification, and product engineering teams.

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