{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/virtuoso"},"x-facet":{"type":"skill","slug":"virtuoso","display":"Virtuoso","count":14},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c8818cbe-c70"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a highly skilled Layout Design Senior Engineer to join our team. As a Layout Design Senior Engineer, you will be responsible for developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below).</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below)</li>\n<li>Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements.</li>\n<li>Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles.</li>\n<li>Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues.</li>\n<li>Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area</li>\n<li>Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes.</li>\n<li>Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products.</li>\n<li>Ensuring robust and reliable IP performance through meticulous layout design and physical verification.</li>\n<li>Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more.</li>\n<li>Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader.</li>\n<li>Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.</li>\n<li>Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization.</li>\n<li>Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BTech/MTech degree in Electronics, Electrical, or related engineering discipline.</li>\n<li>2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below).</li>\n<li>Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies.</li>\n<li>Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies.</li>\n<li>Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation.</li>\n<li>Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms.</li>\n<li>Ability to work independently and collaboratively, managing multiple tasks and priorities.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR &amp; HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c8818cbe-c70","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93917039824","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout development","advanced process nodes","DRC","LVS","ERC","Antenna checks","physical verification","deep submicron effects","floorplan techniques","layout matching","ESD","latch-up prevention","EMIR analysis","DFM considerations","LEF generation","Cadence Virtuoso","Synopsys Custom Compiler"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:03.456Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout development, advanced process nodes, DRC, LVS, ERC, Antenna checks, physical verification, deep submicron effects, floorplan techniques, layout matching, ESD, latch-up prevention, EMIR analysis, DFM considerations, LEF generation, Cadence Virtuoso, Synopsys Custom Compiler"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b17a8dfe-137"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR &amp; HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills,both verbal and written,enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything.</p>\n<p>Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b17a8dfe-137","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93942161184","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"Competitive salaries","x-skills-required":["BTech/MTech degree in Electronics, Electrical, or related engineering discipline","2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below)","Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies","Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies","Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation"],"x-skills-preferred":["Cadence Virtuoso","Synopsys Custom Compiler","EDA platforms"],"datePosted":"2026-04-24T14:18:54.565Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BTech/MTech degree in Electronics, Electrical, or related engineering discipline, 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below), Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies, Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies, Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation, Cadence Virtuoso, Synopsys Custom Compiler, EDA platforms"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fa1cede5-336"},"title":"Analog Mixed Signal Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>Design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...</p>\n<p>Analyse and verify to make sure design meet all requirements of functionality, performance, area and reliability.</p>\n<p>Work closely with layout engineers to make sure layout quality. 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Perform mixed signal verification which combining both analog and digital blocks.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_fa1cede5-336","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-mixed-signal-design-engineer-hcmc/44408/94030515936","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS Analog design knowledge and techniques","Circuit design tools: SNSP Custom Designer, Cadence Virtuoso","Circuit simulation tools: Hspice or Spectre or Custom Sim...","Good understanding of layout effects on circuit performance","Familiar with writing design review presentations and circuit verification reports"],"x-skills-preferred":["Strong problem-solving abilities and keen attention to detail","Good verbal and written English communication skills","Highly responsible and self-motivated, with a strong sense of ownership over your work","Collaborative team player, open to feedback and eager to learn from others","Detail-oriented and methodical, always striving for accuracy and quality"],"datePosted":"2026-04-24T14:17:29.212Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS Analog design knowledge and techniques, Circuit design tools: SNSP Custom Designer, Cadence Virtuoso, Circuit simulation tools: Hspice or Spectre or Custom Sim..., Good understanding of layout effects on circuit performance, Familiar with writing design review presentations and circuit verification reports, Strong problem-solving abilities and keen attention to detail, Good verbal and written English communication skills, Highly responsible and self-motivated, with a strong sense of ownership over your work, Collaborative team player, open to feedback and eager to learn from others, Detail-oriented and methodical, always striving for accuracy and quality"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d0d01c2f-b91"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.</p>\n<p>Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.</p>\n<p>Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.</p>\n<p>Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.</p>\n<p>Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.</p>\n<p>Conducting design reviews and offering constructive feedback to enhance quality and performance.</p>\n<p>Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.</p>\n<p>Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.</p>\n<p>Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys&#39; IP products.</p>\n<p>Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.</p>\n<p>Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.</p>\n<p>Fostering collaboration across global teams, leading to improved methodologies and best practices.</p>\n<p>Maintaining the highest standards of quality, compliance, and performance in every design delivered.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d0d01c2f-b91","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/layout-design-sr-engineer/44408/93979726464","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BTech/MTech in Electrical Engineering, Electronics, or related field","2+ years of relevant experience in IC layout design, preferably in standard cell libraries","Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM)","Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs","Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:16:00.975Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BTech/MTech in Electrical Engineering, Electronics, or related field, 2+ years of relevant experience in IC layout design, preferably in standard cell libraries, Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_65b38286-e1d"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below)</li>\n<li>Design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements</li>\n<li>Perform DRC, LVS, ERC, Antenna checks, and ensure timely completion of verification cycles</li>\n<li>Apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues</li>\n<li>Collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area</li>\n<li>Troubleshoot and debug layout challenges, continually improving methodologies and design outcomes</li>\n<li>Document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Accelerate the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products</li>\n<li>Ensure robust and reliable IP performance through meticulous layout design and physical verification</li>\n<li>Drive innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more</li>\n<li>Contribute to the world&#39;s broadest portfolio of silicon IP, enhancing Synopsys&#39; position as a technology leader</li>\n<li>Reduce risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements</li>\n<li>Foster a culture of collaboration, accountability, and technical excellence within the team and across the organization</li>\n<li>Help shape the next wave of semiconductor advancements, powering smart devices and connected systems globally</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>B.Tech/M.Tech degree in Electronics, Electrical, or related engineering discipline</li>\n<li>2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below)</li>\n<li>Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies</li>\n<li>Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies</li>\n<li>Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation</li>\n<li>Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms</li>\n<li>Ability to work independently and collaboratively, managing multiple tasks and priorities</li>\n</ul>\n<p>Team:</p>\n<p>You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR &amp; HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world&#39;s most advanced chips and devices.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_65b38286-e1d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93930643616","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout development","advanced process nodes","DRC, LVS, ERC, Antenna checks","physical verification methodologies","deep submicron effects","floorplan techniques","layout matching in CMOS, FinFET, GAA technologies","ESD, latch-up prevention","EMIR analysis","DFM considerations","LEF generation","Cadence Virtuoso","Synopsys Custom Compiler"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:13:15.595Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout development, advanced process nodes, DRC, LVS, ERC, Antenna checks, physical verification methodologies, deep submicron effects, floorplan techniques, layout matching in CMOS, FinFET, GAA technologies, ESD, latch-up prevention, EMIR analysis, DFM considerations, LEF generation, Cadence Virtuoso, Synopsys Custom Compiler"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_47eb1938-db3"},"title":"Analog Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a passionate and detail-oriented engineer who thrives on solving complex technical challenges. Your expertise in analog and mixed-signal circuit design is matched by your drive to push the boundaries of data transmission speeds. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR &amp; HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.</p>\n<p>Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</p>\n<p>Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products. Ensuring robust and reliable IP performance through meticulous layout design and physical verification. Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more. Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader. Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements. Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization. Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.</p>\n<p>BTech/MTech degree in Electronics, Electrical, or related engineering discipline. 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below). Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies. Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies. Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation. Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms. Ability to work independently and collaboratively, managing multiple tasks and priorities.</p>\n<p>Analytical thinker with strong problem-solving and debugging skills. Self-motivated, accountable, and results-driven. Collaborative team player who fosters trust and open communication. Adaptable and eager to learn new technologies and methodologies. Effective communicator with excellent interpersonal skills. Committed to diversity, inclusion, and continuous improvement.</p>\n<p>You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR &amp; HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world&#39;s most advanced chips and devices.</p>\n<p>Rewards and Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_529617b7-a03","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93942161104","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DRC","LVS","ERC","Antenna checks","physical verification","layout matching","ESD","latch-up prevention","EMIR analysis","DFM considerations","LEF generation","Cadence Virtuoso","Synopsys Custom Compiler"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:08:58.635Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DRC, LVS, ERC, Antenna checks, physical verification, layout matching, ESD, latch-up prevention, EMIR analysis, DFM considerations, LEF generation, Cadence Virtuoso, Synopsys Custom Compiler"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d0dacac5-f8f"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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