Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:\nYou are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.
\nYou are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.
\nWhat You’ll Be Doing:\nSpecify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\nDevelop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\nDesign, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\nPerform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\nCollaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\nLeverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\nContribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.
\nThe Impact You Will Have:\nEnsure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\nDrive innovation in verification methodologies, setting new standards for efficiency and coverage.\nEnhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\nStrengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\nMentor and support junior engineers, fostering a culture of learning and continuous improvement.\nContribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.
\nWhat You’ll Need:\nBSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\nExpertise in developing HVL (System Verilog)-based verification environments and testbenches.\nStrong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\nProficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\nSolid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\nFamiliarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\nDemonstrated ability to work with functional coverage-driven methodologies and quality metric goals.
\nWho You Are:\nAnalytical thinker with strong problem-solving and debugging skills.\nExcellent verbal and written communication abilities.\nTeam player who thrives in collaborative, multi-site environments.\nProactive, self-motivated, and able to take initiative on challenging projects.\nDetail-oriented, quality-focused, and driven by a desire to excel.\nAdaptable and eager to continuously learn and apply new technologies.
\nThe Team You’ll Be A Part Of:\nYou will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.
\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
\nBenefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_455b32d6-da0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/ip-verification-usb-staff-engineer/44408/92684730560","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["System Verilog","UVM/OVM/VMM","HVL-based test environments","Industry-standard simulators (VCS, NC, MTI)","Debugging tools","Functional coverage-driven methodologies","Quality metric goals","MIPI-I3C","UFS","AMBA","Ethernet","DDR","PCIe","USB","Perl","TCL","Python","VIP development","Formal verification"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:02.691Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, UVM/OVM/VMM, HVL-based test environments, Industry-standard simulators (VCS, NC, MTI), Debugging tools, Functional coverage-driven methodologies, Quality metric goals, MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, USB, Perl, TCL, Python, VIP development, Formal verification"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e21ac2ad-394"},"title":"Principal Verification Engineer","description":"You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion for verification and a keen eye for detail. With a strong background in architecting verification environments for complex serial protocols, you are proficient in HVL (System Verilog) and have hands-on experience with industry-standard simulators. Your extensive experience includes developing and implementing test plans, extracting verification metrics, and coding for functional coverage. You are well-versed in verification methodologies such as VMM, OVM, and UVM, and have a solid understanding of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. Your familiarity with HDLs like Verilog and scripting languages such as Perl, TCL, and Python enhances your verification processes. You possess exceptional problem-solving skills, demonstrate high levels of initiative, and excel in written and oral communication. Your collaborative spirit enables you to work closely with RTL designers and seamlessly integrate into a global team of professional verification engineers, driving the next generation of connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you'll do
\nSpecifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.
\nPerforming verification tasks for IP cores, including test planning and environment coding at both unit and system levels.
\nDeveloping and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.
\nManaging regression and ensuring adherence to verification methodologies.
\nCollaborating closely with RTL designers and a global team of verification engineers.
\nWorking on next-generation connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you need
\nBSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.
\nExperience in architecting verification environments for complex serial protocols.
\nProficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.
\nExpertise in verification methodologies such as VMM, OVM, and UVM.
\nKnowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.
\nFamiliarity with Verilog and scripting languages such as Perl, TCL, and Python.
\nExperience with IP design and verification processes, including VIP development.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_e21ac2ad-394","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-verification-principal-engineer/44408/77023412560","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["HVL (System Verilog)","industry-standard simulators","verification methodologies","protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB","HDLs like Verilog","scripting languages such as Perl, TCL, and Python"],"x-skills-preferred":["VIP development"],"datePosted":"2025-12-22T12:04:28.502Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"HVL (System Verilog), industry-standard simulators, verification methodologies, protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB, HDLs like Verilog, scripting languages such as Perl, TCL, and Python, VIP development"}]}