{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/vhdl"},"x-facet":{"type":"skill","slug":"vhdl","display":"Vhdl","count":18},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_24665b43-498"},"title":"Senior ASIC Design Research Engineer","description":"<p>What Makes a Honda, is Who makes a Honda</p>\n<p>Honda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success. We strive to be a company that serves as a source of “power” that supports people around the world who are trying to do things based on their own initiative and that helps people expand their own potential. To this end, Honda strives to realize “the joy and freedom of mobility” by developing new technologies and an innovative approach to achieve a “zero environmental footprint.”</p>\n<p>We are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.</p>\n<p>If your goals and values align with Honda’s, we want you to join our team to Bring the Future!</p>\n<p>Job Purpose</p>\n<p>The Design Research Senior Engineer in the CoE Division conducts sensing for NA market and consumer trends, extract emerging technologies, formulate hypothesis and propose research initiatives to provide value toward NA Honda’s business direction.</p>\n<p>Key Accountabilities</p>\n<p>Conduct sensing for NA market and consumer trends, extract emerging technologies, and propose research initiatives.</p>\n<p>Continuously summarize and correlate sensing results and conclusions with internal stakeholders.</p>\n<p>Propose and carry out advanced research of emerging technologies utilizing Agile methodologies to prove hypothesis and define value with speed.</p>\n<p>Independently manage technical project resources while maintaining leading knowledge of state-of-the-art principles and theories.</p>\n<p>Propose new technology research themes for implementation into the Honda technical strategy through existing meeting structure and cadence.</p>\n<p>Develops and maintains strong relationships with internal and external research partners, industry experts, consortium members, university staff, and policy leaders to gather expertise and grow capability.</p>\n<p>Within defined technical pillar, identify root cause of highly technical and multidisciplinary problems and develop plans, designs, test systems, materials, techniques and processes to achieve objectives.</p>\n<p>Gain knowledge and expertise in emerging technologies, document findings, and inform others to grow the overall technical capability in North America.</p>\n<p>Qualifications, Experience, and Skills</p>\n<p>Minimum Educational Qualifications:</p>\n<p>Bachelor’s of Science in Engineering field or equivalent relevant experience in science/engineering research capacity.</p>\n<p>Minimum Experience:</p>\n<p>5 or more years with focus on digital chip architectures, benchmarking, open-source IP / ISA (RISC), ARM, familiarity with CPU / GPU / NPU, FPGAs, SoCs (System-on-Chip) and heterogenous integration.</p>\n<p>Familiarity with Assembly language.</p>\n<p>Other highly desirables: Prior experience with industry standard EDA tools (e.g. - Synopsys / Cadence &amp;c) for IC chip design. Exp in HDLs - e.g. - Verilog / VHDL</p>\n<p>Other Job-Specific Skills:</p>\n<p>Passion for research, solving hard problems, and challenging the status quo.</p>\n<p>Ability to learn new topics of apply principles to design and manufacturing challenges.</p>\n<p>Working knowledge of Agile processes and methodologies</p>\n<p>Design experiments to test hypothesis and prove them out.</p>\n<p>Utilize agile process and methodologies to conduct sensing and research initiatives</p>\n<p>Confidently make autonomous decisions bounded by the research mission and understanding of the company business model.</p>\n<p>Ability to efficiently manage resources to achieve project initiatives and schedules</p>\n<p>Clearly communicate new research and technology concepts and ideas to technical team members and management.</p>\n<p>Scientifically analyze data provided from tests and experiments to gather knowledge and understanding of the subject of research.</p>\n<p>Oversee overall research project schedule, budget, and direction.</p>\n<p>Workstyle</p>\n<p>This position will require the employee to work at our ADC, Raymond, OH office at least 4 days per workweek. One remote workday a week may be possible with prior departmental approval.</p>\n<p>What differentiates Honda and make us an employer of choice?</p>\n<p>Total Rewards:</p>\n<p>Competitive Base Salary (pay will be based on several variables that include, but not limited to geographic location, work experience, etc.)</p>\n<p>Paid Overtime</p>\n<p>Regional Bonus (when applicable)</p>\n<p>Industry-leading Benefit Plans (Medical, Dental, Vision, Rx)</p>\n<p>Paid time off, including vacation, holidays, shutdown</p>\n<p>Company Paid Short-Term and Long-Term Disability</p>\n<p>401(K) Plan with company match + additional contribution</p>\n<p>Relocation assistance (if eligible)</p>\n<p>Career Growth:</p>\n<p>Advancement Opportunities</p>\n<p>Career Mobility</p>\n<p>Education Reimbursement for Continued Learning</p>\n<p>Training and Development programs</p>\n<p>Additional Offerings:</p>\n<p>Tuition Assistance &amp; Student Loan Repayment</p>\n<p>Lifestyle Account</p>\n<p>Childcare Reimbursement Account</p>\n<p>Elder Care Support</p>\n<p>Wellbeing Program</p>\n<p>Community Service and Engagement Programs</p>\n<p>Product Programs</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_24665b43-498","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Honda","sameAs":"https://careers.honda.com","logo":"https://logos.yubhub.co/careers.honda.com.png"},"x-apply-url":"https://careers.honda.com/us/en/job/10679/Senior-ASIC-Design-Research-Engineer","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$90,200.00 - $112,700.00","x-skills-required":["digital chip architectures","benchmarking","open-source IP / ISA (RISC)","ARM","CPU / GPU / NPU","FPGAs","SoCs (System-on-Chip)","heterogenous integration","Assembly language","Synopsys / Cadence","Verilog / VHDL"],"x-skills-preferred":[],"datePosted":"2026-04-22T17:20:50.174Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Raymond"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Automotive","skills":"digital chip architectures, benchmarking, open-source IP / ISA (RISC), ARM, CPU / GPU / NPU, FPGAs, SoCs (System-on-Chip), heterogenous integration, Assembly language, Synopsys / Cadence, Verilog / VHDL","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":90200,"maxValue":112700,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9d8bfb7e-5fa"},"title":"Electrical Engineer","description":"<p>As a member of Rigetti&#39;s Control Systems team, you will design, develop, test, and deploy hardware that generates microwave pulses that control and read the qubits in our quantum computer.</p>\n<p>You&#39;ll collaborate closely with embedded software engineers, mechanical engineers, and physicists to deliver cutting-edge quantum control solutions. We&#39;re looking for someone who will deepen our team&#39;s expertise in low-noise mixed-signal board design , including specifying and designing critical circuit components such as low-noise power supply rails, precise clock distribution, and high-speed transceivers.</p>\n<p>We&#39;re seeking an experienced Electrical Engineer with a proven track record of leading projects across diverse teams and driving technical excellence in fast-paced, high-growth environments. The ideal candidate combines deep technical expertise with exceptional communication and leadership skills, effectively translating complex concepts for diverse audiences and influencing key design and delivery decisions. This individual fosters a culture of innovation, accountability, and rigorous engineering design, while mentoring others to achieve their highest potential.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Collaborate with internal and external team members to generate system requirements</li>\n<li>Capture circuit board schematic and layout for designs containing digital, analog, and RF components</li>\n<li>Create and execute test plans using oscilloscopes, spectrum analyzers, and VNAs (also qubits!)</li>\n</ul>\n<p>Required Qualifications:</p>\n<ul>\n<li>Previous experience working in startups or dynamic work environments</li>\n<li>BS or MS degree in EE, or equivalent, with 10+ years experience</li>\n<li>Ability to operate standard lab equipment (oscilloscopes, spectrum analyzers, and VNAs)</li>\n<li>Excellent communication skills and an ability to interact across different disciplines</li>\n<li>Demonstrated success taking designs from conception through the full design cycle, including manufacturing and test</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Experience with analog design and simulation (SPICE or equivalent)</li>\n<li>Knowledge of signal processing concepts: Nyquist zones, convolution, cross-correlation, numerically-controlled oscillators</li>\n<li>Focus on supporting other teams and a desire to jump in and help</li>\n<li>Exposure to Verilog/VHDL and digital hardware design and FPGA development</li>\n<li>Familiarity with Python scripting (especially scientific Python libraries like numpy and scipy)</li>\n<li>Understanding of RF design and test</li>\n</ul>\n<p>Additional Information:</p>\n<p>As engineering leaders, we value diversity and are committed to building a culture of inclusion to attract and engage innovative thinkers. Our technology, meant to serve all of humanity, cannot succeed if those who built it do not mirror the diversity of the communities we serve. Applications from women, minorities, and other under-represented groups are encouraged.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9d8bfb7e-5fa","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Rigetti Computing","sameAs":"https://www.rigetti.com","logo":"https://logos.yubhub.co/rigetti.com.png"},"x-apply-url":"https://jobs.lever.co/rigetti/b06e5caa-dc81-41b2-b1b0-8f118255c33a","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["EE","analog design","digital hardware design","FPGA development","Python scripting","RF design","test planning","lab equipment operation"],"x-skills-preferred":["analog design and simulation","signal processing concepts","Verilog/VHDL","numerically-controlled oscillators"],"datePosted":"2026-04-17T12:54:35.660Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Fremont"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"EE, analog design, digital hardware design, FPGA development, Python scripting, RF design, test planning, lab equipment operation, analog design and simulation, signal processing concepts, Verilog/VHDL, numerically-controlled oscillators"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ae1562a1-6be"},"title":"Senior FPGA Architect","description":"<p>Rigetti is seeking a Senior FPGA Architect to join the development of FPGA-based control hardware used to drive our quantum processors.</p>\n<p>In this role, you will define FPGA architectures, implement high-performance digital logic, and collaborate closely with hardware, firmware, and quantum engineering teams to build scalable, low-latency control systems.</p>\n<p>Key responsibilities include:\nDeveloping and improving a custom microprocessor responsible for waveform generation and critical logic to operate a quantum computer\nWorking closely with hardware, firmware, and software teams to define architecture, data flow, and interfaces\nImplementing, simulating, and verifying designs including DSP pipelines, control logic, and high-speed I/O\nOptimizing designs for latency, resource utilization, and robustness in production environments\nDeveloping and maintaining testbenches, verification flows, and CI\nSupporting bring-up, lab validation, and debugging in collaboration with Quantum Engineering on actual quantum computers\nContributing to the long-term roadmap for the architecture of Rigetti’s control systems.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ae1562a1-6be","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Rigetti Computing","sameAs":"https://www.rigetti.com","logo":"https://logos.yubhub.co/rigetti.com.png"},"x-apply-url":"https://jobs.lever.co/rigetti/efc17b70-a451-4aeb-8a37-70cb7201693b","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","VHDL","FPGA design","Digital signal processing","High-speed serial interfaces","Processor architecture design","Collaboration on cross-functional teams"],"x-skills-preferred":["RF/microwave or mixed-signal systems","ASIC design","Real-time control systems","Data acquisition","Instrumentation","Quantum computing","Test and measurement equipment","Scientific Python stack"],"datePosted":"2026-04-17T12:54:29.986Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, VHDL, FPGA design, Digital signal processing, High-speed serial interfaces, Processor architecture design, Collaboration on cross-functional teams, RF/microwave or mixed-signal systems, ASIC design, Real-time control systems, Data acquisition, Instrumentation, Quantum computing, Test and measurement equipment, Scientific Python stack"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_601e090b-a37"},"title":"FPGA Engineer","description":"<p>We are seeking a talented FPGA Engineer to design and implement high-performance digital solutions for advanced defense systems. This role supports mission-critical applications including radar, electronic warfare (EW), and communications requiring real-time processing and high-reliability hardware design.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Design, develop, and optimize FPGA-based digital systems for real-time defense applications</li>\n<li>Implement RTL designs (VHDL, Verilog, SystemVerilog) for high-speed data processing</li>\n<li>Perform simulation, synthesis, timing analysis, and timing closure</li>\n<li>Develop and integrate DSP algorithms in hardware (e.g., FFTs, filters, modulation)</li>\n<li>Interface with high-speed ADCs/DACs, RF front ends, and embedded processors</li>\n<li>Support hardware bring-up, debugging, and validation in lab environments</li>\n<li>Collaborate with RF, systems, and software engineers to ensure system performance</li>\n<li>Document designs, requirements, and verification results</li>\n</ul>\n<p><strong>Required Qualifications</strong></p>\n<ul>\n<li>Bachelor’s degree in Electrical or Computer Engineering (or related field)</li>\n<li>Minimum of 2 years&#39; professional experience within the aerospace &amp; defense industry</li>\n<li>Minimum 2 years&#39; experience using FPGA toolchains (Xilinx Vivado, Intel Quartus)</li>\n<li>Proficiency in HDLs (VHDL, Verilog, or SystemVerilog)</li>\n<li>Strong understanding of digital design fundamentals (timing, clock domains, pipelining)</li>\n<li>Experience with simulation/verification tools (ModelSim, Questa, etc.)</li>\n<li>Ability to obtain and maintain a U.S. security clearance</li>\n</ul>\n<p><strong>ITAR Regulations</strong></p>\n<ul>\n<li>To conform to U.S. Government technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicant must be a US Citizen, Green Card holder, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.</li>\n</ul>\n<p><strong>Bonus Points</strong></p>\n<ul>\n<li>Experience with defense systems (radar, EW, communications)</li>\n<li>Knowledge of digital signal processing (DSP) implementation and fixed-point math</li>\n<li>Proficient in scripting languages (Tcl, bash, Python)</li>\n<li>Familiarity with embedded software integration on SoCs</li>\n<li>Experience with high-speed interfaces (JESD204, PCIe, Ethernet, DDR)</li>\n<li>Familiarity with SoC platforms (e.g., Xilinx Zynq, RFSoC)</li>\n<li>Understanding of RF signal chains and systems</li>\n</ul>\n<p><strong>Additional Information</strong></p>\n<p>CX2 is a next-generation defense technology company securing spectrum dominance for the United States and its allies. We build AI-enabled hardware and software platforms to detect, disrupt, and defend the electromagnetic spectrum across land, air, sea, and space. Our systems are deployed in the most contested operational environments in the world. We’re backed by leading venture investors in the defense ecosystem and led by founders with track records at Meta, SpaceX, Epirus, and the U.S. Department of Defense.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_601e090b-a37","directApply":true,"hiringOrganization":{"@type":"Organization","name":"CX2","sameAs":"https://cx2.com/","logo":"https://logos.yubhub.co/cx2.com.png"},"x-apply-url":"https://jobs.lever.co/cx2/e8f0fee8-d95e-4d7b-a18d-83fd86dfc8d2","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["FPGA","VHDL","Verilog","SystemVerilog","Xilinx Vivado","Intel Quartus","digital design fundamentals","simulation/verification tools","U.S. security clearance"],"x-skills-preferred":["defense systems","digital signal processing","scripting languages","embedded software integration","high-speed interfaces","SoC platforms","RF signal chains"],"datePosted":"2026-04-17T12:28:34.111Z","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"FPGA, VHDL, Verilog, SystemVerilog, Xilinx Vivado, Intel Quartus, digital design fundamentals, simulation/verification tools, U.S. security clearance, defense systems, digital signal processing, scripting languages, embedded software integration, high-speed interfaces, SoC platforms, RF signal chains"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f9b4dd6-6f1"},"title":"Emulation Applications Engineer, Sr. Staff","description":"<p>We currently have an opening for an Emulation Applications Engineer, Sr. Staff to join our team. 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Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/29/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a forward-thinking engineer with a passion for leveraging cutting-edge AI technologies to revolutionize electronic design automation and verification. You thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your experience in verification frontend flows and AI/ML frameworks enables you to bridge the gap between traditional engineering practices and intelligent automation. You are comfortable working across diverse teams, collaborating with design, verification, CAD, and methodology experts to identify impactful automation opportunities. You possess strong analytical skills, enabling you to dissect complex verification challenges and develop scalable GenAI solutions. Your commitment to professional growth is evident in your eagerness to stay current with the latest advancements in LLMs, GenAI, and verification technology. With a keen eye for detail and a drive to deliver high-quality results, you are adept at integrating AI-driven capabilities into established workflows, elevating productivity and efficiency. You value inclusivity and diverse perspectives, and you are motivated by the opportunity to shape the future of engineering through innovative, intelligent solutions.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Develop and deploy LLM/GenAI-based solutions to enhance verification productivity across static, formal, and simulation-based flows in EDA tools.</li>\n</ul>\n<ul>\n<li>Collaborate cross-functionally with design, verification, CAD, and methodology teams to identify high-impact areas for AI-assisted automation.</li>\n</ul>\n<ul>\n<li>Build tools and frameworks to generate or refine assertions, constraints, checkers, and test intent, summarize design/spec content, and analyze logs, failures, and coverage gaps.</li>\n</ul>\n<ul>\n<li>Integrate LLM-driven capabilities into existing verification flows, tools, and automation infrastructure, ensuring seamless adoption.</li>\n</ul>\n<ul>\n<li>Develop and maintain scripts, data pipelines, and evaluation frameworks for AI-assisted verification use cases.</li>\n</ul>\n<ul>\n<li>Stay current with advances in LLMs, GenAI, verification technology, and digital design methodologies to inform best practices.</li>\n</ul>\n<ul>\n<li>Participate in technical reviews and help define scalable AI adoption strategies within verification environments.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate verification planning, setup, and closure, enabling faster time-to-market for complex digital designs.</li>\n</ul>\n<ul>\n<li>Enhance productivity and efficiency for engineering teams through intelligent automation and AI-driven solutions.</li>\n</ul>\n<ul>\n<li>Reduce manual effort and potential errors in verification by automating routine and complex tasks.</li>\n</ul>\n<ul>\n<li>Improve coverage analysis, debug processes, and testbench/content generation, resulting in higher quality silicon chips.</li>\n</ul>\n<ul>\n<li>Drive innovation in verification methodologies by integrating state-of-the-art GenAI capabilities.</li>\n</ul>\n<ul>\n<li>Foster cross-functional collaboration, contributing to robust and scalable verification strategies.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ leadership in EDA technology and AI-driven engineering solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.</li>\n</ul>\n<ul>\n<li>5–8 years of experience in EDA software development with prior experience in developing GenAI-based tools.</li>\n</ul>\n<ul>\n<li>Hands-on experience with LLM/GenAI or AI/ML frameworks/tools such as PyTorch, TensorFlow, Hugging Face, LangChain, or equivalent.</li>\n</ul>\n<ul>\n<li>Proficiency in C++ and familiarity with Verilog, VHDL, or SystemVerilog.</li>\n</ul>\n<ul>\n<li>Strong understanding of verification frontend methodologies, including static analysis (CDC/RDC/Lint), formal/property-based verification, and simulation bring-up/debug.</li>\n</ul>\n<ul>\n<li>Experience with cloud or scalable compute platforms (AWS, GCP, Azure) is a plus.</li>\n</ul>\n<ul>\n<li>Familiarity with Agile development methodologies is desirable.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a passion for applying AI to real-world engineering challenges.</li>\n</ul>\n<ul>\n<li>Effective communicator, able to convey complex technical concepts to diverse audiences.</li>\n</ul>\n<ul>\n<li>Collaborative team player who thrives in cross-functional environments.</li>\n</ul>\n<ul>\n<li>Strong problem-solving abilities and analytical mindset.</li>\n</ul>\n<ul>\n<li>Adaptable, eager to learn, and comfortable with ambiguity in fast-evolving technology landscapes.</li>\n</ul>\n<ul>\n<li>Self-driven and proactive, with a commitment to delivering impactful solutions.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a collaborative and innovative engineering team focused on advancing verification productivity through AI-driven solutions. The team works closely with design, verification, CAD, and methodology groups to identify and implement high-impact automation strategies. Together, you will drive the adoption of GenAI technologies within Synopsys’ EDA ecosystem, fostering a culture of continuous improvement and technological excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>Get an idea of what your daily routine <strong>around the office</strong> can be like</strong></p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_90f641e9-987","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/ai-llm-software-developer-verification-frontend/44408/93375604432","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["LLM/GenAI","PyTorch","TensorFlow","Hugging Face","LangChain","C++","Verilog","VHDL","SystemVerilog","static analysis","formal/property-based verification","simulation bring-up/debug"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:21.052Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"LLM/GenAI, PyTorch, TensorFlow, Hugging Face, LangChain, C++, Verilog, VHDL, SystemVerilog, static analysis, formal/property-based verification, simulation bring-up/debug"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a4490a5f-125"},"title":"Sr Staff Application Engineer - VCS Simulation","description":"<p><strong>Job Summary</strong></p>\n<p>As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&amp;D to ensure successful adoption and integration.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead customer deployments of VCS simulation technology, working closely with field teams and R&amp;D to ensure successful adoption and integration.</li>\n<li>Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.</li>\n<li>Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.</li>\n<li>Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.</li>\n<li>Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.</li>\n<li>Interface directly with customers, product validation, and R&amp;D teams to propose solutions and suggest improvements in implementation and validation processes.</li>\n<li>Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.</li>\n<li>Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.</li>\n<li>Enhance Synopsys&#39; product offerings by providing actionable feedback from customer engagements and competitive benchmarking.</li>\n<li>Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.</li>\n<li>Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.</li>\n<li>Contribute to the growth of Synopsys&#39; leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.</li>\n<li>Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.</li>\n<li>Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.</li>\n<li>Proven experience in debugging simulation mismatches and verification flows.</li>\n<li>Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.</li>\n<li>Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Excellent written and oral communication skills, comfortable interfacing with global teams and customers.</li>\n<li>Collaborative team player with a proactive and innovative mindset.</li>\n<li>Detail-oriented and organized, able to manage multiple tasks and priorities.</li>\n<li>Motivated self-starter with strong problem-solving abilities.</li>\n<li>Adaptable and open to travel, eager to learn and grow in a fast-paced environment.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&amp;D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a4490a5f-125","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/sr-staff-application-engineer-vcs-simulation/44408/93232526272","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["verification technologies","simulation","UVM","SVA","LRM","HDL languages","Verilog","VHDL","SystemVerilog","digital design fundamentals","advanced scripting skills","Perl","TCL","Make","Shell","UNIX environments","Synopsys EDA tools","SpyGlass","VC SpyGlass","Verdi"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:36.950Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"verification technologies, simulation, UVM, SVA, LRM, HDL languages, Verilog, VHDL, SystemVerilog, digital design fundamentals, advanced scripting skills, Perl, TCL, Make, Shell, UNIX environments, Synopsys EDA tools, SpyGlass, VC SpyGlass, Verdi"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1fe3012d-71e"},"title":"R&D Staff Software Engineer - Simulation","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification, and manufacturing.</p>\n<p>We are seeking a seasoned engineer with a passion for pushing the boundaries of technology to join our team. With 5-8 years of experience, you will bring a wealth of knowledge in software architecture and excel in C/C++ software development, digital simulation, compiler optimizations, and design patterns, data structures, and algorithms.</p>\n<p>As a member of our performance team in Digital Simulation, you will work closely with both local and global teams to drive technological advancements and achieve project goals.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Designing, developing, and troubleshooting core algorithms for compiler.</li>\n<li>Collaborating with local and global teams to enhance runtime performance for verilog compiler.</li>\n<li>Engaging in pure technical roles focused on software development and architecture.</li>\n<li>Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation.</li>\n<li>Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Driving technological innovation in chip design and verification.</li>\n<li>Enhancing the performance and quality of simulation tools used globally.</li>\n<li>Solving complex compiler optimizations problems to improve simulation performance.</li>\n<li>Collaborating with cross-functional teams to achieve project milestones.</li>\n<li>Pioneering new software architectures that set industry standards.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Strong hands-on experience in C/C++ based software development.</li>\n<li>Deep understanding of design patterns, data structures, algorithms, and programming concepts.</li>\n<li>Knowledge of ASIC design flow and EDA tools and methodologies.</li>\n<li>Proficiency in Verilog, SystemVerilog, and VHDL HDL.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Highly enthusiastic and energetic team player with excellent communication skills.</li>\n<li>Strong desire to learn and explore new technologies.</li>\n<li>Effective problem-solver with a keen analytical mind.</li>\n<li>Experienced in working on Unix/Linux platforms.</li>\n<li>Adept at using developer tools such as gdb and Valgrind.</li>\n</ul>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1fe3012d-71e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/r-and-d-staff-software-engineer-simulation/44408/88147323248","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["C/C++","Digital simulation","Compiler optimizations","Design patterns","Data structures","Algorithms","Verilog","SystemVerilog","VHDL"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:07.099Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++, Digital simulation, Compiler optimizations, Design patterns, Data structures, Algorithms, Verilog, SystemVerilog, VHDL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f7e7aee-bc7"},"title":"Verification Design Lead","description":"<p>At Synopsys, we drive innovations that shape how we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. As leaders in chip design, verification, and IP integration, we empower the creation of high-performance silicon chips and software.</p>\n<p>You are an experienced verification architect who thrives on technical leadership and mentoring others. You excel in digital design and verification, enjoy collaborating with global teams, and are motivated by delivering high-quality solutions. Your expertise includes System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. You’re proactive, inclusive, and passionate about process improvement and innovation.</p>\n<p>Responsibilities:\nProvide technical leadership and mentor junior engineers.\nCollaborate with cross-functional, global teams.\nDefine and implement advanced verification plans and methodologies.\nDevelop and maintain UVM-based testbenches.\nDrive process improvements for verification efficiency.\nAutomate verification flows using scripting and programming skills.</p>\n<p>The Impact You Will Have:\nEnsure robust verification for complex ASIC and IP designs.\nSupport first-silicon success and faster time-to-market.\nElevate team skills and technical excellence.\nChampion best verification practices and tools.\nEnhance collaboration across global teams.\nPromote continuous improvement in verification processes.</p>\n<p>What You’ll Need:\nBSEE or MSEE with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL.\nExpertise in UVM and coverage-driven RTL verification.\nProficiency in scripting and programming (Python, Perl, C/C++).\nAbility to define verification plans and architect testbenches.\nExperience with 200G SerDes verification is an asset.</p>\n<p>Who You Are:\nCollaborative leader and effective communicator.\nMentor who empowers others.\nAnalytical, detail-oriented problem solver.\nAdaptable and innovative.</p>\n<p>The Team You’ll Be A Part Of:\nJoin a diverse, world-class engineering team dedicated to delivering industry-leading verification solutions for next-generation semiconductor products.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2f7e7aee-bc7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ottawa/verification-design-lead-14733/44408/91320791920","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["System Verilog","Verilog","VHDL","UVM","C/C++"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:41.079Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ottawa"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, Verilog, VHDL, UVM, C/C++"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6d8de738-1a7"},"title":"Staff Hardware Engineer","description":"<p>We are seeking a skilled Staff Hardware Engineer to join our team in Cairo. As a Staff Hardware Engineer, you will be responsible for defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development. You will develop and optimize RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability. You will also drive the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.</li>\n<li>Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.</li>\n<li>Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.</li>\n<li>Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.</li>\n</ul>\n<p>As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.</p>\n<p>Requirements include:</p>\n<ul>\n<li>BS/MS in Computer Science, Electrical Engineering, or a related field.</li>\n<li>5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.</li>\n<li>Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.</li>\n<li>Expertise in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.</li>\n<li>Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.</li>\n<li>Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).</li>\n<li>Strong logical thinking and problem-solving abilities, with a keen attention to detail.</li>\n</ul>\n<p>Benefits include:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6d8de738-1a7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/cairo/staff-hardware-engineer/44408/93286401152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design and verification","Xilinx UltraScale, UltraScale+, and Versal FPGAs","Hardware Description Languages (VERILOG, VHDL, SystemVerilog)","Industry-standard EDA tools and methodologies","FPGA flows and tools (Vivado)","Unix/Linux environments","Scripting languages (Shell, Perl, Python, TCL)","HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:19:26.758Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Cairo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, Xilinx UltraScale, UltraScale+, and Versal FPGAs, Hardware Description Languages (VERILOG, VHDL, SystemVerilog), Industry-standard EDA tools and methodologies, FPGA flows and tools (Vivado), Unix/Linux environments, Scripting languages (Shell, Perl, Python, TCL), HDL simulation, emulation, and prototyping platforms (Zebu, HAPS)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bf6e7034-9fc"},"title":"Principal Simulation R&D Software Engineer","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are seeking a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. 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