Honda has a clear vision for the future, and it’s a joyful one. We are looking for individuals with the skills, courage, persistence, and dreams that will help us reach our future-focused goals. At our core is innovation. Honda is constantly innovating and developing solutions to drive our business with record success. We strive to be a company that serves as a source of “power” that supports people around the world who are trying to do things based on their own initiative and that helps people expand their own potential. To this end, Honda strives to realize “the joy and freedom of mobility” by developing new technologies and an innovative approach to achieve a “zero environmental footprint.”

We are looking for qualified individuals with diverse backgrounds, experiences, continuous improvement values, and a strong work ethic to join our team.

If your goals and values align with Honda’s, we want you to join our team to Bring the Future!

Job Purpose

The Design Research Senior Engineer in the CoE Division conducts sensing for NA market and consumer trends, extract emerging technologies, formulate hypothesis and propose research initiatives to provide value toward NA Honda’s business direction.

Key Accountabilities

Conduct sensing for NA market and consumer trends, extract emerging technologies, and propose research initiatives.

Continuously summarize and correlate sensing results and conclusions with internal stakeholders.

Propose and carry out advanced research of emerging technologies utilizing Agile methodologies to prove hypothesis and define value with speed.

Independently manage technical project resources while maintaining leading knowledge of state-of-the-art principles and theories.

Propose new technology research themes for implementation into the Honda technical strategy through existing meeting structure and cadence.

Develops and maintains strong relationships with internal and external research partners, industry experts, consortium members, university staff, and policy leaders to gather expertise and grow capability.

Within defined technical pillar, identify root cause of highly technical and multidisciplinary problems and develop plans, designs, test systems, materials, techniques and processes to achieve objectives.

Gain knowledge and expertise in emerging technologies, document findings, and inform others to grow the overall technical capability in North America.

Qualifications, Experience, and Skills

Minimum Educational Qualifications:

Bachelor’s of Science in Engineering field or equivalent relevant experience in science/engineering research capacity.

Minimum Experience:

5 or more years with focus on digital chip architectures, benchmarking, open-source IP / ISA (RISC), ARM, familiarity with CPU / GPU / NPU, FPGAs, SoCs (System-on-Chip) and heterogenous integration.

Familiarity with Assembly language.

Other highly desirables: Prior experience with industry standard EDA tools (e.g. - Synopsys / Cadence &c) for IC chip design. Exp in HDLs - e.g. - Verilog / VHDL

Other Job-Specific Skills:

Passion for research, solving hard problems, and challenging the status quo.

Ability to learn new topics of apply principles to design and manufacturing challenges.

Working knowledge of Agile processes and methodologies

Design experiments to test hypothesis and prove them out.

Utilize agile process and methodologies to conduct sensing and research initiatives

Confidently make autonomous decisions bounded by the research mission and understanding of the company business model.

Ability to efficiently manage resources to achieve project initiatives and schedules

Clearly communicate new research and technology concepts and ideas to technical team members and management.

Scientifically analyze data provided from tests and experiments to gather knowledge and understanding of the subject of research.

Oversee overall research project schedule, budget, and direction.

Workstyle

This position will require the employee to work at our ADC, Raymond, OH office at least 4 days per workweek. One remote workday a week may be possible with prior departmental approval.

What differentiates Honda and make us an employer of choice?

Total Rewards:

Competitive Base Salary (pay will be based on several variables that include, but not limited to geographic location, work experience, etc.)

Paid Overtime

Regional Bonus (when applicable)

Industry-leading Benefit Plans (Medical, Dental, Vision, Rx)

Paid time off, including vacation, holidays, shutdown

Company Paid Short-Term and Long-Term Disability

401(K) Plan with company match + additional contribution

Relocation assistance (if eligible)

Career Growth:

Advancement Opportunities

Career Mobility

Education Reimbursement for Continued Learning

Training and Development programs

Additional Offerings:

Tuition Assistance & Student Loan Repayment

Lifestyle Account

Childcare Reimbursement Account

Elder Care Support

Wellbeing Program

Community Service and Engagement Programs

Product Programs

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You'll collaborate closely with embedded software engineers, mechanical engineers, and physicists to deliver cutting-edge quantum control solutions. We're looking for someone who will deepen our team's expertise in low-noise mixed-signal board design , including specifying and designing critical circuit components such as low-noise power supply rails, precise clock distribution, and high-speed transceivers.

We're seeking an experienced Electrical Engineer with a proven track record of leading projects across diverse teams and driving technical excellence in fast-paced, high-growth environments. The ideal candidate combines deep technical expertise with exceptional communication and leadership skills, effectively translating complex concepts for diverse audiences and influencing key design and delivery decisions. This individual fosters a culture of innovation, accountability, and rigorous engineering design, while mentoring others to achieve their highest potential.

Responsibilities:

• Collaborate with internal and external team members to generate system requirements
• Capture circuit board schematic and layout for designs containing digital, analog, and RF components
• Create and execute test plans using oscilloscopes, spectrum analyzers, and VNAs (also qubits!)

Required Qualifications:

• Previous experience working in startups or dynamic work environments
• BS or MS degree in EE, or equivalent, with 10+ years experience
• Ability to operate standard lab equipment (oscilloscopes, spectrum analyzers, and VNAs)
• Excellent communication skills and an ability to interact across different disciplines
• Demonstrated success taking designs from conception through the full design cycle, including manufacturing and test

Preferred Qualifications:

• Experience with analog design and simulation (SPICE or equivalent)
• Knowledge of signal processing concepts: Nyquist zones, convolution, cross-correlation, numerically-controlled oscillators
• Focus on supporting other teams and a desire to jump in and help
• Exposure to Verilog/VHDL and digital hardware design and FPGA development
• Familiarity with Python scripting (especially scientific Python libraries like numpy and scipy)
• Understanding of RF design and test

Additional Information:

As engineering leaders, we value diversity and are committed to building a culture of inclusion to attract and engage innovative thinkers. Our technology, meant to serve all of humanity, cannot succeed if those who built it do not mirror the diversity of the communities we serve. Applications from women, minorities, and other under-represented groups are encouraged.

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In this role, you will define FPGA architectures, implement high-performance digital logic, and collaborate closely with hardware, firmware, and quantum engineering teams to build scalable, low-latency control systems.

Key responsibilities include: Developing and improving a custom microprocessor responsible for waveform generation and critical logic to operate a quantum computer Working closely with hardware, firmware, and software teams to define architecture, data flow, and interfaces Implementing, simulating, and verifying designs including DSP pipelines, control logic, and high-speed I/O Optimizing designs for latency, resource utilization, and robustness in production environments Developing and maintaining testbenches, verification flows, and CI Supporting bring-up, lab validation, and debugging in collaboration with Quantum Engineering on actual quantum computers Contributing to the long-term roadmap for the architecture of Rigetti’s control systems.

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Key Responsibilities

• Design, develop, and optimize FPGA-based digital systems for real-time defense applications
• Implement RTL designs (VHDL, Verilog, SystemVerilog) for high-speed data processing
• Perform simulation, synthesis, timing analysis, and timing closure
• Develop and integrate DSP algorithms in hardware (e.g., FFTs, filters, modulation)
• Interface with high-speed ADCs/DACs, RF front ends, and embedded processors
• Support hardware bring-up, debugging, and validation in lab environments
• Collaborate with RF, systems, and software engineers to ensure system performance
• Document designs, requirements, and verification results

Required Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (or related field)
• Minimum of 2 years' professional experience within the aerospace & defense industry
• Minimum 2 years' experience using FPGA toolchains (Xilinx Vivado, Intel Quartus)
• Proficiency in HDLs (VHDL, Verilog, or SystemVerilog)
• Strong understanding of digital design fundamentals (timing, clock domains, pipelining)
• Experience with simulation/verification tools (ModelSim, Questa, etc.)
• Ability to obtain and maintain a U.S. security clearance

ITAR Regulations

• To conform to U.S. Government technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicant must be a US Citizen, Green Card holder, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

Bonus Points

• Experience with defense systems (radar, EW, communications)
• Knowledge of digital signal processing (DSP) implementation and fixed-point math
• Proficient in scripting languages (Tcl, bash, Python)
• Familiarity with embedded software integration on SoCs
• Experience with high-speed interfaces (JESD204, PCIe, Ethernet, DDR)
• Familiarity with SoC platforms (e.g., Xilinx Zynq, RFSoC)
• Understanding of RF signal chains and systems

Additional Information

CX2 is a next-generation defense technology company securing spectrum dominance for the United States and its allies. We build AI-enabled hardware and software platforms to detect, disrupt, and defend the electromagnetic spectrum across land, air, sea, and space. Our systems are deployed in the most contested operational environments in the world. We’re backed by leading venture investors in the defense ecosystem and led by founders with track records at Meta, SpaceX, Epirus, and the U.S. Department of Defense.

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative environments. You have a proven track record in RTL design and verification, and you are excited about contributing to cutting-edge technology. With your extensive expertise, you can handle complex and unique issues, often requiring innovative solutions. You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.

What You’ll Be Doing:

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.
• Developing and executing comprehensive test plans to verify the functionality and performance of your designs.
• Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.
• Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.
• Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.

The Impact You Will Have:

• Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.
• Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.
• Enhancing the overall quality and performance of Synopsys' products through meticulous design and verification processes.
• Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.
• Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.
• Contributing to Synopsys' reputation as a leader in the semiconductor industry through your expertise and innovative solutions.

What You’ll Need:

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.
• Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.
• Experience with power analysis and RTL level power optimization techniques.
• Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Who You Are:

• A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.
• A strategic thinker with the ability to implement goals that have a direct impact on department results.
• A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.
• A collaborative team player who thrives in dynamic and fast-paced environments.
• A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Staff Engineer in ASIC Digital Design, you will be responsible for architecting and designing embedded RISC microprocessor IP at both architectural and RTL levels. You will write comprehensive high-level architecture and micro-architecture specifications for processor designs, optimize designs for performance, speed, area, and power, and develop standalone Verilog testbenches to verify modules and ensure robust functionality.

You will also debug design issues and collaborate closely with verification teams to resolve bugs and improve quality. Additionally, you will maintain existing processor product lines and derivative products, ensuring ongoing reliability and innovation.

You will work closely with multi-site, multi-time zone, and multi-cultural teams on aspects like design, implementation, physical design, and verification. You will also develop and manage project plans, working closely with program managers to align deliverables and timelines.

As a member of the Synopsys ARC Processor hardware team, you will contribute to the advancement of processor technology and work on architectural design, implementation, verification, and maintenance of processor products that drive the next wave of intelligent devices.

You will join a team of passionate engineers dedicated to advancing processor technology and collaborate with global teams to deliver innovative solutions. You will work on architectural design, implementation, verification, and maintenance of processor products that drive the next wave of intelligent devices.

You will be responsible for driving improvements in design methodology and verification processes, raising the bar for quality and speed of delivery. You will also facilitate seamless collaboration across global teams, fostering a culture of shared knowledge and success.

You will support the growth and maintenance of Synopsys' processor product portfolio, ensuring market competitiveness. You will enable customers to build smarter, faster, and more energy-efficient devices by delivering optimized processor designs.

You will contribute to the evolution of silicon chip technology that powers intelligent systems worldwide.

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As a Senior Staff Engineer in RTL Design and Verification, you will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance.

You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.

You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

You will accelerate the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions.

You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy. You will enable successful integration of advanced 3D-IC technologies, expanding Synopsys' leadership in the market.

You will foster strong customer relationships through technical expertise and responsive support. You will contribute to a culture of excellence and continuous learning within the engineering team.

To succeed in this role, you will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will require 8+ years of hands-on experience in RTL design and verification.

You will need proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. You will need experience working in Unix/Linux environments.

You will need strong debugging and problem-solving skills, especially in complex chip design environments. You will need excellent written and verbal communication skills in English.

Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus. Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.

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Your key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.

To be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

As a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.

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At Synopsys, we value diversity and inclusion. We are committed to creating a workplace where everyone feels valued and supported to do their best work.

Responsibilities: Assist SiCADA instructor in developing VDM (Verilog Design Methodology) & ADV (Advanced Design Verification) homework specifications. Assist in reviewing ADV course materials, including SVTB (SystemVerilog Testbench) and UVM (Universal Verification Methodology), and update the course content. Serve as a teaching assistant for the VDM and ADV courses, helping to answer student questions and grade assignments. Support SoC implementation course especially STA and UPF teaching assistance if possible.

Benefits: Professional development opportunities Collaborative and dynamic work environment Flexible work arrangements

Hiring Journey at Synopsys: Apply Phone Screen Interview Offer Onboarding Welcome!

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Your responsibilities will include:

• Architecting and optimizing high-performance simulation kernels for the Synopsys VCS RTL simulator using advanced C++ techniques.
• Exploring and implementing GPU acceleration strategies with CUDA to significantly reduce simulation runtimes for customers.
• Leveraging deep knowledge of Verilog/SystemVerilog LRM to ensure accurate and reliable simulation across diverse design environments.
• Integrating AI-powered tools (such as Cursor, GitHub Copilot, and generative AI assistants) to automate code generation and debugging processes.
• Mentoring and guiding junior engineers, fostering skills development and technical growth within the team.
• Collaborating with distributed R&D teams to maintain Synopsys' leadership and drive innovation in the EDA industry.

As a senior staff engineer, you will have a significant impact on the company's success. You will be responsible for driving the evolution of the world's fastest Verilog simulator, setting new industry standards for performance and reliability. You will also empower customers to achieve greater productivity and efficiency through advanced simulation capabilities and reduced runtimes.

To be successful in this role, you will need to have:

• 8-10 years of relevant experience.
• Expert-level proficiency in C++ with proven experience in performance-critical software development.
• Deep understanding of Verilog/SystemVerilog Language Reference Manuals (LRM) and simulation methodologies.
• Hands-on experience with GPU programming, especially using CUDA for parallel acceleration.
• Familiarity with AI-powered development tools such as Cursor, GitHub Copilot, and generative AI assistants.
• Strong architectural design skills and ability to analyze and optimize complex software systems.
• Experience in mentoring and guiding junior engineers within an R&D environment.

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You will work closely with customers, Sales, R&D, and field teams to help them adopt and deploy Synopsys Verification solutions.

Responsibilities

• Engage directly with customers to understand their verification needs
• Support pre-sales activities: demos, technical evaluations, benchmarks, methodology guidance
• Improve customer verification flows and testbench architectures
• Debug RTL/gate-level simulation issues and SystemVerilog/UVM environments
• Analyse functional and code coverage
• Develop and debug SystemVerilog assertions
• Collaborate with Sales to grow adoption and identify new opportunities
• Act as the technical voice of the customer to R&D

Requirements

• Typically requires 8–13 years of relevant experience
• Strong knowledge of Verilog/SystemVerilog, UVM, coverage, and assertions
• Experience in customer interaction, pre-sales, or technical support is a plus
• Strong problem-solving and communication skills
• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field

The Team You’ll Be A Part Of

You’ll join a dynamic, Theale based Customer Application Services team dedicated to delivering world-class technical support and solutions for leading semiconductor companies.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.

You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.

You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks. Performing digital design validation and functional verification at both block and SoC levels. Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs. Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing. Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance. Utilizing and scripting in languages such as Tcl to automate design and verification workflows. Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides.

Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies. Shape the evolution of embedded memory test and SLM architectures that power next-generation devices. Drive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products. Enhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support. Contribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks. Mentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth. Influence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization. Support strategic decision-making by providing technical insights and market-driven recommendations.

2-4 years of relevant experience in ASIC digital design and verification. Proficiency in RTL simulation, logic synthesis, and timing verification tools. Strong understanding of DFT architectures. Familiarity with debug tools such as Verdi and workflows for performance analysis. Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl. Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.

Analytical thinker with exceptional problem-solving skills. Effective communicator, able to collaborate across disciplines and with external partners. Proactive, self-motivated, and adaptable in fast-paced environments. Committed to quality, detail, and continuous learning. Team player who values diversity, inclusion, and mentorship. Customer-focused, dedicated to delivering timely and effective solutions.

You'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Responsibilities:

• Collaborate with R&D architects and customers on hardware-assisted verification products.

• Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.

• Define test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.

• Become an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.

• Leverage your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.

• Adapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.

• Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.

The Impact You Will Have:

• Enhance Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.

• Improve the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.

• Provide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.

• Ensure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.

• Support the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.

• Facilitate the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.

What You’ll Need:

• BSEE/MS with 7+ years of related experience.

• Expertise in Emulation and/or Prototyping flows, systems, and methodologies.

• Strong proficiency in Verilog, System Verilog, and VHDL.

• Understanding of verification concepts and experience with functional simulators.

• Experience with scripting languages.

• Knowledge in Simulation flows, Assertion, DPI, and Transactors.

• Complex problem-solving and debugging skills.

• Strong communication skills and the ability to interact with customers and peers.

• Knowledge in synthesis and timing analysis concepts (preferred).

• Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).

• Experience with Xilinx & Altera architecture and toolchains (preferred).

• Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

What You’ll Be Doing:

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

The Impact You Will Have:

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

What You’ll Need:

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

Who You Are:

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

The Team You’ll Be A Part Of:

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.

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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Description

Date posted: 03/29/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a forward-thinking engineer with a passion for leveraging cutting-edge AI technologies to revolutionize electronic design automation and verification. You thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your experience in verification frontend flows and AI/ML frameworks enables you to bridge the gap between traditional engineering practices and intelligent automation. You are comfortable working across diverse teams, collaborating with design, verification, CAD, and methodology experts to identify impactful automation opportunities. You possess strong analytical skills, enabling you to dissect complex verification challenges and develop scalable GenAI solutions. Your commitment to professional growth is evident in your eagerness to stay current with the latest advancements in LLMs, GenAI, and verification technology. With a keen eye for detail and a drive to deliver high-quality results, you are adept at integrating AI-driven capabilities into established workflows, elevating productivity and efficiency. You value inclusivity and diverse perspectives, and you are motivated by the opportunity to shape the future of engineering through innovative, intelligent solutions.

What You’ll Be Doing:

• Develop and deploy LLM/GenAI-based solutions to enhance verification productivity across static, formal, and simulation-based flows in EDA tools.

• Collaborate cross-functionally with design, verification, CAD, and methodology teams to identify high-impact areas for AI-assisted automation.

• Build tools and frameworks to generate or refine assertions, constraints, checkers, and test intent, summarize design/spec content, and analyze logs, failures, and coverage gaps.

• Integrate LLM-driven capabilities into existing verification flows, tools, and automation infrastructure, ensuring seamless adoption.

• Develop and maintain scripts, data pipelines, and evaluation frameworks for AI-assisted verification use cases.

• Stay current with advances in LLMs, GenAI, verification technology, and digital design methodologies to inform best practices.

• Participate in technical reviews and help define scalable AI adoption strategies within verification environments.

The Impact You Will Have:

• Accelerate verification planning, setup, and closure, enabling faster time-to-market for complex digital designs.

• Enhance productivity and efficiency for engineering teams through intelligent automation and AI-driven solutions.

• Reduce manual effort and potential errors in verification by automating routine and complex tasks.

• Improve coverage analysis, debug processes, and testbench/content generation, resulting in higher quality silicon chips.

• Drive innovation in verification methodologies by integrating state-of-the-art GenAI capabilities.

• Foster cross-functional collaboration, contributing to robust and scalable verification strategies.

• Support Synopsys’ leadership in EDA technology and AI-driven engineering solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 5–8 years of experience in EDA software development with prior experience in developing GenAI-based tools.

• Hands-on experience with LLM/GenAI or AI/ML frameworks/tools such as PyTorch, TensorFlow, Hugging Face, LangChain, or equivalent.

• Proficiency in C++ and familiarity with Verilog, VHDL, or SystemVerilog.

• Strong understanding of verification frontend methodologies, including static analysis (CDC/RDC/Lint), formal/property-based verification, and simulation bring-up/debug.

• Experience with cloud or scalable compute platforms (AWS, GCP, Azure) is a plus.

• Familiarity with Agile development methodologies is desirable.

Who You Are:

• Innovative thinker with a passion for applying AI to real-world engineering challenges.

• Effective communicator, able to convey complex technical concepts to diverse audiences.

• Collaborative team player who thrives in cross-functional environments.

• Strong problem-solving abilities and analytical mindset.

• Adaptable, eager to learn, and comfortable with ambiguity in fast-evolving technology landscapes.

• Self-driven and proactive, with a commitment to delivering impactful solutions.

The Team You’ll Be A Part Of:

You will join a collaborative and innovative engineering team focused on advancing verification productivity through AI-driven solutions. The team works closely with design, verification, CAD, and methodology groups to identify and implement high-impact automation strategies. Together, you will drive the adoption of GenAI technologies within Synopsys’ EDA ecosystem, fostering a culture of continuous improvement and technological excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Key Responsibilities:

• Develop emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers.
• Engage in software development using C/C++ and synthesizable RTL development with Verilog.
• Verify solutions to ensure high performance and reliability.
• Interact with customers during the deployment and debug phases to ensure smooth implementation.
• Collaborate with cross-functional teams to integrate emulation solutions.
• Maintain and enhance existing emulation solutions to meet evolving industry standards.

Impact:

• Drive the development of advanced emulation solutions that meet industry standards.
• Enhance the performance and reliability of semiconductor products through innovative solutions.
• Ensure customer satisfaction by providing robust and efficient deployment support.
• Contribute to the continuous improvement of Synopsys' emulation technologies.
• Support the adoption of new protocols and standards in the semiconductor industry.

Requirements:

• 5+ years of relevant experience
• In-depth knowledge of PCIe, CXL, and UCIe protocols.
• Proficiency in C/C++ programming and object-oriented programming concepts.
• Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog.
• Experience with scripting languages like Python, Perl, or TCL.
• Familiarity with ARM architecture and UVM/functional verification is a plus.

Who You Are:

• A collaborative team player with excellent communication skills.
• A problem-solver with a keen eye for detail and a passion for innovation.
• Adaptable and able to work effectively in a fast-paced, dynamic environment.
• Customer-focused, with the ability to handle deployment and debugging challenges efficiently.
• Committed to continuous learning and staying updated with industry advancements.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You have a strong passion for working with embedded processors or processor-based systems.

You bring knowledge of HDL design, with a preference for experience in RISC processor architectures, DSP, AI (Neural Processing Unit), and multi-core systems.

You are familiar with design and verification languages such as Verilog and SystemVerilog, and have experience with RTL simulation tools, such as VCS.

Scripting or programming skills in languages such as assembler, C, Tcl, Csh, and Python is desirable.

Experience with embedded software related to DSP or AI reference models is a plus.

You have strong analytical and problem-solving abilities, as well as excellent written and verbal communication skills, including proficiency in English, detailed status reporting, and the ability to present results to program management teams.

What You’ll Be Doing:

• Develop and maintain microprocessor hardware IP including specification, implementation, verification, and FPGA validation, with an emphasis on validating system architecture and performance for DSP processor IP or Neural Processing Unit (NPU) IP.

• Optimize designs for performance, area, and power efficiency.

• Create and enhance tests for hardware IP verification and validation, improving functional coverage and performance through the application of state-of-the-art methodologies.

• Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.

The Impact You Will Have:

• Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.

• Enable customers to create sophisticated and efficient embedded designs.

• Support the delivery of world-class microprocessors used in advanced applications.

• Help improve functional coverage and performance of processor IP through advanced verification methods.

• Collaborate globally to deliver customer-focused solutions.

• Drive continuous improvement in processor system verification.

What You’ll Need:

• Passion for embedded processors or processor-based systems.

• Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.

• Familiarity with Verilog and SystemVerilog.

• Experience with RTL simulation tools (e.g., VCS).

• Scripting or programming skills in assembler, C, Tcl, Csh, or Python.

• Experience with embedded software for DSP or AI reference models is a plus.

Who You Are:

• Strong analytical and problem-solving abilities.

• Excellent written and verbal communication skills.

• Proficient in English.

• Capable of detailed status reporting and presenting results to program management teams.

The Team You’ll Be A Part Of:

Join our dynamic team dedicated to developing highly optimized hardware IP for the ARC family of configurable processors, enabling customers to create sophisticated and efficient embedded designs.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.

Key responsibilities include: Planning tests, checklists, coverage, and assertion planning. Creating detailed verification environments from functional specifications. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Writing test cases, checkers, and coverage that implement the verification test plan. Debugging simulations, including those of real signals modeled using SystemVerilog for analog. Performing RTL, GLS, and co-simulations and ensuring coverage closure. Participating in technical reviews and contributing actively. Providing customer support with the bring-up of IP in customer simulation environments. Following and improving development processes to ensure high-quality output.

Requirements include: BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 2+ years of experience in design verification. Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Ideal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written. A great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems.

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We are looking for a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. You will thrive in collaborative environments, bringing together diverse perspectives to solve complex challenges. With a strong foundation in RTL design and verification, you will approach every project with a sense of ownership and a commitment to excellence.

As an effective communicator, you will clearly articulate technical concepts to both internal teams and external customers, fostering strong partnerships and driving innovation. You will be adaptable, self-motivated, and resilient in the face of challenges, always seeking opportunities to learn and grow.

Your responsibilities will include designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance. You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.

You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

The impact you will have includes accelerating the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions. You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy.

You will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will have 5+ years of hands-on experience in RTL design and verification. You will be proficient in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.

You will be an analytical and critical thinker with a detail-oriented approach. You will be an effective communicator, comfortable collaborating across teams and with customers. You will be self-motivated and proactive in seeking solutions and driving projects forward.

You will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.

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As a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.

Key responsibilities include:

Creating and debugging test benches and test cases Running RTL and gate-level simulations Supporting application engineers and customers on HBM/DDR PHY topics Contributing to technical documentation Driving product improvements based on customer feedback

The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

ASIC RTL design and verification experience Verilog, PERL, TCL, Python skills Static timing analysis and synthesis knowledge Simulation and debugging abilities HBM/DDR protocol experience is an asset

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.

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As an experienced and visionary ASIC digital design architect, you will thrive in a fast-paced, collaborative environment. You will bring a passion for solving complex system-level challenges and a track record of delivering innovative, high-quality silicon solutions.

Your deep understanding of IP and SoC architectures enables you to see the big picture while meticulously refining subsystem details. You are comfortable navigating ambiguity, building consensus across diverse teams, and translating product requirements into robust, scalable architectures.

Your leadership inspires those around you, and you excel at mentoring and empowering engineers to reach their full potential. You are adept at balancing trade-offs across performance, power, area, and security, always striving for the optimal solution.

Communication is your strength,you articulate technical concepts clearly to both technical and non-technical stakeholders, ensuring alignment and shared understanding.

With a growth mindset, you embrace new challenges, technologies, and methodologies, continuously seeking opportunities to innovate and improve.

You value inclusion and diversity, recognizing that the best ideas emerge from a culture where everyone feels empowered to contribute.

As an IP Subsystems Architect, you will define architectural specifications for complex subsystems, translate system-level requirements into detailed subsystem architectures, and integrate multiple IP blocks into cohesive subsystems.

You will lead cross-functional collaboration with hardware, software, verification, and physical design teams to ensure subsystem feasibility and correctness.

Establishing and guiding verification and validation strategies, including defining coverage requirements and participating in silicon bring-up and debug sessions.

Producing comprehensive architecture documents, specifications, and guidelines, and clearly communicating architectural intent to a wide range of stakeholders.

Mentoring and coaching engineers, driving best practices, and fostering a culture of technical excellence.

Shape the architecture of industry-leading silicon IP and subsystem solutions that power millions of devices worldwide.

Accelerate time-to-market for differentiated products by ensuring robust and efficient subsystem design and integration.

Reduce risk through rigorous requirements management, architectural clarity, and cross-functional alignment.

Enhance product performance, power efficiency, and reliability, directly impacting customer satisfaction and competitive advantage.

Foster innovation by mentoring teams, introducing new methodologies, and championing best practices.

Strengthen Synopsys’ position as a trusted technology leader in the semiconductor ecosystem.

Bachelor’s or Master’s degree in Electronics or a related field, with 15+ years of industry experience.

At least 10 years in semiconductor design, IP integration, or SoC/subsystem architecture roles.

Deep expertise in Verilog/SystemVerilog, simulation tools, and advanced verification methodologies (e.g., SV UVM, BFM development).

Proficiency with industry-standard interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.).

Experience with synthesis, lint, CDC, low-power flows, and achieving verification closure.

Strong documentation and communication skills for effective cross-team alignment and requirements management.

A strategic thinker with exceptional leadership and mentoring capabilities.

A collaborative partner who thrives in diverse, cross-functional teams.

An excellent communicator, able to tailor messaging for both technical and non-technical audiences.

Innovative and proactive, always seeking opportunities to improve processes and outcomes.

Resilient and adaptable, comfortable with change and ambiguity.

Committed to fostering an inclusive and empowering team culture.

Join the Digital IP Subsystems Team at Synopsys,a high-performing group of architects, designers, and engineers focused on delivering world-class silicon IP and subsystem solutions.

The team collaborates closely with hardware, software, verification, and product teams across the globe, driving innovation in next-generation SoCs for AI, automotive, 5G, IoT, and more.

Together, we value creativity, technical excellence, and inclusion, empowering each team member to make a significant impact.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You have a proven track record in digital design and verification, and you are comfortable working across ASIC, FPGA, and firmware domains. Your experience enables you to interpret and review digital and analog specifications, create robust analog models, and write modular, constrained-random testbenches in Verilog and SystemVerilog.

You are adept at performing functional, assertion, and code coverage, and you have a keen eye for failure analysis and testplan management. Your organisational skills ensure that projects move forward efficiently, and your communication abilities allow you to interface effectively with multidisciplinary teams and customer support groups.

You value diversity, inclusivity, and continuous learning, seeking out opportunities to grow and mentor others. As someone who is motivated by innovation, you are excited to work with an expert team and help deliver high-end mixed-signal designs that power the next generation of smart technology.

Responsibilities:

• Designing and verifying ASIC, FPGA, and firmware for high-speed mixed-signal circuits.

• Reviewing digital and analog specifications to ensure alignment with project goals.

• Creating analog models based on schematics and functional requirements.

• Developing modular, constrained-random testbenches in Verilog and SystemVerilog for robust verification.

• Performing functional, assertion, and code coverage, analysing results to identify areas for improvement.

• Developing, managing, and tracking comprehensive testplans to ensure thorough verification.

• Reviewing and analysing failure cases to drive corrective actions and enhance product reliability.

• Running gate-level simulations to validate design integrity and performance.

• Collaborating with cross-functional design groups and customer support teams to resolve technical challenges.

Impact:

• Advancing the development of high-performance mixed-signal designs that enable next-generation applications.

• Ensuring functional and performance integrity of silicon IP products through rigorous verification.

• Accelerating time-to-market for differentiated products by reducing risk and increasing design confidence.

• Contributing to the world's broadest portfolio of silicon IP, supporting innovation in AI, IoT, 5G, and more.

• Enhancing reliability and quality of products that power smart devices and autonomous systems.

• Supporting Synopsys' reputation as a leader in chip design and software security by delivering excellence.

Requirements:

• BSEE with 2 years of digital design and verification experience, or MSEE with 0 years of digital design and verification industry experience.

• Expertise in ASIC design, synthesis, and clock domain crossing (CDC).

• Hands-on experience writing complex testcases in Verilog and SystemVerilog.

• Familiarity with code quality metrics and best practices in verification methodologies.

• Ability to create system-level specifications for digital and analog domains.

• Strong knowledge of high-speed digital and mixed-signal design principles.

• Experience with asynchronous clock crossings and DFT (Design For Test) methodologies.

Team:

Join a highly experienced mixed-signal design team, dedicated to delivering high-end mixed-signal designs from specification development through functional and performance testing. You'll be working alongside expert digital and mixed-signal engineers, collaborating across design, verification, and customer support to push the boundaries of innovation in silicon IP and SoC integration.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a passionate Computer Scientist with an exceptional analytical mind, driven by curiosity and a desire to solve some of the most challenging problems in automated logical reasoning and symbolic computation. You thrive in intellectually stimulating environments, enjoying the pursuit of innovative solutions within deep technology domains. Your expertise spans formal methods, algorithms, and complexity theory, enabling you to tackle large-scale, industrial verification challenges with confidence and creativity.

You bring hands-on experience in developing robust software solutions, particularly in C/C++. Whether your background is academic or industry, your contributions have been recognized by peers, and you are eager to collaborate with leading experts in the field. You understand the nuances of hardware architecture and design languages like SystemVerilog, or you are enthusiastic to learn them, appreciating their impact on verification excellence.

You are adaptable, open to new ideas, and motivated by continuous learning. You value diversity of thought, enjoy working in collaborative teams, and are committed to advancing the state of the art in formal verification. You believe in the transformative power of AI/ML-assisted design flows and are excited to shift the paradigm from design-centric to verification-centric innovation. Above all, you are ready to make a significant impact in the future of technology by joining the Synopsys Formal Technology Group.

Designing and implementing advanced formal verification algorithms and proof engines for large-scale VLSI chip designs. Developing scalable, memory-efficient, and mathematically robust solvers to address industry-leading verification challenges. Integrating innovative solutions into the Synopsys VC Formal platform, enhancing its capabilities and usability for thousands of engineers worldwide. Collaborating with cross-functional teams to extend formal verification technologies into domains such as hardware security, functional safety, and low power. Engaging with customers and industry partners to understand their verification needs and deliver best-in-class solutions. Contributing to the formal verification community through peer-reviewed publications, technical presentations, and mentorship of junior team members.

Advancing the scalability and reliability of formal verification tools used by leading chip design companies. Breaking complexity barriers, enabling verification of the most challenging and extensive industrial designs. Driving innovation in AI/ML-assisted design flows, transforming the verification landscape for the semiconductor industry. Empowering customers to achieve functional safety, hardware security, and low power goals in their products. Facilitating widespread adoption of formal methods across diverse domains and applications. Fostering a collaborative, intellectually rich environment that inspires continuous learning and knowledge sharing.

8-10 years of relevant experience Expertise in formal methods, model checking, theorem proving, and equivalence checking. Strong proficiency in algorithms, data structures, and complexity analysis. Professional coding skills in C/C++ and experience developing large-scale software systems. Background in hardware architecture and familiarity with design languages such as SystemVerilog (preferred but not required). Peer recognition in the formal verification community, such as publications or industry accolades.

Analytical thinker with a keen eye for detail and problem-solving. Collaborative team player who values diversity and open communication. Innovative and adaptable, willing to embrace new technologies and methodologies. Driven by curiosity and a passion for continuous learning. Resilient in the face of challenging technical problems and complexity.

You’ll join the Synopsys VC Formal R&D Team,a vibrant community of talent and expertise dedicated to advancing formal verification technologies. The team is renowned for solving deep theoretical and practical problems and integrating them into world-leading verification tools. You will collaborate with experts in formal methods, software engineering, and AI/ML, contributing to the proliferation of formal verification across hardware security, functional safety, low power, and more.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

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As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

Key responsibilities include:

• Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products
• Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles
• Mentoring and developing team members, fostering technical growth, and a culture of innovation
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges

The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

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This role is ideal for an engineer who enjoys deep technical work , analysing complex logic simulations, working across hardware and software, and driving improvements in test efficiency and overall QoR. You’ll be hands-on with Verilog, simulation/debug, and C/C++ development, influencing key aspects of next-generation DFT solutions.

Responsibilities:

• Contribute across the entire DFT flow: RTL, netlist, ATPG, and logic simulation
• Analyse DFT IP behaviour, debug logic issues, and deliver robust fixes
• Enhance pattern-generation workflows for better performance and QoR
• Develop C/C++ components for pattern processing, automation, and data handling
• Work closely with multi-site R&D teams to ensure smooth flow integration
• Use AI-based tools to accelerate debugging, code comprehension, and analysis

Requirements:

• Master’s degree in Electronics, Computer Science, or equivalent, with background in both Verilog and C/C++.
• Strong understanding of DFT, scan architectures, and test-generation concepts
• Hands-on experience with Verilog and logic-simulation debug
• Proficiency in C/C++ programming
• Ability to work effectively across large-scale SoC hardware and complex software environments.
• Strong analytical and root-cause-debugging skills
• Openness to using AI tools to boost productivity

Nice to Have:

• Experience with TestMAX, Tessent, Modus, or similar DFT/ATPG tools
• Knowledge of pattern compression, hierarchical DFT, or test scheduling
• Experience with automation or performance-oriented C/C++ code

Why Join Synopsys:

You’ll work on core DFT technologies used by the world’s leading semiconductor companies. Your contributions will directly strengthen the Streaming Fabric and SEQ solution and support their integration into the TestMAX ecosystem , enabling improved scalability, test efficiency, and product quality.

If you’re excited by deep technical challenges and want to work on impactful DFT innovation, we’d love to hear from you.

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We are seeking a seasoned engineer with a passion for pushing the boundaries of technology to join our team. With 5-8 years of experience, you will bring a wealth of knowledge in software architecture and excel in C/C++ software development, digital simulation, compiler optimizations, and design patterns, data structures, and algorithms.

As a member of our performance team in Digital Simulation, you will work closely with both local and global teams to drive technological advancements and achieve project goals.

Responsibilities:

• Designing, developing, and troubleshooting core algorithms for compiler.
• Collaborating with local and global teams to enhance runtime performance for verilog compiler.
• Engaging in pure technical roles focused on software development and architecture.
• Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation.
• Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.

Impact:

• Driving technological innovation in chip design and verification.
• Enhancing the performance and quality of simulation tools used globally.
• Solving complex compiler optimizations problems to improve simulation performance.
• Collaborating with cross-functional teams to achieve project milestones.
• Pioneering new software architectures that set industry standards.

Requirements:

• Strong hands-on experience in C/C++ based software development.
• Deep understanding of design patterns, data structures, algorithms, and programming concepts.
• Knowledge of ASIC design flow and EDA tools and methodologies.
• Proficiency in Verilog, SystemVerilog, and VHDL HDL.

Who You Are:

• Highly enthusiastic and energetic team player with excellent communication skills.
• Strong desire to learn and explore new technologies.
• Effective problem-solver with a keen analytical mind.
• Experienced in working on Unix/Linux platforms.
• Adept at using developer tools such as gdb and Valgrind.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Senior Manager of SOC Engineering, you will oversee and drive end-to-end RTL design, verification, architecture, and integration of advanced subsystems. You will lead teams in Bangalore/Hyderabad, manage customer communications, and ensure timely, high-quality delivery. You will guide your team through the full lifecycle: from requirements to release, ensuring excellence at every stage. Foster innovation and continuous improvement, motivating engineers to reach their full potential.

Key Qualifications:

• Bachelor's or Master's in Electronics or related field, with 15+ years of overall experience
• 8+ years of hands-on techno-managerial experience managing remote and local teams
• Strong track record in Subsystem/SoC design, architecture, and implementation
• Deep expertise in Verilog/System Verilog and simulation tools
• Proficiency with interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.)
• Experience with synthesis, lint, CDC, low power flows, and verification closure (SV UVM, BFM development, test environment creation)
• Outstanding communication skills and a passion for team development

What Sets You Apart:

• You have strong, hands-on technical experience and thrive on rolling up your sleeves to solve complex challenges
• You excel at turning high-level requirements into innovative solutions and see projects through to successful, timely completion
• You build strong, trust-based relationships with customers and stakeholders, always putting their needs at the centre
• You bring a creative mindset and lead proactively, inspiring your team to think big, embrace change, and drive continuous improvement

Hands-on experience is an absolute must for success in this role.

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This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.

As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.

In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.

Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You are an experienced verification architect who thrives on technical leadership and mentoring others. You excel in digital design and verification, enjoy collaborating with global teams, and are motivated by delivering high-quality solutions. Your expertise includes System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. You’re proactive, inclusive, and passionate about process improvement and innovation.

Responsibilities: Provide technical leadership and mentor junior engineers. Collaborate with cross-functional, global teams. Define and implement advanced verification plans and methodologies. Develop and maintain UVM-based testbenches. Drive process improvements for verification efficiency. Automate verification flows using scripting and programming skills.

The Impact You Will Have: Ensure robust verification for complex ASIC and IP designs. Support first-silicon success and faster time-to-market. Elevate team skills and technical excellence. Champion best verification practices and tools. Enhance collaboration across global teams. Promote continuous improvement in verification processes.

What You’ll Need: BSEE or MSEE with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL. Expertise in UVM and coverage-driven RTL verification. Proficiency in scripting and programming (Python, Perl, C/C++). Ability to define verification plans and architect testbenches. Experience with 200G SerDes verification is an asset.

Who You Are: Collaborative leader and effective communicator. Mentor who empowers others. Analytical, detail-oriented problem solver. Adaptable and innovative.

The Team You’ll Be A Part Of: Join a diverse, world-class engineering team dedicated to delivering industry-leading verification solutions for next-generation semiconductor products.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An enthusiastic and detail-oriented ASIC Digital Design Verification Engineer with a passion for cutting-edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high-level requirements into robust and efficient designs. Your expertise, coupled with your strong understanding of digital design and verification methodologies, makes you an invaluable asset to any project. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges, and delivering innovative solutions. You are proactive, with excellent communication skills that enable you to work effectively with cross-functional teams. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements.

What You’ll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing all task related to verifying a complex digital IP including detailed test plans, functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.
• Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality.
• Documenting design specifications, test plans, and verification reports.
• Proficiency in System Verilog, UVM, SVA, and other verification techniques.
• Strong understanding of digital design and verification concepts.
• Excellent problem-solving skills and attention to detail.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You’ll Need:

• Proficiency in digital design and verification methodologies.
• Experience with developing testbenches using System Verilog and UVM.
• Expertise in using advanced verification techniques.
• Familiarity with scripting languages such as Python or Perl for automation.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• A results-driven professional committed to delivering high-quality work.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

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Job Description

We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SecurityIP solutions.

Responsibilities

• Leading a diverse team of design engineers in the development of next-generation SecurityIP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Driving all phases of SecurityIP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth and a culture of innovation.
• Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Impact

• Delivering industry-leading SecurityIP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding of SecurityIP architecture is a plus.

Team

You’ll join the Synopsys SecurityIP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Your primary responsibilities will include building and running CoSim simulations using established environments, integrating schematics and RTL, and adhering to procedures for reproducibility and traceability. You will also be responsible for debugging mixed-signal failures by collecting logs, waveforms, and reproducible steps, performing first-pass triage, and escalating issues with clear evidence to design and verification teams.

In this role, you will collaborate with analog and digital designers to confirm expected behaviors, review corner cases, and align verification needs for day-to-day activities. You will maintain and improve test content, scripts, and documentation to enhance verification quality and speed.

As a Mixed-Signal Verification Engineer, you will contribute to the overall reliability and performance of SERDES deliverables by surfacing system-level issues and supporting their resolution.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly.

Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence.

Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning.

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We are seeking a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success.

As a Principal Simulation R&D Software Engineer, you will be responsible for designing, developing, and troubleshooting core algorithms for compiler. You will collaborate with local and global teams to enhance runtime performance for verilog compiler. You will engage in pure technical roles focused on software development and architecture. You will utilize your knowledge of digital simulation flows and EDA tools to drive innovation. You will leverage your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.

You will drive technological innovation in chip design and verification. You will enhance the performance and quality of simulation tools used globally. You will solve complex compiler optimizations problems to improve simulation performance. You will collaborate with cross-functional teams to achieve project milestones. You will pioneer new software architectures that set industry standards.

To succeed in this role, you will need strong hands-on experience in C/C++ based software development. You will require a deep understanding of design patterns, data structures, algorithms, and programming concepts. You will need knowledge of ASIC design flow and EDA tools and methodologies. You will require proficiency in Verilog, SystemVerilog, and VHDL HDL. You will need 10+ years of relevant EDA Software experience preferably in Simulation domain.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You'll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Creating and executing detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You'll Need:

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS, ModelSim, or similar.
• Excellent problem-solving skills and attention to detail.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You'll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.

As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.

You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.

You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.

You will develop and implement advanced test plans and test environments at both unit and system levels.

You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.

You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.

You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.

You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.

You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.

You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.

You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.

You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

You will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.

The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.

Collaboration, innovation, and a drive for excellence define our culture.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Responsibilities:

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
• Take ownership of tools that verify common design blocks used in all products at NVIDIA.
• Act as a 'DevOps' engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
• Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (or equivalent experience).
• 3+ years of proven experience preferred.
• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
• Proficiency in scripting using modern Python and/or Perl.
• Experience with Unix/Linux shell scripting and Makefiles.
• Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Preferred qualifications:

• Prior experience in ASIC verification.
• Knowledge of Clocks/Resets design and verification.
• Exposure to CDC related design/verification flows.
• Exposure to backend flows (Synthesis, Timing, etc).

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of constant innovation and creating the highest performance products in the industry? If so, we want to hear from you.

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Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.

As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
• You will be responsible for micro-architecture using sophisticated verification methodologies.
• As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Requirements:

• Bachelors or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
• Strong background developing TB's from scratch using SV and UVM methodology is desired
• C++ programming language experience, scripting ability and an expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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We are seeking a highly skilled ASIC Security Staff Engineer to join our team at Synopsys. As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.

Job Description

What You'll Be Doing:

• Designing and implementing RTL in Verilog and/or System Verilog for Security Applications.
• Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM.
• Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification.
• Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions.
• Working within an international team setup, contributing to global projects.
• Ensuring adherence to high-quality standards and best practices in digital design and verification processes.

The Impact You Will Have:

• Enhancing the performance and security of our IP cores and subsystems.
• Contributing to the rapid integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.
• Reducing time-to-market for differentiated products with minimized risk.
• Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive.
• Collaborating with a diverse team to deliver leading-edge solutions that shape the future of technology.
• Playing a key role in maintaining Synopsys' position as a leader in chip design and software security.

What You'll Need:

• 3+ years Experience in RTL design of hardware IP components.
• Proficiency in ASIC verification using System Verilog, UVM, and or Verilog
• Ability to create detailed specifications for test environments.
• MSc or PhD in Electrical Engineering or Computer Science.
• Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.

Who You Are:

• A strong communicator with excellent written and verbal skills.
• A team player who thrives in a collaborative international environment.
• An innovative thinker who is passionate about technology and continuous improvement.
• Detail-oriented and committed to delivering high-quality work.
• Adaptable and able to manage multiple tasks effectively.

The Team You’ll Be A Part Of:

You will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15159

Remote Eligible

No

Date Posted

02/04/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.

What You’ll Be Doing:

• Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.

• Creating emulation-based transactor and solutions using SystemVerilog and C++.

• Providing technical support and guidance to customers during the deployment of the ZeBu emulator.

The Impact You Will Have:

• Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.

• Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.

• Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.

• Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys' market position.

• Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.

• Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.

What You’ll Need:

• Bachelor's degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.

• A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.

• Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.

• Proficiency with UNIX and scripting.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.

Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.

Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.

Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.

You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 02/24/2026

Category EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.

What You’ll Be Doing:

• Developing robust functional verification environments (test benches) for high-speed PHY IPs.
• Creating comprehensive test plans and detailed test cases to ensure thorough coverage.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.
• Building architectural and micro-architectural understanding of complex digital design blocks under verification.
• Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.
• Contributing to process improvements and sharing best practices within the team.

The Impact You Will Have:

• Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.
• Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.
• Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.
• Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.
• Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.
• Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Experience with industry-standard development and verification tools and methodologies.
• Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.
• Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.
• Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.
• Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.

Who You Are:

• Detail-oriented and analytical thinker with a proactive approach to problem-solving.
• Effective communicator who thrives in collaborative and diverse team environments.
• Adaptable and eager to learn new technologies and methodologies.
• Resourceful and resilient in overcoming technical challenges.
• Committed to fostering inclusion, respect, and continuous improvement within the workplace.

The Team You’ll Be A Part Of:

You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.

What You’ll Be Doing:

• Developing functional verification environments (test benches) for complex digital design blocks.
• Creating comprehensive test plans and test cases to ensure thorough coverage and robust design validation.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Performing simulations, generating random and focused stimulus, and conducting coverage analysis to verify functionality.
• Building architecture and micro-architecture knowledge of digital blocks under test to drive effective verification strategies.
• Collaborating with cross-functional teams to share insights and resolve issues throughout the pre-silicon verification process.
• Utilizing industry-standard verification tools and methodologies to enhance efficiency and quality.

The Impact You Will Have:

• Ensuring the reliability and performance of high-speed PHY IPs through rigorous pre-silicon functional verification.
• Accelerating product time-to-market by identifying and resolving design issues early in the development cycle.
• Reducing risk for customers by delivering thoroughly verified and differentiated silicon IP solutions.
• Supporting the development of next-generation products that power innovations in AI, 5G, IoT, and more.
• Contributing technical expertise to the team, fostering a culture of continuous improvement and learning.
• Promoting collaboration and knowledge sharing across engineering teams to achieve collective goals.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows.
• Experience with industry-standard development and verification tools and methodologies.
• Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred).
• Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred).
• Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred).

Who You Are:

• Analytical thinker with a strong eagerness to learn and grow.
• Dynamic personality, energizing and motivating team members.
• Strong communicator, able to collaborate effectively in diverse environments.
• Self-motivated leader, capable of driving verification activities independently and as part of a team.
• Detail-oriented, ensuring thorough validation and quality in all deliverables.

The Team You’ll Be A Part Of:

You will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.

A technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.

You bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You'll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure quality design, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Driving cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You'll Need:

• 15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.

• Be results driven

• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.

• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.

• In-depth knowledge of system-level validation for high-speed interface PHY

• Proven track record of working cross-functionally and driving issues to closure

• Knowledge of mixed-signal design

• Experience in working in cross-functional collaborations

• Be an excellent communicator and a beacon for change

• Excellent debugging, analytical, and problem-solving skills

• Working knowledge of scripting in languages such as Python and/or Perl

• Good understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon

• Good interpersonal skills, ability & desire to work as a standout colleague

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

#LI-DP1

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness
• Time Away
• Family Support
• ESPP
• Retirement Plans
• Compensation

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Your proactive approach and problem-solving abilities make you a trusted advisor for both internal stakeholders and external customers. You are detail-oriented, yet able to see the big picture, ensuring that every design meets rigorous standards for quality, performance, and scalability. You enjoy guiding teams through challenging technical obstacles and are always eager to explore new technologies and methodologies that can enhance product development. Your communication skills are top-notch, enabling you to clearly articulate complex concepts to diverse audiences. You value inclusion and respect, fostering a team culture where every voice is heard and every idea is considered.

Role Details

• Oversee junior engineers and lead the design, implementation, verification, and physical synthesis of NVM controllers for OTP and MTP products at advanced technology nodes.
• Provide digital guidance for new product developments, ensuring robust architecture and innovative solutions.
• Manage the maintenance and enhancement of digital control blocks, chip test systems, circuit models, and design-for-test circuits.
• Participate in all phases of the ASIC design cycle, including architecture definition, modeling, RTL coding, verification, synthesis, and place & routing.
• Deliver technical support to internal teams, application engineers, and customers during product integration phases.
• Collaborate with cross-functional teams to optimize design flows and ensure seamless integration of digital components.
• Drive continuous improvement initiatives and promote best practices in digital design and verification methodologies.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.

What You’ll Be Doing:

• Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.
• Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.
• Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.
• Collaborating with R&D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.
• Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.

The Impact You Will Have:

• Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.
• Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.
• Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.
• Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.
• Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.
• Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design

What You’ll Need:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.
• Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.
• 7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.
• Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).
• Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.
• Experience in Unix/Linux development environments.

Who You Are:

• Collaborative team player with excellent communication skills and a global mindset.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.
• Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.
• Adaptable and eager to stay updated with the latest industry trends and technologies.
• Customer-focused, with a dedication to supporting and enabling client success.

The Team You’ll Be A Part Of:

You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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We are looking for a hardware verification engineer who will perform verification of complex leading-edge security systems IP components. Be a part of a world-class team, building advanced security solutions that meet the Synopsys high quality standard for best-in-class products. These products are found in some of the most advanced, high-tech devices today in areas like automotive, networking, mobile, and IoT applications.

Responsibilities

• Performing design verification of cutting-edge IP components and subsystems used in high-profile security applications.
• Developing comprehensive product verification strategies, including test specifications, detailed test plans, and thorough test reports.
• Implementing, developing, and automating test environments for regression testing to ensure robust product quality.
• Collaborating closely with design engineers and architects to debug products and resolve defects efficiently.
• Staying current with the latest verification methodologies and tools, integrating state-of-the-art practices into your workflow.
• Hardware verification of IP cores and subsystems with techniques such as SystemVerilog /UVM and Formal Verification
• Proactively researching and integrating new developments in the domain of embedded security

Requirements

• Proven expertise in verification of digital hardware IP components
• Deep technical knowledge of and experience with modern verification methodologies including UVM, assertion-based verification, coverage driven methodology and formal verification
• Good knowledge about IC Design flows and excellent problem solving and debugging skills
• Experience with verification flow automation and scripting.
• Strong communication (written and verbal) and interpersonal skills
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Science, with 8+ years of relevant experience.
• Familiarity with security and cryptographic protocols is desirable.

What You’ll Be A Part Of

You’ll join the Security IP group in Ottawa, world-class, security-focused team of hardware and software engineers dedicated to advancing the best in security technologies. The team works collaboratively to design, verify, and deliver leading-edge security solutions found in the world’s most advanced devices, from automotive to IoT. Together, you’ll challenge the status quo and set new benchmarks in embedded systems security.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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RTL & Codesign Engineer

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems.

In this role you will:

• Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.

• Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.

• Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.

• Work closely with designers and verification engineers to turn real pain points into durable tools.

• Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.

• Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.

• Help enable PPA optimization loops by building analysis and automation around area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.

You might thrive in this role if:

• Demonstrated ability to build and maintain software (projects, internships, research, open source, or equivalent experience).

• Strong CS fundamentals: data structures, algorithms, debugging, and software design.

• Proficiency in at least one of Rust, C++, or Python (and willingness to learn the rest).

• Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or equivalent hardware descriptions.

• Familiarity with compiler or IR-based ideas (representations, passes, transformations, lowering), through coursework or projects.

• Comfort operating in ambiguity and iterating quickly with users of your tools.

Nice to have skills:

• Exposure to compiler and hardware toolchains such as XLS/DSLX, LLVM, Chisel/FIRRTL, CIRCT/MLIR, other novel hardware languages (e.g. HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope)

• Experience with Verilog tooling ecosystems (Yosys/RTLIL, Verilator, Slang) or writing tooling around them.

• Experience with build and test infrastructure (Bazel, CI systems, fuzzing, performance testing).

• Prior work touching synthesis, place and route, static timing analysis, or other PPA-related workflows.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world.

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What you'll do

• Develop and implement high-performance PCIe-based designs on FPGA platforms, ensuring optimal functionality and efficiency.
• Collaborate closely with cross-functional teams to gather requirements, evaluate design tradeoffs, and deliver robust FPGA solutions that satisfy project goals.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in FPGA design and development.
• Proficiency in HDL languages such as Verilog.
• Strong expertise with industry-standard FPGA development tools like Vivado.
• In-depth understanding of digital design principles, including clock domains and timing analysis.
• Experience with high-speed interfaces (PCIe or Ethernet).
• Excellent analytical, debug, and problem-solving skills.
• Ability to collaborate effectively in a multi-disciplinary, team-based environment.
• Strong verbal and written communication skills.

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What you'll do

• Leading end-to-end deployment and integration of Verification IP at strategic customer accounts, ensuring seamless adoption and success.
• Defining and implementing robust verification strategies for Arm-based SoCs, with a focus on interconnect and coherency protocol validation.

What you need

• Deep expertise in UVM, SystemVerilog, and advanced protocol verification methodologies.
• Hands-on experience with Verification IPs (VIPs) and Transactors in both simulation and emulation environments.

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What you'll do

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5 years of hands-on experience in RTL design and verification.

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What you'll do

• Supporting post-sales integration and silicon bring-up of Memory Interface PHY IPs and Controller IPs.
• Delivering insightful technical presentations and hands-on training sessions to both internal teams and external customers.
• Creating clear, detailed documentation and user collateral to facilitate customer understanding and product usability.

What you need

• Direct experience with Memory Interface PHY IPs and Controller IPs integration and bring-up.
• Solid knowledge of AMBA/AXI bus interfaces, floor-planning, and backend engineering for ASIC design.
• Proficiency with Linux, Verilog/VHDL, and modern ASIC design flows.

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What you'll do

• Designing and implementing RTL-based HBM controller IP cores for cutting-edge SoC applications.
• Interpreting and translating standard and product functional specifications into detailed micro-architectures.

What you need

• Extensive hands-on experience with RTL design and micro-architecture development from functional specifications.
• Proficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.

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What you'll do

• Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.
• Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows

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What you'll do

• Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
• Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
• Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
• Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.
• 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
• Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
• Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.

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What you'll do

• Interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB;
• Evaluating and troubleshooting digital and mixed-signal circuits to ensure optimal performance and resolve complex design challenges;
• Collaborating with digital, firmware, and analog teams to solve verification challenges and improve design methodologies;
• Adapting and debugging internal verification environments to effectively replicate challenging scenarios;
• Identifying and implementing process improvements to enhance efficiency in design procedures and methodologies;
• Documenting verification environments, plans, and procedures to ensure clear communication and knowledge sharing across teams.

What you need

• 6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification;
• Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping with logical synthesis flows;
• Strong programming and scripting skills for test automation and data analytics (Python, C/C++, TCL);
• Strong understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization techniques;
• Ability to interpret and apply digital architecture and SerDes standards documentation to develop robust verification solutions;
• Excellent technical documentation skills to ensure clear communication and knowledge transfer.

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What you'll do

As a HBM Design Verification Engineer, Principal, you will be responsible for developing verification strategies and plans for ASIC/SoC projects, defining and implementing testbench architecture and methodologies, building testbench infrastructure and verification components, and creating verification item lists, coverage models, and checkers.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 10–15+ years of relevant experience

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What you'll do

• Developing and executing comprehensive verification plans for complex ASIC designs, focusing on next-generation HBM (High Bandwidth Memory) products.
• Writing and maintaining advanced testcases using SystemVerilog and UVM methodologies to ensure thorough coverage and robust verification.
• Debugging and analyzing complex testbench and design-related issues, collaborating closely with design and mixed-signal engineering teams.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE) with a minimum of 10 years of digital design/verification experience.
• Proven experience in writing and maintaining testcases using SystemVerilog/UVM.
• Strong debugging skills for complex testbench and design-related issues.
• Solid understanding of digital circuit design concepts and principles.
• Proficiency with scripting languages such as Python or Perl for automation and workflow enhancement.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Partnering with design teams to define verification requirements
• Developing test plans from specifications
• Building and maintaining UVM testbenches and agents

What you need

• B.Sc./M.Sc. in a relevant engineering field
• 10+ years in ASIC/UVM verification

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What you'll do

• Collaborate directly with customers to understand their technical requirements and deliver tailored solutions for chip design and verification challenges
• Provide expert-level support for Synopsys products, troubleshooting issues, and guiding users through advanced features and best practices

What you need

• 5-10 years of experience in ASIC/SoC verification or related field
• Strong proficiency in Verilog, System Verilog, and UVM methodology

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Exposure to Verilog/System Verilog and AMS concepts or circuit design (coursework, labs, or hands-on experience).

Why this matters

As a Mixed-Signal AMS Co-Simulation Verification Engineer, you will play a critical role in ensuring the quality and reliability of our high-performance SERDES and mixed-signal IP, which powers AI, automotive, cloud, and mobile applications at massive scale.

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What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Leading and managing a team of ASIC Digital Verification engineers, providing guidance and mentorship;
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies;

What you need

• Extensive experience in ASIC digital verification, particularly with HBM (or DDR/LPDDR) protocols;
• Proficiency in SystemVerilog, UVM, and other verification tools and methodologies;

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.

What you need

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.

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What you'll do

As a Sr Staff Engineer, you will be responsible for designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

What you need

• MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
• Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
• Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
• Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
• Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
• Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Why this matters

• Accelerate the development of industry-leading prototyping systems, enabling faster time-to-market for cutting-edge ASIC designs.
• Enhance the functionality and reliability of Synopsys' HAPS and ProtoCompiler products through innovative hardware and software solutions.
• Drive customer satisfaction by delivering robust, scalable, and user-friendly prototyping tools that meet diverse engineering needs.
• Contribute to Synopsys' reputation as a leader in verification and prototyping technology, influencing industry standards and practices.

What you'll be doing

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
• Developing and maintaining complex EDA software for high-performance prototyping systems.
• Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
• Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
• Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
• Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
• Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
• Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Why you'll love this role

• Opportunity to work on cutting-edge projects and technologies.
• Collaborative and dynamic work environment.
• Professional growth and development opportunities.
• Recognition and rewards for outstanding performance.
• Comprehensive benefits and compensation package.

What you'll need to succeed

• Strong technical skills and knowledge in digital design, verification, and prototyping.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.
• Ability to work independently and as part of a team.
• Adaptability and flexibility in a fast-paced environment.

How to apply

• If you're ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.
• Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away, including company holidays, ETO, and FTO programs.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, with a 15% discount on Synopsys common stock.
• Retirement plans, varying by region and country.
• Competitive salaries.

How we hire

• We're proud to be an equal opportunities employer and welcome applications from diverse candidates.
• Our hiring process typically involves a phone screen, followed by an interview with the hiring team.
• We're committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.

Join our team

• If you're passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.
• We can't wait to hear from you!

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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What you'll do

• Conducting comprehensive testing on silicon implementations of high-speed analog integrated circuits in a cutting-edge R&D lab environment.
• Reviewing and debugging silicon under test, as well as supporting associated hardware systems to ensure optimal performance.

What you need

• Bachelor’s degree in Electrical Engineering (BSEE) or equivalent technical field with at least 3+ years of industry direct related experience.

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.
• Creating, executing and tracking against detailed test plans to verify complex ASIC designs.

What you need

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Proficiency in System Verilog, SVA and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.
• Experience with simulation tools such as VCS, Model Sim, or similar.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

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What you'll do

Develop advanced technologies to enhance hardware emulation performance and scalability.

• Developing advanced technologies to enhance hardware emulation performance and scalability.
• Analyzing and debugging complex problems that span hardware and software domains.
• Understanding and improving sophisticated emulation technologies, including clock processing and timing analysis.
• Proposing innovative ideas and solutions to optimize emulation workflows and system efficiency.
• Working across all aspects of the emulation flow, including compilation, runtime, and debug processes for next-generation products.

What you need

• Proficiency in C++ and demonstrated experience debugging complex systems.
• Hands-on experience with Verilog or VHDL and HDL simulation environments.
• Familiarity with Electronic Design Automation (EDA) and emulation technologies (desired).
• Strong analytical skills to tackle intricate hardware and software challenges with creative solutions.
• Solid understanding of verification flows, ASIC or FPGA workflows, and performance optimization strategies.
• Understanding of clocking challenges in ASIC and FPGA

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.

What you need

• MSEE (preferred) or equivalent with a minimum of 5 years' experience in digital design and verification.
• Proven proficiency in Verilog or VHDL for ASIC development.
• Experience with code quality metrics and coverage-driven verification methodologies.
• In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies.
• Strong understanding of CDC, synthesis, and power optimization techniques.
• Hands-on experience with simulation tools and collaborative debugging in verification environments.
• Ability to develop system-level specifications for complex digital and analog systems.

What you'll be doing:

• Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.
• Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.
• Driving the creation, execution, and tracking of comprehensive test plans, including functional, assertion, and code coverage metrics.
• Overseeing design flows for clock domain crossing (CDC), synthesis, design-for-test (DFT), and low-power methodologies.
• Collaborating closely with verification teams to debug issues, analyze failure cases, and run gate-level simulations.
• Coordinating with cross-functional teams and providing technical leadership throughout the product lifecycle, from specification development to performance testing of test chips.
• Mentoring and developing junior engineers, fostering a culture of continuous learning and innovation.

The Impact You Will Have:

• Accelerate the delivery of industry-leading mixed-signal ASIC solutions, enabling next-generation connectivity standards.
• Enhance the quality and reliability of high-speed SERDES products through rigorous design and verification practices.
• Drive process improvements that elevate team productivity and product performance.
• Champion best practices in digital and mixed-signal design, setting new benchmarks for quality and efficiency.
• Foster a collaborative and innovative team environment, empowering engineers to reach their full potential.
• Strengthen Synopsys' reputation as a global leader in semiconductor technology through successful project execution and customer satisfaction.

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

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What you'll do

• Deploying Automation for characterization of Mixed-Signal Integrated Circuits with Synopsys IP.
• Designing and implementing laboratory test setups.
• Utilizing high-end laboratory equipment such as oscilloscopes, arbitrary waveform generators, and network analyzers.

What you need

• MSc in Electrical Engineering or Computer Science.
• Knowledge of microelectronics, mixed-signal IC concepts, and digital and analog circuits.

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What you'll do

You will be responsible for developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.

• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.

Why this matters

Drive the development of cutting-edge HBM PHY IP, enabling industry-leading memory bandwidth for next-generation computing systems.

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What you'll do

You will join the Synopsys IP Group, a highly collaborative and innovative team focused on developing leading-edge interface IP solutions for memory technologies.

• Developing detailed verification testplans and comprehensive functional coverage models for complex memory interface IP.
• Implementing scalable UVM testbench infrastructure and designing robust test cases to verify training firmware functionality on RTL PHY models.

What you need

• Proficiency in SystemVerilog and UVM, with hands-on experience using simulation and waveform debugging tools.
• Strong background in developing verification solutions focused on productivity, performance, and throughput.

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

• Designing and verifying complex ASIC digital and mixed-signal systems using Verilog or VHDL.
• Analyzing digital and analog specifications to develop robust system-level designs.

What you need

• Master’s degree in Electrical Engineering or related field, with at least 5 years of relevant industry experience.
• Proficient in Verilog or VHDL for digital design and verification.

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What you'll do

You will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.
• Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.
• Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.
• Contributing to the improvement of verification methodologies and automation flows.
• Documenting design specifications, verification plans, and results to ensure transparency and repeatability.
• Participating in code reviews and technical discussions to drive innovation and continuous improvement.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 8+ years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
• Experience working in Unix/Linux environments.
• Strong debugging and problem-solving skills, especially in complex chip design environments.
• Excellent written and verbal communication skills in English.
• Knowledge of digital, analog, and mixed-signal IP/circuit design (a plus).
• Familiarity with 3D-IC standards and semiconductor verification best practices (desirable).

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What you'll do

Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.

Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels.

Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.

Managing regression and ensuring adherence to verification methodologies.

Collaborating closely with RTL designers and a global team of verification engineers.

Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

What you need

BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.

Experience in architecting verification environments for complex serial protocols.

Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.

Expertise in verification methodologies such as VMM, OVM, and UVM.

Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Familiarity with Verilog and scripting languages such as Perl, TCL, and Python.

Experience with IP design and verification processes, including VIP development.

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What you'll do

Develop reusable verification environments and testbenches using UVM.

• Plan, maintain, and execute verification strategies for ASIC/SoC projects.

• Create test cases, set up and run regressions, and close coverage.

What you need

Minimum 6 years' SoC/ASIC verification experience.

• Strong SystemVerilog (UVM preferred) skills.

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