ad7a01f1-d14 Senior FPGA Verification Engineer The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.

The Imaging team is seeking a Senior FPGA Verification Engineer to help design new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

Responsibilities:

  • Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
  • Creation of written test plans, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Required Qualifications:

  • A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field
  • 8+ years of experience developing HDL firmware for FPGA devices
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
  • Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity
  • Eligible to obtain and maintain an active U.S. Secret security clearance

Preferred Qualifications:

  • Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts
  • Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado

Benefits: Anduril offers a comprehensive, competitive benefits package (available at little to no cost to employees) to support health, recovery, and overall well-being.

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]]> full-time senior $191,000-$253,000 USD FPGA verification, SystemVerilog, OVM/UVM, VHDL, Verilog, ASIC/FPGA development, Git, Subversion, U.S. Secret security clearance, ASIC/FPGA lab validation, DFT, manufacturability, production test concepts, Unix/Linux environments, scripting, software development, QuestaSim, Synplify, Quartus, Vivado Engineering Technology Anduril https://logos.yubhub.co/andurilindustries.com.png Anduril develops state-of-the-art imaging systems for security challenges. https://andurilindustries.com USD 191000 253000 yearly https://job-boards.greenhouse.io/andurilindustries/jobs/5235483007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Waltham, Massachusetts Waltham Massachusetts US 2026-09-11 66ea5e73-e90 Senior FPGA Verification Engineer The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.

The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product line. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

Responsibilities:

  • Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
  • Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Required Qualifications:

  • A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required
  • 8+ years of experience developing HDL firmware for FPGA devices
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
  • Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity
  • Eligible to obtain and maintain an active U.S. Secret security clearance

Preferred Qualifications:

  • Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts
  • Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado

Benefits: Anduril offers top-tier benefits for full-time employees, including comprehensive, competitive benefits package (available at little to no cost to employees) to support health, recovery, and well-being.

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]]> full-time senior $165,000-$218,000 USD FPGA, ASIC, SystemVerilog, OVM/UVM, VHDL, Verilog, Git, Subversion, U.S. Secret security clearance, ASIC/FPGA lab validation, DFT, manufacturability, production test concepts, Unix/Linux, scripting, software development, QuestaSim, Synplify, Quartus, Vivado Engineering Technology Anduril https://logos.yubhub.co/andurilindustries.com.png Anduril develops state-of-the-art imaging systems for security challenges. https://andurilindustries.com USD 165000 218000 yearly https://job-boards.greenhouse.io/andurilindustries/jobs/5235474007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Boulder, Colorado Boulder Colorado US 2026-09-11 ca817102-b50 Senior FPGA Verification Engineer The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.

The Imaging team is seeking a Senior FPGA Verification Engineer to help design new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.

Responsibilities:

  • Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
  • Creation of written test plans, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Required Qualifications:

  • A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field
  • 8+ years of experience developing HDL firmware for FPGA devices
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
  • Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity
  • Eligible to obtain and maintain an active U.S. Secret security clearance

Preferred Qualifications:

  • Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts
  • Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado

Benefits: Anduril offers a comprehensive, competitive benefits package (available at little to no cost to employees) to support health, recovery, and overall well-being.

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]]> full-time senior $191,000-$253,000 USD FPGA verification, SystemVerilog, OVM/UVM, VHDL, Verilog, RTL design, ASIC/FPGA development, Git, Subversion, ASIC/FPGA lab validation, DFT, manufacturability, production test concepts, Unix/Linux environments, scripting, software development, QuestaSim, Synplify, Quartus, Vivado Engineering Technology Anduril https://logos.yubhub.co/andurilindustries.com.png Anduril develops state-of-the-art imaging systems for security challenges. https://andurilindustries.com USD 191000 253000 yearly https://job-boards.greenhouse.io/andurilindustries/jobs/5235482007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Goleta, California Goleta California US 2026-09-11 f03b555b-d45 ASIC Digital Design, Sr Staff Engineer-18732 Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you're adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization.

Responsibilities:

  • Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
  • Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.
  • Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
  • Mentoring and developing team members, fostering technical growth, and a culture of innovation.
  • Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Requirements:

  • Bachelor’s degree or higher in Electrical Engineering, with 8+ years of complex technical development experience.
  • Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation.
  • Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA), CDC/RDC, DFT, and power optimization.
  • Excellent communication skills and the ability to work independently and collaboratively.
  • Understanding the PCIe and Ethernet standard is a plus.

Benefits:

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.

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]]> employee senior $122000-$183000 Electrical Engineering, Verilog, System Verilog, linting, synthesis, static timing analysis, power optimization, PCIe, Ethernet Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys drives innovations in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. https://careers.synopsys.com CAD 122000 183000 yearly https://careers.synopsys.com/job/mississauga/asic-digital-design-sr-staff-engineer-18732/44408/100460077328?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Mississauga, Ontario Mississauga Ontario CA 2026-09-11 8188c044-ec9 Applications Engineering, Staff Engineer - DFT We are seeking a seasoned professional with a strong background in Electrical or Electronics Engineering to join our team as an Applications Engineering, Staff Engineer - DFT. You will collaborate with customers to evaluate their methodologies and flows, provide valuable insights, and support the successful implementation of Synopsys Test Automation tools.

Responsibilities:

  • Collaborate with customers to evaluate their methodologies and flows, providing valuable insights to our test product business unit.
  • Participate in customer design and flow reviews, consulting on test solutions during design planning, including Memory/SCAN testing architecture, DFT IP insertion, pattern generation, and validation flow.
  • Provide technical support and expertise for customers leveraging Synopsys Test Automation tools across various applications.
  • Work closely with solution architects and R&D teams to align with customer requirements and deliver customized solutions.
  • Communicate effectively in English to support and influence internal and external stakeholders.
  • Keep up-to-date with the latest advancements in DFT methodologies and tools to continuously improve your skill set and contribute to innovative solutions.

The Impact You Will Have:

  • Enhance customer satisfaction by providing expert insights and solutions tailored to their specific needs.
  • Support the successful implementation of Synopsys Test Automation tools, driving customer success across various applications.
  • Contribute to the continuous improvement of our test product business unit through valuable feedback and collaboration.
  • Ensure high-quality DFT solutions that meet industry standards and best practices.
  • Facilitate seamless integration of DFT IP and test solutions in customer designs, improving overall design efficiency and reliability.
  • Strengthen Synopsys' reputation as a leader in chip design and test automation through your technical expertise and customer-centric approach.

Requirements:

  • BE/ME, Btech/Mtech in Electrical/Electronics Engineering or related field.
  • Minimum 5 years of hands-on work experience in ASIC DFT design.
  • Strong knowledge of various DFT methodologies, industrial standards, and practices.
  • Experience with industry-standard DFT tools, simulators, and waveform debug tools.
  • Hands-on experience with DFT circuit insertion, pattern generation, and validation.
  • Strong understanding of chip design, DFT principles, Verilog/System Verilog, and STA.
  • Knowledge of DDR/LPDDR is a plus.

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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]]> full-time staff DFT design, Electrical Engineering, Electronics Engineering, Verilog, System Verilog, STA, DFT tools, simulators, waveform debug tools, DDR, LPDDR Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a company that provides software and services for chip design and verification. It has 420 open roles. https://careers.synopsys.com https://careers.synopsys.com/job/xi-an/applications-engineering-staff-engineer-dft/44408/100466373104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Xi'an, Shaanxi Xi'an Shaanxi CN 2026-09-11 071358fe-51d ASIC Engineer We are seeking a top-notch ASIC engineer to join our Clocks team, responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with various teams to understand clocking requirements, design the physical floorplan of the chip, and explain the programming model to the software team.

As an ASIC engineer, you will architect the clock domain to satisfy functional, physical, and testing design requirements. You will engage with multiple teams to design GPU or CPU clocks, improve Power, Performance, and Area (PPA) of innovative NVIDIA chips, and collaborate with Physical design and timing teams to evaluate clocking concerns.

Responsibilities:

  • Architect the clock domain to satisfy functional, physical, and testing design requirements
  • Engage with multiple teams to design GPU or CPU clocks
  • Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips
  • Collaborate with Physical design and timing teams to evaluate clocking concerns
  • Deliver clock RTL information to GPU, CPU, and SOC verification teams, timing and DFT teams
  • Participate in the end-to-end cycle of ASIC execution

Requirements:

  • BS in Electrical Engineering or equivalent experience (MS preferred)
  • 2+ years of relevant work experience
  • Deep understanding of logic optimization techniques and PPA trade-offs
  • Excellent interpersonal skills and ability to collaborate with multiple teams
  • Experience in RTL design (Verilog), verification, and logic synthesis
  • Strong coding skills in Python or other industry-standard scripting languages

Preferred qualifications:

  • Experience with clocks controller, clocks logic design
  • Understanding of system-level artifacts like power, noise, etc.
  • Experience with scalable designs and architecture
  • Hands-on silicon debug experience

We offer competitive salaries and a generous benefits package. The base salary range is $116,000 - $189,750 for Level 2 and $136,000 - $218,500 for Level 3.

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]]> full-time mid $116,000 - $189,750 for Level 2 and $136,000 - $218,500 for Level 3 RTL design, Verilog, logic synthesis, Python, Electrical Engineering, clocks controller, clocks logic design, scalable designs, silicon debug Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA invented the GPU in 1999 and has since become a leader in parallel computing and artificial intelligence. https://www.nvidia.com USD 116000 218500 yearly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---Clocks-IP_JR2025580?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-09-11 d915f826-ffb Senior Verification Engineer NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

  • B.Tech./ M.Tech or equivalent experience
  • 4+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
  • Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Excellent knowledge of PCIE protocol - Gen3 and above
  • Good understanding of the system level architecture of PCIE/CXL-based designs
  • Perl, Python or similar scripting and SW programming language experience
  • Good debugging and analytical skills
  • Good interpersonal skills & dream to work as a great teammate

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]]> full-time senior PCI Express, UVM, Verilog, SystemVerilog, verification, PCIE protocol, Perl, Python, debugging, analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that creates graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2025156?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-09-11 afefb736-e22 Solutions Engineering, Sr Staff Engineer Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

The Senior Staff Engineer, Solutions Engineering will contribute to product development for IP compilers related to embedded monitoring, test, diagnostic, and repair solutions for 3DIC optical interconnects within the SMS/SHS product portfolio.

Primary Responsibilities

  • Design and develop IP compilers for embedded monitoring, test, diagnostic, and repair solutions targeting 3DIC optical interconnects within the SMS/SHS product line
  • Build and maintain a multiphysics simulation bridge with Ansys, requiring comprehensive technical understanding and full collaboration on integration efforts
  • Apply expertise in optical and photonic chip design, co-packaged opto-electronic systems, and test/diagnostics frameworks to deliver production-ready solutions
  • Develop and refine IC design flows using Verilog and SystemVerilog, ensuring alignment with EDA toolchains and AI-assisted design methodologies
  • Lead technical discussions, provide mentorship to engineering team members, and drive technical decisions that balance innovation with long-term maintainability
  • Produce comprehensive technical documentation to support internal teams and external stakeholders

Impact and Contributions

  • Enable next-generation 3DIC optical interconnect solutions that advance industry capabilities in bandwidth, power efficiency, and system integration
  • Deliver IP compilers that reduce time-to-market for customers developing advanced co-packaged optics and photonic systems
  • Strengthen Synopsys' multiphysics simulation capabilities through direct integration with Ansys platforms
  • Contribute to the technical development and growth of engineering team members through mentorship and knowledge transfer
  • Influence product roadmaps by identifying technical gaps, proposing solutions, and providing technical direction for SMS/SHS offerings
  • Enhance the robustness and scalability of test, diagnostic, and repair frameworks utilized across high-volume semiconductor manufacturing

Required Qualifications

  • Master's degree or PhD in Electrical Engineering, Photonics, or a closely related technical discipline
  • Demonstrated expertise in optical or photonic chip design and co-packaged opto-electronic test, diagnostics, and repair methodologies
  • Strong technical background in multiphysics simulation, including reliability, mechanical, stress, and thermal analysis
  • Comprehensive understanding of IC design flows, with hands-on experience in Verilog and SystemVerilog
  • Proficiency in Python or other scripting languages for automation and workflow development
  • Excellent written and verbal communication skills in English, with demonstrated ability to produce clear, comprehensive technical documentation
  • Proven problem-solving capabilities and ability to address complex technical challenges
  • Willingness to acquire new technical knowledge and contribute to innovative solutions
  • Ability to function effectively as a technical leader and mentor within team environments

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries

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]]> employee senior optical chip design, co-packaged opto-electronic systems, multiphysics simulation, Verilog, SystemVerilog, Python, communication skills, IEEE 1687, 1500, 1838, 1149, EDA tools, AI-assisted design tools Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is the industry leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/yerevan/solutions-engineering-sr-staff-engineer/44408/96459426960?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Yerevan Yerevan 2026-09-10 d8aebec8-f44 DDR/LPDDR IP Design Sr Staff Engineer We are seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.

The successful candidate would be working as part of a highly experienced DDR/LPDDR design and verification team, targeting the current and next generation technology. Theoretical and practical background in DDR or LPDDR is a solid plus.

Key Responsibilities

  • Work on digital design based on predefined RTL coding style including Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT, and synthesis
  • Solid debugging skills and ability to root cause issues including both simulation and silicon
  • Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality
  • Good communication skills for interacting between different design groups and customer support teams are required

Preferred Qualifications

  • Strong desire to learn and explore new technologies
  • Demonstrates good analysis and problem-solving skills
  • Knowledge in interface technologies such as DDR, HBM, UCIe is a plus
  • Scripting experience in Shell, Perl, Python, and TCL is a plus
  • Knowledge of analogic circuit is a plus
  • Interacting with Application Engineers for customer support

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries

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]]> employee senior ASIC design, RTL coding, Verilog, System Verilog, lint, CDC, DFT, synthesis, VCS, Verdi, Spyglass, DC, Formality, DDR, LPDDR, HBM, UCIe, Shell scripting, Perl scripting, Python scripting, TCL scripting, analogic circuit Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys provides software and services used in the design, verification, and manufacture of electronic components and systems. https://careers.synopsys.com https://careers.synopsys.com/job/wuhan/ddr-lpddr-ip-design-sr-staff-engineer/44408/100326868048?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Wuhan, Hubei Wuhan Hubei CN 2026-09-09 786608a5-044 ASIC Design Engineer NVIDIA is looking for an ASIC Design Engineer with proven hardware design and methodology expertise to join our world-class team to help amplify human creativity and intelligence.

The ideal candidate will develop and deploy in-house tools and workflows to support engineering business units across NVIDIA. They will take ownership of tools that verify common design blocks used in all products at NVIDIA and act as a "DevOps" engineer for automated RTL generation.

Responsibilities:

  • Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
  • Take ownership of tools that verify common design blocks used in all products at NVIDIA.
  • Act as a "DevOps" engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
  • Build new workflows and methodologies to ensure smooth integration into various IP development environments.

Requirements:

  • Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 3+ years of proven experience preferred.
  • Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
  • Proficiency in scripting using modern Python and/or Perl.
  • Experience with Unix/Linux shell scripting and Makefiles.
  • Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Nice to have:

  • Prior experience in ASIC verification.
  • Knowledge of Clocks/Resets design and verification.
  • Exposure to CDC related design/verification flows.
  • Exposure to backend flows (Synthesis, Timing, etc).

Salary: 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. Benefits: You will also be eligible for equity and benefits.

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]]> full-time senior hybrid 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3 Verilog, Python, Perl, Unix/Linux shell scripting, Makefiles, ASIC verification, Clocks/Resets design and verification, CDC related design/verification flows, backend flows (Synthesis, Timing, etc) Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that invented the GPU in 1999 and has since evolved to become a leader in parallel computing and artificial intelligence. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-TX-Austin/ASIC-Design-Engineer--Tools-and-Methodology-Development_JR2025219?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-09-09 f16880de-8cf Power Methodology and Analysis Engineer We are seeking a Power Methodology and Analysis Engineer to join our team. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next-generation GPUs and Tegra SOCs.

Key responsibilities include:

  • Continuously improving the performance and efficiency of power analysis tools
  • Developing advanced power optimization tools to empower both front-end and back-end design teams to improve power efficiency
  • Using internally developed tools and industry-standard pre-silicon gate-level and RTL power analysis tools to help improve product power efficiency
  • Developing and sharing best practices for performing pre-silicon power analysis, enhancing internal power tools, and automating best practices
  • Performing comparative power analysis to spot trends and anomalies that warrant more scrutiny
  • Interacting with architects and RTL designers to help them interpret their power data and identify power bugs, and driving them to implement fixes

Requirements:

  • MS with 1-3 years of experience (or PhD preferred) in related fields
  • Basic understanding of concepts of energy consumption, estimation, and low power design
  • Familiarity with Verilog and ASIC design principles, including knowledge of logic cells
  • Good verbal/written English and interpersonal skills, with much collaboration with design teams expected
  • Strong coding skills, preferably in Python, C++
  • Ability to formulate and analyze algorithms, and comment on their time complexity and memory consumption
  • Desire to bring data-driven decision-making and analytics to improve our products

Nice to have:

  • Familiarity with power tools and flow development
  • Hands-on experience leveraging AI tools for engineering productivity

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]]> full-time mid Verilog, ASIC design, Python, C++, power analysis, low power design, power tools, flow development, AI tools, engineering productivity Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/Power-Methodology-and-Analysis-Engineer_JR2025068?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-09-09 4142294b-bc6 Verification Engineer As a Verification Engineer in NVIDIA's MMPLEX team, you will play a crucial role in ensuring the quality and functionality of our hardware IPs.

Responsibilities:

  • Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products.
  • Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
  • Build block/IP testbench based on UVM methodology.
  • Build test run and regression flow. Triage failures in regression and help designer root cause the bug.
  • Work on building various metrics (passing rate, functional coverage, etc) and monitor its health.
  • Take SOC verification on fullchip test environment for IPs.
  • Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
  • Deploy the advanced verification methodology and infrastructure of the SOC/IP.

Requirements:

  • MS in electrical/computer engineering or equivalent experience.
  • 5+ years (MS) working experience.
  • Familiar with advance verification methodology, tools and flow.
  • Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
  • Deep understanding in Verilog and HVL (High-level Verification Language).

Preferred skills:

  • Strong programming skills in Python and C/C++.
  • Having good arch/design experience.
  • At least good at one of the script programming languages: Perl, Shell, Ruby, Python.

NVIDIA offers competitive salaries and a generous benefits package.

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]]> full-time senior Verilog, HVL, verification methodology, UVM methodology, Python, C/C++, Perl, Shell, Ruby Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that delivers cutting-edge IP solutions to various product lines, including datacenter, GeForce, automotive, networking, and more. The company has over 300 team members in its MMPLEX team in Shanghai. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/Senior-Design-Verification-Engineer---Hardware_JR2024382-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai CN 2026-09-09 8358d8a0-e3b Senior ASIC Design Engineer NVIDIA is seeking a Senior ASIC Design Engineer for its Circuit Solutions Group. The engineer will work on micro-architecture and digital design implementation of innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation.

Responsibilities:

  • Lead the micro-architecture and digital design implementation of various IPs
  • Collaborate with architects, circuit designers, and verification engineers
  • Develop scalable RTL designs and execute synthesis and timing analysis
  • Perform functional verification, CDC checks, and formal equivalence
  • Support post-silicon bring-up and debug activities
  • Develop tools and flows, including Agentic AI flows

Requirements:

  • BS in Electrical Engineering, Computer Engineering, or related field; MS or PhD a plus
  • 3+ years of experience in logic design, Verilog, and/or System-Verilog
  • Understanding of physical design and VLSI
  • Experience with multiple clock domains and asynchronous interfaces
  • Exposure to digital systems design and computer architecture
  • Programming skills in PERL or Python
  • Excellent communication and interpersonal skills

Preferred qualifications:

  • Experience with all stages of ASIC design flow
  • Understanding of behavioral real number modeling and low-level digital or mixed-signal design concepts
  • Knowledge of mixed-signal and custom-designed IPs solutions
  • Proficiency in scripting languages like Perl, Tcl, and Makefiles

NVIDIA offers competitive salaries and a comprehensive benefits package.

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]]> full-time senior ASIC design, Digital design, Verilog, System-Verilog, VLSI, PERL, Python, RTL design, Synthesis, Timing analysis, Mixed-signal design, Custom-designed IPs, Tcl, Makefiles, Agentic AI flows Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company is involved in AI, GPU technology, and computing platforms. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2017358?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-09-09 2061c415-63c Principal Post-Silicon Applications Engineer You are a senior technical expert who is called upon when PCIe 6.0 or 7.0 silicon exhibits unexpected behavior under critical timelines.

Over the past decade, you have developed deep expertise in diagnosing complex issues that span analog signal integrity, digital protocol implementation, and system-level interoperability, often working with incomplete information and demanding schedules.

Your knowledge of PCIe link training at 64 GT/s extends beyond theory into practical application.

You understand where PAM4 encoding can obscure margining issues, where FLIT mode negotiation may encounter difficulties, and how subtle impedance discontinuities can compromise bring-up success.

Your experience debugging customer systems has given you the ability to identify power delivery issues from oscilloscope measurements and recognize when firmware assumptions conflict with hardware implementation.

Leading technical discussions with customer architects and internal design teams is a natural extension of your work because you have established credibility through consistent results and deep technical knowledge.

You operate effectively without requiring exhaustive documentation, developing test plans, executing them, adapting as needed, and documenting findings to benefit future engineers.

Traveling approximately twice annually to customer sites or internal laboratories is an expected aspect of the role, and you recognize that on-site presence often accelerates resolution significantly.

At Synopsys, you will work with the most advanced SerDes IP in the industry, and your contributions will directly influence what our customers bring to market.

Responsibilities

  • Provide senior-level technical support to customers during silicon bring-up and production phases for PCIe 6.0, PCIe 7.0, including on-site engagement when critical issues require direct technical presence
  • Lead comprehensive root cause analysis for complex signal integrity, protocol compliance, and interoperability challenges across analog, digital, and system integration layers
  • Utilize advanced laboratory instrumentation including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers to perform precision measurements and isolate failure mechanisms at 64 GT/s and higher data rates
  • Analyze and simulate Verilog/SystemVerilog RTL, collaborating with digital design and firmware teams to resolve issues involving PAM4 encoding, FLIT mode operation, and link training state machine behavior
  • Drive technical engagements with customer engineering teams and system architects, translating technical findings into clear recommendations and design guidance
  • Develop and refine test methodologies, debug procedures, and technical best practices for next-generation SerDes validation and customer deployment
  • Travel approximately twice per year to customer locations or internal development sites for critical bring-up support and technical collaboration

The Impact You Will Have

  • Enable customer tape-outs and production ramps by resolving technical blockers that would otherwise delay significant development programs
  • Establish Synopsys as a recognized technical authority in PCIe 6.0/7.0 through substantive customer partnerships and effective technical problem resolution
  • Provide real-world silicon and system-level insights to IP design, validation, and product development teams, improving quality and reducing time-to-market for future releases
  • Reduce costly silicon re-spins by identifying and resolving subtle issues during initial bring-up phases that would otherwise manifest in volume production
  • Develop the technical capabilities of applications and validation engineers across the organization through knowledge transfer and mentorship
  • Contribute to the technical roadmap for SerDes applications engineering by identifying opportunities to improve tooling, processes, and support infrastructure
  • Build enduring customer relationships that result in design wins and expanded IP adoption across next-generation semiconductor platforms

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related discipline with 10+ years of hands-on experience in post-silicon validation, applications engineering, or SerDes bring-up
  • Extensive expertise with PCIe 6.0 or newer standards, including PAM4 signaling, FLIT mode operation, link training protocols, and compliance testing at 64 GT/s and above
  • Demonstrated proficiency using advanced laboratory equipment including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers for signal integrity and protocol debug
  • Experience analyzing and simulating Verilog or SystemVerilog RTL to diagnose digital design issues affecting silicon behavior
  • Solid understanding of high-speed printed circuit board design, signal integrity principles, power delivery architectures, and system-level integration is highly valuable
  • Willingness to travel approximately twice per year for on-site customer support and internal technical collaboration

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]]> full-time senior hybrid PCIe 6.0, PCIe 7.0, PAM4 signaling, FLIT mode operation, link training protocols, compliance testing, high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, protocol analyzers, Verilog, SystemVerilog RTL Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/porto-salvo/principal-post-silicon-applications-engineer/44408/100305008256?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Porto Salvo, Lisbon District Porto Salvo Lisbon District PT 2026-09-08 a00e9144-424 DDR/LPDDR IP Design Principal Engineer We are seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.

The successful candidate will work as part of a highly experienced DDR/LPDDR design and verification team, targeting current and next-generation technology. A theoretical and practical background in DDR or LPDDR is a solid plus.

Key Responsibilities

  • Work on digital design based on predefined RTL coding style, including Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT, and synthesis
  • Solid debugging skills and ability to root cause issues, including both simulation and silicon
  • Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality
  • Good communication skills for interacting between different design groups and customer support teams

Preferred Qualifications

  • Strong desire to learn and explore new technologies
  • Demonstrates good analysis and problem-solving skills
  • Knowledge in interface technologies such as DDR, HBM, UCIe is a plus
  • Scripting experience in Shell, Perl, Python, and TCL is a plus
  • Knowledge of analogic circuit is a plus
  • Interacting with Application Engineers for customer support

Benefits

  • Comprehensive medical and healthcare plans
  • Time away programs, including ETO and FTO
  • Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: purchase Synopsys common stock at a 15% discount
  • Retirement plans that vary by region and country
  • Competitive salaries

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]]> full-time senior onsite ASIC design, RTL coding, Verilog, System Verilog, lint, CDC, DFT, synthesis, VCS, Verdi, Spyglass, DC, Formality, DDR, LPDDR, HBM, UCIe, Shell scripting, Perl scripting, Python scripting, TCL scripting, analogic circuit Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys provides software and services used in the design, verification, and manufacturing of electronic components and systems. https://careers.synopsys.com https://careers.synopsys.com/job/wuhan/ddr-lpddr-ip-design-principal-engineer/44408/100326868032?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Wuhan, Hubei Wuhan Hubei CN 2026-09-08 43e2d287-16d Sr Staff Applications Engineer, Simulation & Debug You will work as a Sr Staff Applications Engineer, Simulation & Debug at Synopsys, driving customer deployments of VCS and Verdi simulation and debug platforms.

You have spent years in verification, thinking like both designers and engineers, and understand the importance of simulation beyond just running tests.

Your responsibilities include:

  • Driving customer deployments of VCS and Verdi simulation and debug platforms
  • Diagnosing complex technical issues across UVM testbenches and gate-level simulations
  • Leading competitive engagements and benchmarking efforts
  • Collaborating with R&D and product teams to gather customer requirements
  • Developing and optimizing automation scripts in Perl, Python, TCL, Shell, and Make
  • Interfacing across global teams to propose solutions and drive product improvements
  • Supporting customers through technical escalations

This role requires:

  • Bachelor's or Master's in Electronics Engineering or equivalent
  • 5-12 years of hands-on experience in verification or application engineering
  • Deep expertise in simulation technologies, UVM, SystemVerilog Assertions (SVA), and verification methodologies
  • Strong command of HDL languages including Verilog, VHDL, and SystemVerilog
  • Proven experience with gate-level simulation, timing-aware verification, and low power flows using UPF
  • Advanced scripting ability in Perl, Python, TCL, Shell, and Make

You will have the opportunity to enable customers to close verification faster, influence the VCS and Verdi product roadmap, win competitive deals, and accelerate adoption of advanced features.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits.

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]]> full-time senior simulation technologies, UVM, SystemVerilog Assertions (SVA), verification methodologies, Verilog, VHDL, SystemVerilog, gate-level simulation, timing-aware verification, low power flows using UPF, Perl, Python, TCL, Shell, Make, Synopsys Verdi, DPI, C/C++, SystemC, functional safety standards, generative AI technologies, AI-driven EDA workflows Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/bengaluru/sr-staff-applications-engineer-simulation-and-debug/44408/100290788256?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, Karnataka Bengaluru Karnataka IN 2026-09-07 2991c982-5b5 ASIC Digital Design, Sr Staff Engineer Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building RTL that tapes out clean, not almost clean, actually clean, and you know the difference between a subsystem that works in simulation and one that survives silicon. The dopamine rush you get from first-time-right RTL is real, and it is what keeps you coming back to the hardest parts of digital design. You have driven multiple tape-outs and learned that the architecture decisions you make in week two will either save or sink the team in month six. You think in hierarchies, timing paths, and power domains without losing sight of what the block is actually supposed to do. Working with verification teams does not slow you down, it sharpens your thinking, and you write RTL that makes their job possible, not harder.

Responsibilities

  • Own the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and final release
  • Craft subsystem architecture and functional specifications, define micro-architecture, and write production-quality RTL using industry best practices
  • Drive RTL quality checks including lint, CDC, RDC, and work closely with verification teams to ensure functional correctness and coverage closure
  • Integrate and design around standard protocols including PCIe, DDR, UFS, USB, and AMBA-based interconnects
  • Implement low power design techniques across clock gating, power gating, and multi-voltage domains, ensuring power intent is captured and verified
  • Collaborate with logic synthesis, STA, and physical design teams to ensure timing closure, develop synthesis constraints, and resolve equivalence check issues
  • Work with DFT teams to architect scan, MBIST, and other testability features into your subsystems from the start

The Impact You Will Have

  • Your RTL will tape out in production silicon used by leading semiconductor companies building next-generation AI, automotive, and mobile SoCs
  • The subsystems you architect will enable faster time-to-market for Synopsys IP customers who depend on proven, reusable, and robust design blocks
  • Your attention to RTL quality and first-time-right design will reduce verification cycles, implementation iterations, and post-silicon debug time across the product
  • The protocols and low power techniques you implement will directly influence power, performance, and area outcomes in customer chips
  • Your collaboration with cross-functional teams will set the standard for how design, verification, and implementation work together on complex projects
  • The design practices and methodologies you bring will influence how the team approaches architecture, coding standards, and release quality
  • Your ability to drive projects to completion will unlock new IP releases and product milestones that depend on subsystem readiness

Requirements

  • Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or equivalent technical field
  • 8+ years of hands-on RTL design experience with multiple tape-outs under your belt, ideally in complex IP, subsystems, or SoC blocks
  • Deep proficiency with Verilog or SystemVerilog and proven ability to write synthesizable, timing-clean, low power RTL at scale
  • Strong working knowledge of standard protocols such as PCIe, DDR, UFS, USB, or AMBA (AXI, AHB, APB)
  • Hands-on experience with low power design techniques including clock gating, power gating, retention, UPF, and multi-voltage domain architecture
  • Solid understanding of logic synthesis, constraint development (SDC), static timing analysis (STA), and equivalence checking flows
  • Familiarity with DFT concepts including scan insertion, ATPG, MBIST, and how testability requirements shape design architecture, experience working directly with DFT teams is a plus

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family
  • Time away: In addition to company holidays, we have ETO and FTO Programs
  • Family support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
  • Retirement plans: Save for your future with our retirement plans that vary by region and country
  • Competitive salaries

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]]> full-time senior onsite RTL design, Verilog, SystemVerilog, PCIe, DDR, UFS, USB, AMBA, low power design, logic synthesis, STA, DFT Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-engineer/44408/100290788336?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, Karnataka Bengaluru Karnataka IN 2026-09-07 2b4b63c9-778 ASIC Design and Verification Intern, SOC - 2027 The NVIDIA SOC group is looking for ASIC Design and Verification Interns to join the SysASIC and Clock teams. In this position, you will participate in the design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic for latest NVIDIA products. You will work closely with global teams across Architecture, ASIC Design, Verification, DFT, Physical Design, Firmware, and Software.

Responsibilities

  • Participate in RTL design and verification of SysASIC and clock-related IPs
  • Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions
  • Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification
  • Collaborate with cross-functional teams to improve design quality, verification coverage, and development efficiency
  • Develop scripts, automation tools and AI agent to improve design and verification flows

Requirements

  • Pursuing a BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Understanding of digital logic design and front-end ASIC development flow, including RTL design, simulation, synthesis, STA, lint, and CDC/RDC
  • Familiarity with clocking concepts, such as clock gating, clock-domain crossing, reset synchronization, PLLs, and timing fundamentals
  • Proficiency in Verilog and/or SystemVerilog; knowledge of UVM, SVA, or functional coverage is a plus
  • Familiarity with formal verification concepts and tools, including property specification, assertion-based verification (SVA), equivalence checking, or formal property verification
  • Experience with Python, Perl, Tcl, shell scripting, C, or C++ is preferred
  • Familiarity with Linux development environments and common EDA tools
  • Strong analytical and debugging skills, attention to detail, and willingness to learn
  • Good English communication skills and the ability to work effectively in a global team

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]]> internship ASIC design, Verification, RTL design, SystemVerilog, Verilog, Formal verification, Clocking concepts, Digital logic design, Front-end ASIC development flow, UVM, SVA, Functional coverage, Python, Perl, Tcl, Shell scripting, C, C++, Linux development environments, EDA tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and now powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Design-and-Verification-Intern--SOC---2027_JR2024860?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai CN 2026-09-06 28711c66-d4d ASIC Digital Design, Sr Staff Engineer - 18603 Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.

You will:

  • Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
  • Optimize designs to meet timing, power, and area targets across multiple process nodes
  • Develop Perl automation for design generation and flow integration
  • Collaborate with cross-functional teams to resolve timing and power challenges
  • Contribute to design reviews and methodology development

Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products. You will contribute to a major revenue-generating product line for Synopsys. Your work will define performance characteristics for customer systems-on-chip. Your automation will improve design efficiency across the engineering team. Your expertise will influence architectural decisions for future products.

Requirements:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of ASIC digital design experience with RTL ownership in production silicon
  • Expert Verilog proficiency for timing-critical designs
  • Strong Perl scripting skills for design automation
  • Deep knowledge of synthesis, timing analysis, and power optimization
  • Experience with PHY IP or high-speed interfaces is preferred

Benefits include comprehensive health, wellness, and financial benefits, such as medical and healthcare plans, time away, family support, ESPP, retirement plans, and competitive salaries.

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]]> full-time senior $159000-$239000 ASIC digital design, RTL design, Verilog, Perl scripting, synthesis, timing analysis, power optimization, PHY IP, high-speed interfaces Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys delivers industry-leading silicon design, IP, simulation and analysis solutions, and design services. https://careers.synopsys.com USD 159000 239000 yearly https://careers.synopsys.com/job/sunnyvale/asic-digital-design-sr-staff-engineer-18603/44408/100144992704?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Sunnyvale, California Sunnyvale California 2026-09-04 11f7dd7a-278 Digital Design Verification Engineering Internship (16-Month Co-op) Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally.

As a Digital Design Verification Engineering Intern, you'll be involved in verifying current and next-generation Backplane Ethernet, PCIe, SATA, USB 2/3, and MIPI CPHY/DPHY SERDES products.

Your day-to-day responsibilities will include:

  • Defining and tracking Verification Testplans to ensure comprehensive coverage of design functionality
  • Designing and writing constrained-random SystemVerilog testbenches using UVM (Universal Verification Methodology) and directed testbenches for ATE/Customer applications
  • Creating and examining Functional Coverage and writing SystemVerilog assertions to validate design behavior
  • Debugging RTL and gate-level simulation failures, performing Code Coverage Analysis and Closure, and tracking bugs using tools such as Jira
  • Leveraging AI to enhance verification tasks and workflows, gaining hands-on experience with cutting-edge technologies while collaborating with design engineers in Portugal and verification teams in Cairo

You'll need:

  • Currently pursuing a Bachelor's degree in Computer Engineering, Electrical Engineering, or a related discipline with previous co-op or internship experience
  • Strong interest in digital design and verification, supported by relevant coursework
  • Proficiency in scripting languages like Perl or Python
  • Comprehensive knowledge of Verilog and/or SystemVerilog language
  • Basic proficiency with Unix/Linux shell environments
  • Confident communication and initiative – you're comfortable asking questions, connecting with team members across different time zones and locations, and proactively seeking guidance when encountering challenges
  • Independent and resourceful – we're looking for interns who take ownership of their work, remove their own blockers, and actively pursue learning and growth opportunities

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]]> internship hybrid $0-$0 SystemVerilog, UVM, Verilog, Perl, Python, Unix/Linux Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. https://careers.synopsys.com https://careers.synopsys.com/job/mississauga/digital-design-verification-engineering-internship-16-month-co-op/44408/100144992768?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Mississauga, Ontario Mississauga Ontario CA 2026-09-04 91ac2b8c-9fa Senior Digital Design Engineer, Air Dominance and Strike Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology.

We are looking for a Senior FPGA Design Engineer to join our Air Dominance and Strike (AD&S) Electrical Engineering Team in Costa Mesa, CA.

In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded systems, avionics, and mission-critical hardware.

Responsibilities

  • Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC-based systems.
  • Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans.
  • Own FPGA designs or major functional blocks from architecture through integration, timing closure, and lab debug.
  • Develop and execute simulation, synthesis, and implementation flows, including timing and resource closure.
  • Debug functional, timing, and integration issues in simulation and on hardware.
  • Support board bring-up, lab validation, and system integration on target platforms.
  • Collaborate with hardware, embedded software, systems, and verification engineers to deliver complete solutions.
  • Participate in design reviews, code reviews, and technical documentation.
  • Contribute to reusable design practices, coding standards, and development workflows.
  • Support rapid prototyping while maintaining the engineering rigor required for production hardware.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of FPGA, ASIC, or closely related digital design experience.
  • Proficiency in VHDL and/or Verilog/SystemVerilog.
  • Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
  • Hands-on debug experience in simulation and on hardware.
  • Strong digital design fundamentals, including clocking, resets, state machines, CDC awareness, and interface design.
  • Proficiency with Linux-based development environments, Git-based workflows, and Tcl and/or Python scripting.
  • Strong written and verbal communication skills.
  • Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications

  • 12+ years of FPGA development experience.
  • Experience owning a major functional block, subsystem, or full FPGA design from concept through integration.
  • Familiarity with AMD (Xilinx), Intel/Altera, or Lattice FPGA development environments.
  • Experience with embedded systems and hardware/software co-design, including AMD (Xilinx) Vitis or similar tooling.
  • Familiarity with common high-speed or embedded interfaces such as Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, or MIL-STD-1553.
  • Familiarity with DO-254 or similar military or safety-critical development standards.
  • Experience building or improving reusable IP, verification infrastructure, CI/CD flows, or team workflows.
  • Familiarity with modern build and development tooling such as Jira, automated regression infrastructure, and reproducible build environments.

Benefits Anduril offers top-tier benefits for full-time employees, including comprehensive health insurance, retirement savings plans, and paid time off.

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]]> full-time senior $166,000-$220,000 USD FPGA design, VHDL, Verilog, SystemVerilog, digital design, Linux-based development environments, Git-based workflows, Tcl scripting, Python scripting, AMD (Xilinx), Intel/Altera, Lattice FPGA development environments, embedded systems, hardware/software co-design, Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, MIL-STD-1553, DO-254 Engineering Technology Anduril Industries https://logos.yubhub.co/anduril.com.png Anduril Industries is a defense technology company that brings advanced technology to the defense industry. https://anduril.com USD 166000 220000 yearly https://job-boards.greenhouse.io/andurilindustries/jobs/5228714007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Costa Mesa, California Costa Mesa California US 2026-09-03 3c58ef40-38c Silicon Validation Engineer We are seeking a Silicon Validation Engineer to join our team at Synopsys, a leading provider of engineering solutions from silicon to systems.

As a Silicon Validation Engineer, you will validate SerDes PHYs that power the systems running the world, and the lab you work in will have the tools to do it right.

Responsibilities:

  • Test silicon implementations of high-speed SerDes PHYs using state-of-the-art lab equipment including oscilloscopes, network analyzers, and signal integrity tools
  • Debug silicon behavior and supporting hardware when test results do not match expectations, tracing issues across the analog circuit, test board, and measurement setup
  • Run characterization tests across PVT corners and operating conditions, then create detailed test reports that communicate results to design and product teams
  • Design and build custom test boards and hardware solutions to support bring-up, debug, and characterization of new PHY IP
  • Program FPGAs in Verilog to generate test patterns, control interfaces, and automate test sequences for protocols like USB, PCIe, SATA, and Ethernet
  • Write test automation scripts in Python or MATLAB to streamline data collection, analysis, and reporting
  • Collaborate with analog designers to investigate circuit behavior, apply theoretical knowledge to explain performance limits, and validate design assumptions in silicon

Requirements:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • Solid understanding of analog IC circuit design and behavior, especially in high-speed mixed-signal environments
  • Strong debugging skills with the ability to isolate issues across silicon, hardware, firmware, and test setup
  • Hands-on experience with lab equipment including oscilloscopes, network analyzers, signal generators, and power supplies
  • Software programming experience in MATLAB, Python, or similar environments for test automation and data analysis
  • FPGA programming knowledge using Verilog for test pattern generation and protocol control
  • Familiarity with high-speed interface protocols such as USB, PCI Express, SATA, or Ethernet is a strong plus
  • Experience with NRZ and PAM4 signaling, equalization techniques, or SerDes architecture is a plus

Benefits:

  • Comprehensive range of health, wellness, and financial benefits
  • Annual bonus, equity, and other discretionary bonuses may be eligible
  • Competitive total rewards package

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]]> full-time senior onsite $108000-$162000 analog IC circuit design, high-speed mixed-signal environments, debugging, lab equipment, MATLAB, Python, Verilog, FPGA programming, high-speed interface protocols, NRZ and PAM4 signaling, equalization techniques, SerDes architecture Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com USD 108000 162000 yearly https://careers.synopsys.com/job/hillsboro/silicon-validation-engineer/44408/99827095376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hillsboro, Oregon Hillsboro Oregon US 2026-08-28 17e5d7c9-f7e Applications Engineering, Sr Staff Engineer You are a highly motivated and innovative individual with a strong background in emulation and prototyping methodologies. You will collaborate closely with R&D and customers on hardware-assisted verification products, driving all aspects of the technology life cycle, from development to product sign-off and customer deployment.

Responsibilities:

  • Collaborating closely with R&D and customers on hardware-assisted verification products.
  • Driving all aspects of the technology life cycle, from development to product sign-off and customer deployment.
  • Defining test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.
  • Becoming an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.
  • Leveraging your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.
  • Adapting to recognized best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.
  • Working with designs from varied verticals to enable and support key ZeBu products in early-stage development.

The Impact You Will Have:

  • Enhancing Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.
  • Improving the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.
  • Providing expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.
  • Ensuring successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.
  • Supporting the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.
  • Facilitating the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.

Requirements:

  • BSEE/MS with 10+ years of related experience.
  • Expertise in Emulation and/or Prototyping flows, systems, and methodologies.
  • Strong proficiency in Verilog, System Verilog, VHDL and C/C++
  • Understanding of verification concepts and experience with functional simulators.
  • Experience with scripting languages like Python and Tcl
  • Knowledge in Simulation flows, Assertion, DPI, and Transactors.
  • Complex problem-solving and debugging skills.
  • Strong communication skills and the ability to interact with customers and peers.
  • Knowledge in synthesis and timing analysis concepts (preferred).
  • Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).
  • Experience with Xilinx & Altera architecture and toolchains (preferred).
  • Protocols like PCIe, USB, Ethernet, DRAMs, HBM, NAND Flash (preferred).
  • Computing systems like CPU architecture, OS (preferred)
  • Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).
  • DFT solutions (preferred)

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]]> full-time senior Verilog, System Verilog, VHDL, C/C++, Python, Tcl, Emulation, Prototyping, synthesis, timing analysis, Xilinx, Altera, PCIe, USB, Ethernet, DRAMs, HBM, NAND Flash, CPU architecture, OS, DFT solutions Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys drives innovations in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. https://careers.synopsys.com https://careers.synopsys.com/job/seongnam-si/applications-engineering-sr-staff-engineer/44408/99783027792?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Seongnam-si, Gyeonggi-do Seongnam-si Gyeonggi-do KR 2026-08-27 172aa622-c0a System Software Engineer - Performance Verification Infrastructure Join NVIDIA's GPU Performance Infrastructure team as a System Software Engineer - Performance Verification Infrastructure. You'll be part of a new journey in validating and shipping next-generation GPU architectures. This role influences the entire lifecycle of GPU performance verification, from early-stage modelling to post-silicon validation.

Responsibilities:

  • Build and develop end-to-end performance verification infrastructure.
  • Create scalable data pipelines to surface performance metrics from simulation, emulation, and silicon environments.
  • Collaborate with GPU architects to craft infrastructure for performance verification of upcoming architectures.
  • Work with hardware teams to automate and accelerate verification workflows, enabling faster GPU build iteration.
  • Provide insights to GPU architects to understand current performance and model industry-leading performance for future builds.
  • Improve daily workflows for top chip architects, contributing to the creation of the next generation of GPUs.

Requirements:

  • BS/MS in Computer Science, Computer Engineering, or equivalent experience.
  • 3+ years of software engineering experience with C++ and Python.
  • Strong computer science fundamentals, including data structures, algorithms, object-oriented programming, and system design.
  • Verilog basics are a strong plus.
  • Experience with chip and/or system simulation/emulation is a strong plus.
  • Exposure to GPU/CPU/SoC chip performance verification and/or profiling on simulation/emulation/silicon is a strong plus.
  • Familiarity with AI development tools.
  • Excellent interpersonal skills.

Benefits:

  • Equity
  • Benefits package

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]]> full-time senior C++, Python, Computer Science, Algorithms, Data Structures, Object-Oriented Programming, System Design, Verilog, Chip Simulation, Emulation, GPU Performance Verification, Profiling, AI Development Tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company is known for its GPU technology. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/System-Software-Engineer---Performance-Verification-Infrastructure_JR2021574?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-26 d0d839c1-f6f DFT Application Engineer Manager We are seeking a DFT Application Engineer Manager to join our Shanghai AE team. The successful candidate will lead the Shanghai AE team to drive and win TestMAX engagements, provide consultation for test solutions during design planning and budgeting, and implement design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models.

Responsibilities may include:

  • Leading Shanghai AE team to drive and win TestMAX engagements
  • Consultation for test solutions during design planning/budgeting
  • Test methodology design rules checking during RTL coding stages
  • Implementation of design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models
  • Architects and implements solutions for built-in self-test (Memory and Logic BIST) circuitry to test devices in the field
  • Participations in customer’s design and flow reviews
  • Diagnostics study and debug
  • Provides methodologies for test automation flow integration with design planning, RTL parser, scan synthesis, physical design, and sign-off verification tools (static timing, simulation, formal verification)
  • Develops white papers on methodology and other documentation as may be required for projects
  • Provides technical consulting/expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios

Key qualifications:

  • 8-10 years project DFT execution experience, team leadership experience is a plus for this position
  • Excellent soft skills on communication and cross team work experience
  • Excellent knowledge of Hardware Description Language (Verilog/VHDL) and RTL design
  • Excellent knowledge in scripting, TCL and Perl are preferred
  • Ability and desire to dig into and solve complex parallel programming challenges
  • Excellent debug and problem-solving skills
  • Excellent verbal and written communication skills
  • Excellent knowledge of the Linux OS and tools
  • Desire to learn and explore new technologies
  • Design and verification experience are a plus
  • Knowing Design-for-testing concept is a plus
  • Prefer to have a long-term internship (9 or 18 months) and finish Master thesis in Synopsys is a plus

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]]> full-time senior DFT, TestMAX, Verilog, VHDL, RTL design, Scripting, TCL, Perl, Linux OS, Agentic AI development flow, Cursor, VS Code, IC design flow, VLSI implementation flow, English communication skill Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys delivers industry-leading silicon design, IP, simulation and analysis solutions, and design services. The company enables customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/shanghai/dft-application-engineer-manager/44408/99658152512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai 2026-08-25 23619a6e-e2d Senior SRAM Engineer We are seeking a Senior SRAM Engineer to join our Full Custom Memory (FCM) team at NVIDIA. The FCM team designs specialized RAM implementations across NVIDIA's wide array of processing chips. You will design best-in-class SRAM circuits using state-of-the-art technology processes, optimize circuits for performance, area, and power, collaborate with mask designers, verify functionality, and improve design automation flows.

Responsibilities:

  • Design best-in-class SRAM circuits using state-of-the-art technology processes
  • Optimize circuits for performance, area, and power
  • Collaborate with mask designers to craft high-quality and dense pitch-matched layout
  • Verify functionality, electrical integrity, and robustness
  • Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon

Requirements:

  • BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering
  • Minimum 12 years of circuit design experience
  • Strong understanding of SRAM and memory design techniques and macro/block development

Preferred Qualifications:

  • Self-motivation, attention to detail, clear data analysis and presentation skills
  • Familiarity with industry tools such as Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers
  • Background with developing and using various flows and methodologies, including: Static Timing Analysis, EM and IR analysis, Formal Functional Verification
  • Experience with scripting languages - Perl, Python, Shell, Verilog

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]]> full-time senior remote Electrical Engineering, Computer Engineering, Circuit Design, SRAM design, Memory design, Cadence Virtuoso, SPICE simulators, Static Timing Analysis, EM and IR analysis, Formal Functional Verification, Perl, Python, Shell, Verilog Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA invented the GPU in 1999 and has since evolved to become a leader in parallel computing, redefining modern computer graphics and igniting modern AI. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-SRAM-Engineer_JR2023623?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-25 b4abadf8-eb4 Architecture Energy Modeling Engineer - New College Grad 2026 NVIDIA is seeking an Architecture Energy Modeling Engineer to join our Power Modeling, Methodology and Analysis Team. The successful candidate will be responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient. This includes building energy models that integrate into architectural simulators, RTL simulation, emulation, and silicon platforms.

Key responsibilities include:

  • Developing Machine Learning-based power models to analyze and reduce power consumption of NVIDIA GPUs.
  • Collaborating with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next-generation GPUs, CPUs, and Tegra SOCs.
  • Working with architects, designers, and performance engineers to develop an energy-efficient GPU.
  • Identifying key design features and workloads for building Machine Learning-based unit power/energy models.
  • Developing and owning methodologies and workflows to train models using ML and/or statistical techniques.
  • Improving the accuracy of trained models by using different model representations, objective functions, and learning algorithms.
  • Developing methodologies to estimate data movement power/energy accurately.
  • Correlating the predicted energy from models built at different stages of the design cycle, with the goal of bridging early estimates to silicon.
  • Working with performance infrastructure teams to integrate power/energy models into their platforms to enable combined reporting of performance and power for various workloads.
  • Developing tools to debug energy inefficiencies observed in various workloads run on silicon, RTL, and architectural simulators.
  • Prototyping new architectural features, building an energy model for those new features, and analyzing the system impact.
  • Identifying, suggesting, and/or participating in studies for improving GPU perf/watt.

The ideal candidate will have:

  • A Master's or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • Strong coding skills, preferably in Python, C++.
  • A background in machine learning, AI, and/or statistical modeling.
  • A background in computer architecture and interest in energy-efficient GPU designs.
  • Familiarity with Verilog and ASIC design principles is a plus.
  • The ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.
  • A basic understanding of fundamental concepts of energy consumption, estimation, and low power design.
  • A desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.
  • Good verbal/written communication and interpersonal skills.

NVIDIA offers equity and benefits to its employees.

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]]> full-time entry Machine Learning, Python, C++, Electrical Engineering, Computer Engineering, Computer Science, Statistical Modeling, Computer Architecture, Verilog, ASIC design principles Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Architecture-Energy-Modeling-Engineer---New-College-Grad-2026_JR2023398?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-22 572afa7e-99d Senior Architecture Energy Modeling Engineer NVIDIA is seeking a Senior Architecture Energy Modeling Engineer to join the Power Modeling, Methodology and Analysis Team. The team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient.

The successful candidate will develop Machine Learning-based power models to analyze and reduce power consumption of NVIDIA GPUs. They will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next-generation GPUs, CPUs, and Tegra SOCs.

Key responsibilities include:

  • Developing energy-efficient GPU designs
  • Building Machine Learning-based unit power/energy models
  • Identifying key design features and workloads for model training
  • Improving model accuracy using different representations, objective functions, and learning algorithms
  • Estimating data movement power/energy accurately
  • Correlating predicted energy from models built at different stages of the design cycle
  • Integrating power/energy models into performance infrastructure platforms
  • Debugging energy inefficiencies and suggesting solutions
  • Prototyping new architectural features and analyzing system impact

Requirements:

  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
  • 5+ years of experience
  • Strong coding skills in Python, C++
  • Background in machine learning, AI, and/or statistical modeling
  • Background in computer architecture and interest in energy-efficient GPU designs
  • Familiarity with Verilog and ASIC design principles is a plus

NVIDIA offers equity and benefits to its employees.

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]]> full-time senior Python, C++, Machine Learning, AI, Statistical Modeling, Computer Architecture, Energy-Efficient Design, Verilog, ASIC Design Principles Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Architecture-Energy-Modeling-Engineer_JR2022457?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-22 06f4031f-d44 Verification Engineer - PCIE NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • Responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • Collaborating with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

  • B.Tech./ M.Tech. with 2+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog
  • Background with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Excellent problem solving skills
  • Knowledge of PCIE protocol - Gen3 and above
  • Proficiency in Testbench development using SystemVerilog
  • Perl, Python or similar scripting and SW programming language experience
  • Good debugging and analytical skills

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]]> full-time mid ASIC design, verification methodologies, UVM, SystemVerilog, Verilog, PCI Express, IP verification, PCIE protocol, Testbench development, Perl, Python, debugging and analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a computing company that transforms the way graphics are used to solve complex problems in computer science. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2023400?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-08-21 ff866a1c-9a3 Senior Verification Engineer, PCIE NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

  • B.Tech./ M.Tech or equivalent experience
  • 5+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
  • Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Excellent knowledge of PCIE protocol - Gen3 and above
  • Good understanding of the system level architecture of PCIE/CXL-based designs
  • Perl, Python or similar scripting and SW programming language experience
  • Good debugging and analytical skills
  • Good interpersonal skills & dream to work as a great teammate

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]]> full-time senior ASIC design, Verification methodologies, UVM, SystemVerilog, Verilog, PCI Express, USB, SATA, PCIE protocol, Python, Perl, Debugging, Analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a computing company that produces GPUs and SOCs for various applications including consumer graphics, self-driving cars, and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer--PCIE_JR2023401?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-08-21 b756b163-f6c Digital Design Engineer, Air Dominance and Strike Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology.

The Air Dominance and Strike (AD&S) Electrical Engineering Team develops high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms.

We are looking for an FPGA Design Engineer to join our team in Costa Mesa, CA. In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded systems, avionics, and mission-critical hardware.

Responsibilities

  • Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC-based systems.
  • Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans.
  • Own FPGA designs or major functional blocks from architecture through integration, timing closure, and lab debug.
  • Develop and execute simulation, synthesis, and implementation flows, including timing and resource closure.
  • Debug functional, timing, and integration issues in simulation and on hardware.
  • Support board bring-up, lab validation, and system integration on target platforms.
  • Collaborate with hardware, embedded software, systems, and verification engineers to deliver complete solutions.
  • Participate in design reviews, code reviews, and technical documentation.
  • Contribute to reusable design practices, coding standards, and development workflows.
  • Support rapid prototyping while maintaining the engineering rigor required for production hardware.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
  • 2+ years of FPGA, ASIC, or closely related digital design experience.
  • Proficiency in VHDL and/or Verilog/SystemVerilog.
  • Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
  • Hands-on debug experience in simulation and on hardware.
  • Strong digital design fundamentals, including clocking, resets, state machines, CDC awareness, and interface design.
  • Proficiency with Linux-based development environments, Git-based workflows, and Tcl and/or Python scripting.
  • Strong written and verbal communication skills.
  • Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications

  • 4+ years of FPGA development experience.
  • Experience owning a major functional block, subsystem, or full FPGA design from concept through integration.
  • Familiarity with AMD (Xilinx), Intel/Altera, or Lattice FPGA development environments.
  • Experience with embedded systems and hardware/software co-design, including AMD (Xilinx) Vitis or similar tooling.
  • Familiarity with common high-speed or embedded interfaces such as Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, or MIL-STD-1553.
  • Familiarity with DO-254 or similar military or safety-critical development standards.
  • Experience building or improving reusable IP, verification infrastructure, CI/CD flows, or team workflows.
  • Familiarity with modern build and development tooling such as Jira, automated regression infrastructure, and reproducible build environments.

Benefits Anduril offers top-tier benefits for full-time employees, including comprehensive health insurance, retirement savings plans, and paid time off.

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]]> full-time senior onsite $146,000-$194,000 USD FPGA design, RTL implementation, VHDL, Verilog, SystemVerilog, digital design, embedded systems, Linux-based development environments, Git-based workflows, Tcl scripting, Python scripting, FPGA development experience, AMD (Xilinx) FPGA development environments, Intel/Altera FPGA development environments, Lattice FPGA development environments, embedded systems and hardware/software co-design, DO-254 or similar military or safety-critical development standards Engineering Technology Anduril Industries https://logos.yubhub.co/anduril.com.png Anduril Industries is a defense technology company that brings advanced technology to the defense industry. https://anduril.com USD 146000 194000 yearly https://job-boards.greenhouse.io/andurilindustries/jobs/5214070007?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Costa Mesa, California Costa Mesa California US 2026-08-20 cc6f874c-e6e Ph.D. Research Hardware Intern NVIDIA is seeking strategic, ambitious, and creative individuals for a Ph.D. Research Hardware Internship.

You will design and implement novel approaches to circuit and VLSI design, collaborate with teams, and transfer research to product groups.

Responsibilities:

  • Design and implement novel approaches to circuit and VLSI design, including ASIC development and advanced EDA methodologies.
  • Collaborate with other team members, teams, and/or external researchers.
  • Transfer your research to product groups to enable new products or types of products. Deliverable results include prototypes, patents, products, and/or publishing original research.

Requirements:

  • Actively enrolled in a Ph.D. program in Computer Science, Electrical Engineering, or a related field.
  • Anticipated graduation date must be clearly indicated on a resume or CV.
  • Prior experience or knowledge requirements may include:
  • Programming skills: Python, C, C++, Perl, MATLAB, CUDA, Verilog, SystemVerilog.
  • CAD tool packages: Cadence, Synopsys, HFSS.
  • ML Frameworks: PyTorch.
  • EDA tools.
  • Strong background in research with publications at top conferences and/or patents.
  • Excellent communication and collaboration skills.

Preferred qualifications:

  • Research experience in areas such as circuit design, ASIC and VLSI, electronic design automation.

Benefits:

  • Hourly rate: 38 USD - 94 USD.
  • Intern benefits.

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]]> internship 38 USD - 94 USD Python, C, C++, Perl, MATLAB, CUDA, Verilog, SystemVerilog, Cadence, Synopsys, HFSS, PyTorch, Circuit Design, ASIC and VLSI, Electronic Design Automation Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneers accelerated computing to tackle challenges in AI, digital twins, and various industries. https://www.nvidia.com USD 38 94 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--PhD-Research-Hardware_JR2023855?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 f5a7e53a-684 NVIDIA 2027 Internships: Computer Architecture NVIDIA offers a 12-week full-time internship program for students pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. As an intern, you will work on projects that have a measurable impact on our business, focusing on Computer Architecture.

Responsibilities:

  • Work on projects related to Computer Graphics, Deep Learning, Ray Tracing, Parallel Programming, Memory Architecture, or High-Performance Computing Systems
  • Gain experience in Digital Systems, VLSI Design, GPU or CPU Architecture, Computer Arithmetic, CMOS Transistors and Circuits, Computer Organization, Computer System Design
  • Develop skills in Deep Learning, Modelling/Performance Analysis, Parallel Programming, Hardware Control Programming, GPU Acceleration, Parallel Processing (CUDA), High-Performance Computing (HPC), Embedded Systems

Requirements:

  • Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
  • Anticipated graduation date (month and year) must be clearly indicated on a resume or CV
  • Experience in one or more of the focus areas: Computer Graphics, Deep Learning, Ray Tracing, Parallel Programming, Memory Architecture, or High-Performance Computing Systems

Preferred qualifications:

  • Prior experience or knowledge in Verilog, SystemVerilog, VHDL, CUDA, Linux, C, C++, Python, Perl, Modern Graphics APIs (DirectX, OpenGL, Vulkan), GPU Computing (CUDA, OpenCL), Revision Control (Perforce, Git), HPC (MPI, OpenMP)

Benefits:

  • Competitive hourly rate ($20-$71 per hour)
  • Eligibility for Intern benefits

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]]> internship $20-$71 per hour Electrical Engineering, Computer Engineering, Computer Graphics, Deep Learning, Parallel Programming, Memory Architecture, High-Performance Computing Systems, Digital Systems, VLSI Design, GPU or CPU Architecture, Verilog, SystemVerilog, VHDL, CUDA, Linux, C, C++, Python, Perl, Modern Graphics APIs, GPU Computing, Revision Control, HPC Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneers accelerated computing to tackle challenges in various industries, including gaming, robotics, self-driving cars, and healthcare. https://www.nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Computer-Architecture_JR2023489?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 72bb60f0-119 NVIDIA 2027 Internships: Hardware ASIC Design NVIDIA offers a 12-week full-time internship for students pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. As an intern, you will work on projects that have a measurable impact on our business.

Responsibilities:

  • Work on projects related to Hardware ASIC Design
  • Utilize skills in RTL Design and HDL, Digital Systems, Digital Design, VLSI Design, and more
  • Collaborate with industry-leading Hardware teams

Requirements:

  • Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
  • Anticipated graduation date must be clearly indicated on a resume or CV
  • Course or internship experience related to areas such as RTL Design and HDL, Digital Systems, Digital Design, VLSI Design, and more

Preferred qualifications:

  • Experience with programming skills and technologies such as SystemVerilog, Verilog, VHDL, UVM, Perl, TCL, C, C++, Python, Linux, and Testbench Tools

Benefits:

  • Competitive hourly rate ($20-$71 USD)
  • Eligibility for Intern benefits

Applications are accepted on an ongoing basis.

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]]> internship $20-$71/hour Electrical Engineering, Computer Engineering, RTL Design and HDL, Digital Systems, Digital Design, VLSI Design, SystemVerilog, Verilog, VHDL, UVM, Perl, TCL, C, C++, Python, Linux, Testbench Tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneers accelerated computing to tackle challenges in various industries, including gaming, robotics, self-driving cars, and healthcare. https://nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Hardware-ASIC-Design_JR2023486?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 60c9be85-9ed Verification Engineer - PCIE NVIDIA is seeking a Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world's leading GPUs and SOCs.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Responsibilities:

  • You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • You will build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • You are expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Requirements:

  • B.Tech./ M.Tech. with 2+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog
  • Experience with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Benefits:

  • Competitive salaries
  • Generous benefits package

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]]> full-time mid Verilog, SystemVerilog, UVM, VMM, PCI Express, USB, SATA, PCIE protocol, Perl, Python, debugging, analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that creates graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2019559?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-08-19 5b1f623f-b80 NVIDIA 2027 Internships: Mixed Signal Design NVIDIA is offering a 12-week full-time internship for students pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.

The internship will involve working on projects with a measurable impact on the business, focusing on mixed signal design.

Requirements:

  • Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
  • Anticipated graduation date must be clearly indicated on a resume or CV
  • Course or internship experience related to:
  • Analog Fundamentals
  • Analog Simulation
  • Layout and Physical Design Fundamentals
  • CMOS Analog Circuit Design
  • Lab Testing Equipment
  • Prior experience or knowledge in programming skills and technologies such as Verilog, SystemVerilog, VHDL, Perl, Python, SPICE/HSPICE, Simulink, Cadence Virtuoso, Synopsys

Internship Details:

  • 12-week full-time internship
  • Hourly rate: $20 - $71 per hour
  • Eligible for Intern benefits

Applications are accepted on an ongoing basis.

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]]> internship $20 - $71 per hour Analog Fundamentals, Analog Simulation, Layout and Physical Design Fundamentals, CMOS Analog Circuit Design, Lab Testing Equipment, Verilog, SystemVerilog, VHDL, Perl, Python, SPICE/HSPICE, Simulink, Cadence Virtuoso, Synopsys Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing to tackle challenges in AI, digital twins, and various industries. https://nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Mixed-Signal-Design_JR2023502?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 ce4f3393-19f Hardware Verification Intern NVIDIA offers a 12-week full-time internship in Hardware Verification. As an intern, you will work on projects with a measurable impact on the business. You will be part of an industry-leading Hardware team, focusing on tackling challenges in AI, digital twins, and other areas.

To be considered, you must be actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. Your anticipated graduation date must be clearly indicated on your resume or CV.

Relevant course or internship experience includes:

  • SystemVerilog and UVM
  • VLSI Design, Digital Design, Functional Coverage
  • Assertion-Based Verification, Formal Verification, GPU or processor Verification or Validation
  • Debugging and Simulation Tools
  • Random functional testing, writing test plans, directed/random diagnostics
  • CPU and GPU Architecture, Computer Architecture, Software Infrastructure

Prior experience or knowledge requirements may include programming skills and technologies such as UVM, Verilog, SystemVerilog, VHDL, Perl, TCL, C, C++, Python, and Linux.

The hourly rate for this internship is between 20 USD and 71 USD, depending on the position, location, year in school, degree, and experience. You will also be eligible for Intern benefits.

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]]> internship 20 USD - 71 USD SystemVerilog, UVM, VLSI Design, Digital Design, Functional Coverage, Assertion-Based Verification, Formal Verification, GPU or processor Verification or Validation, Debugging, Simulation Tools, Random functional testing, test plans, directed/random diagnostics, CPU and GPU Architecture, Computer Architecture, Software Infrastructure, Verilog, VHDL, Perl, TCL, C, C++, Python, Linux Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneers accelerated computing to tackle challenges in various industries. https://nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Hardware-Verification_JR2023500?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 b58a5c08-442 NVIDIA 2027 Internships: Digital Circuit Design NVIDIA is offering a 12-week full-time internship for students pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field. As an intern, you will work on projects that have a measurable impact on our business, focusing on digital circuit design and related areas.

Responsibilities:

  • Work on digital circuit design and device fundamentals
  • Utilize place and route design tools, datapath tiling techniques, and SPICE simulations
  • Design and analyze CMOS logic, transistor-level circuits, timing and delay analysis, and standard cell design
  • Experience with automation methods, algorithm and power distribution, and power management circuits
  • Familiarity with EDA tools, such as Cadence and Synopsys

Requirements:

  • Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
  • Anticipated graduation date must be clearly indicated on a resume or CV
  • Course or internship experience related to digital circuit design, device fundamentals, and related areas

Benefits:

  • Competitive hourly rate ($20-$71 USD)
  • Eligibility for Intern benefits

Programming skills and technologies:

  • Verilog, SystemVerilog, VHDL, Perl, Python, SPICE/HSPICE, Monte Carlo, CMOS, FinFET, EDA Tools (Synopsys, Cadence, etc.)

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]]> internship $20-$71/hour Digital Circuit Design, Electrical Engineering, Computer Engineering, EDA Tools, Verilog, SystemVerilog, VHDL, Python, SPICE/HSPICE, CMOS, FinFET, Monte Carlo, Perl Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing to tackle challenges in various industries, including gaming, robotics, and healthcare. https://nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Digital-Circuit-Design_JR2023504?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 9b99cf5f-ab9 NVIDIA 2027 Internships: Hardware Engineering NVIDIA offers a 12-week full-time internship program for students pursuing a B.S., M.S., or Ph.D. degree in a relevant field. As an intern, you will work on projects with a measurable impact on the business and collaborate with industry-leading Hardware teams.

Potential internships include:

  • System Validation: Test and debug new features and changes made during product development for datacenter server products.
  • Hardware Design: Work on hardware testing, debugging, and validation of new products to ensure performance, functional, and quality objectives.
  • Mechanical Engineering: Research and develop new concepts and materials for next-generation products.
  • Silicon Solutions: Productize NVIDIA's chips into consumer, professional, server, mobile, and automotive solutions.

Requirements:

  • Actively enrolled in a university pursuing a B.S., M.S., or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
  • Anticipated graduation date must be clearly indicated on a resume or CV.
  • Prior experience or knowledge requirements may include programming skills and technologies such as Verilog, SystemVerilog, VHDL, Perl, Python, TCL, Board-Level Design, PCB, Datacenter Systems, Linux, CAD Software, MATLAB, MOSFETs, Lab Tools.

Benefits:

  • Hourly rate: $20 - $71 per hour
  • Eligibility for Intern benefits

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]]> internship $20 - $71 per hour Electrical Engineering, Computer Engineering, Verilog, SystemVerilog, VHDL, Perl, Python, TCL, Board-Level Design, PCB, Datacenter Systems, Linux, CAD Software, MATLAB, MOSFETs, Lab Tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneers accelerated computing to tackle challenges in various industries. https://www.nvidia.com USD 20 71 hourly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2027-Internships--Hardware-Engineering_JR2023508-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-19 4cfffc6c-f1d SRAM Design Engineer, Sr Staff You are an experienced engineer passionate about advancing memory design technologies. You will be designing and verifying SRAM integrated circuits to ensure robustness and reliability. Your responsibilities will include:

  • Designing and verifying SRAM integrated circuits to ensure robustness and reliability
  • Developing SRAM compilers, including gds and netlist tiling for optimal performance and scalability
  • Characterizing SRAM timing, power, and other critical metrics to meet customer and product requirements
  • Executing compiler quality assurance processes to uphold industry-leading standards
  • Conducting SRAM bitcell analysis and formulating design criteria for advanced memory products
  • Utilizing EDA tools (XA, hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization
  • Collaborating with cross-functional teams to address post-silicon debug and implement improvements
  • Exploring and integrating SP/2P/ROM variety designs into SRAM IP solutions

The Impact You Will Have:

  • Drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology
  • Enhance product performance and reliability for global semiconductor customers
  • Support the delivery of best-in-class SRAM compilers used in high-performance silicon chips
  • Strengthen quality assurance processes, ensuring robust and scalable designs
  • Accelerate time-to-market for new memory IP solutions through efficient verification and debug activities
  • Contribute to the development of advanced memory architectures, impacting next-generation electronic devices

You will need:

  • Master’s degree in Electrical/Electronic Engineering or a related field
  • 12+ years of hands-on experience in SRAM circuit design
  • Prior understanding of CMOS-based block level circuit design and SRAM architectures
  • Experience with SP/2P/ROM variety design and SRAM bitcell analysis
  • Proficiency in digital circuit design and VLSI process concepts
  • Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell
  • Experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR
  • Post-silicon debug experience is a plus

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs including ETO and FTO
  • Family support including maternity and paternity leave
  • ESPP: purchase Synopsys common stock at a 15% discount
  • Retirement plans varying by region and country
  • Competitive salaries

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]]> full-time senior onsite SRAM circuit design, CMOS-based block level circuit design, VLSI process concepts, Python, Tcl/Tk, Perl, Unix shell, XA, hspice, Verilog, Starrc, EMIR, post-silicon debug experience Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys develops and maintains software used in chip design, verification, and manufacturing for the semiconductor industry. https://careers.synopsys.com https://careers.synopsys.com/job/hsinchu/sram-design-engineer-sr-staff/44408/99385622800?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hsinchu, Taiwan Hsinchu Taiwan TW 2026-08-19 a81f13c0-d32 SRAM Design Engineer, Staff You are an experienced engineer passionate about advancing memory design technologies.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Responsibilities

  • Designing and verifying SRAM integrated circuits to ensure robustness and reliability.
  • Developing SRAM compilers, including gds and netlist tiling for optimal performance and scalability.
  • Characterizing SRAM timing, power, and other critical metrics to meet customer and product requirements.
  • Executing compiler quality assurance processes to uphold industry-leading standards.
  • Conducting SRAM bitcell analysis and formulating design criteria for advanced memory products.
  • Utilizing EDA tools (XA, hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
  • Collaborating with cross-functional teams to address post-silicon debug and implement improvements.
  • Exploring and integrating SP/2P/ROM variety designs into SRAM IP solutions.

The Impact You Will Have

  • Drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology.
  • Enhance product performance and reliability for global semiconductor customers.
  • Support the delivery of best-in-class SRAM compilers used in high-performance silicon chips.
  • Strengthen quality assurance processes, ensuring robust and scalable designs.
  • Accelerate time-to-market for new memory IP solutions through efficient verification and debug activities.
  • Contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

Requirements

  • Master’s degree in Electrical/Electronic Engineering or a related field.
  • 3–7+ years of hands-on experience in SRAM circuit design.
  • Prior understanding of CMOS-based block level circuit design and SRAM architectures.
  • Experience with SP/2P/ROM variety design and SRAM bitcell analysis.
  • Proficiency in digital circuit design and VLSI process concepts.
  • Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell.
  • Experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR.
  • Post-silicon debug experience is a plus.

Who You Are

  • Analytical thinker with strong problem-solving skills.
  • Curious and eager to learn new technologies and concepts.
  • Detail-oriented and committed to delivering high-quality results.
  • Collaborative team player with effective communication skills.
  • Adaptable and able to manage multiple tasks in a fast-paced environment.
  • Self-motivated and resourceful in overcoming technical challenges.

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.

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]]> employee staff SRAM circuit design, CMOS-based block level circuit design, SRAM architectures, SP/2P/ROM variety design, SRAM bitcell analysis, digital circuit design, VLSI process concepts, Python, Tcl/Tk, Perl, Unix shell, XA, hspice, Verilog, Starrc, EMIR, post-silicon debug experience Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys develops and maintains software used in chip design, verification, and manufacturing for the semiconductor industry. https://careers.synopsys.com https://careers.synopsys.com/job/hsinchu/sram-design-engineer-staff/44408/99336131584?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hsinchu, Taiwan Hsinchu Taiwan TW 2026-08-18 f6e96a2c-20f SOC Verification Engineer NVIDIA is seeking an expert Verification Engineer to work on its SOC verification team. The successful candidate will work on NVIDIA's next-generation SOC, verifying CPU, GPU, high-speed interfaces, Design for Debug (DFD), and horizontal functions like Boot and Power management at subsystem or full-chip testbenches, including FPGA/Silicon.

The ideal candidate will have experience with full-stack development, from verifying scenarios at SW simulator level to getting the overall end-to-end test working on silicon with a full SW stack. They will also have strong verification fundamentals, experience with Verilog, SystemVerilog, C/C++, and possess strong debugging skills.

Key responsibilities:

  • Work on NVIDIA's next-generation SOC
  • Verify CPU, GPU, high-speed interfaces, DFD, and horizontal functions
  • Develop and implement test plans collaborating with SOC architects
  • Work on developing verification testbenches, flows, and automation

Requirements:

  • Experience with full-stack development
  • Strong verification fundamentals
  • Experience with Verilog, SystemVerilog, C/C++
  • Bachelors/Masters, or equivalent experience, in Computer Science or Electrical Engineering with 3+ years of industry experience

Benefits:

  • Competitive salaries
  • Generous benefits package

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]]> full-time senior Verilog, SystemVerilog, C/C++, debugging, verification, complex verification projects, SOC integration, verification methodologies, collaborating with multi-functional teams Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that has reinvented itself over two decades, inventing the GPU in 1999 and driving innovation in visual processing, high-performance computing, and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/SOC-Verification-Engineer_JR2023239?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-08-14 cf21b3da-cf4 ASIC Engineer NVIDIA's Global Flows Team advances RTL quality and sign-off methodologies used across NVIDIA CPU programs. As an ASIC Engineer, you will develop and deploy innovative RTL design-quality methodologies, including CDC, RDC, Netlist/Design Auditors, Power Insertion, lint, and related structural checks.

Your role will involve:

  • Analyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.
  • Establishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.
  • Collaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
  • Assessing new tool releases and methodology capabilities, coordinating their integration into project environments.
  • Improving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.

We are seeking a professional with:

  • A Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • 3+ years of proven experience in ASIC or SoC RTL design or design-methodology.
  • Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
  • Knowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
  • Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
  • The ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
  • Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

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]]> full-time senior Verilog, SystemVerilog, RTL design, design-methodology, digital design, microarchitecture, lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, timing constraints, Linux, Python, Tcl, Perl, shell, RTL integration, design bring-up, multi-team debugging, Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, Power insertion, UPF, low-power RTL implementation, verification, SDC, static timing analysis, formal verification, equivalence checking Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA builds accelerated computing platforms that are redefining AI, data centers, autonomous systems, and scientific computing. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Engineer_JR2023232?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-08-14 5e8a5a8c-084 Manager, DFT - Post Silicon We are seeking a Chip Design DFT/Post Silicon Manager to develop next-generation DFT technologies. As a Manager in the DFT team at NVIDIA, you will lead a team that transfers DFT technologies to post-silicon in various projects and supports enablement. This role involves working on advanced technologies and complex products, including Switches, Nic, and SoC product lines.

Key Responsibilities:

  • Define and develop characterization and validation techniques for post-silicon bring-up and production testing.
  • Lead methodology planning for future products and serve as the synchronization point between teams.
  • Drive alignment on tooling, flows, and coverage requirements ahead of tape-out and first silicon.
  • Translate product requirements and silicon behavior into structured characterization plans.
  • Lead methodology transfer into execution, ensuring tooling, methods, and engineers are in place for a smooth handoff.
  • Identify methodology gaps early in the program cycle and resolve them through cross-functional collaboration.

Requirements:

  • B.Sc. in Electrical Engineering (or equivalent experience).
  • 8+ years of experience with DFT, IC silicon validation, product engineering, or test engineering.
  • 2+ years of managerial experience.
  • Ability to work in a fast-paced, multifaceted environment with technical excellence and innovative thinking.
  • Strong cross-functional communication skills.
  • Hands-on engineering background with the ability to be technically authoritative.

Preferred Qualifications:

  • Experience in developing verification environments and random-based verification using tools like simulation tools, Verilog, and debug tools.
  • Experience with Specman/UVM.
  • Understanding of RTL design (Verilog).
  • Product engineering experience.

What We Offer:

  • Opportunity to work on cutting-edge technologies.
  • Collaborative and dynamic work environment.
  • Chance to make a significant contribution to NVIDIA's products and achievements.

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]]> full-time senior DFT, IC silicon validation, product engineering, test engineering, Electrical Engineering, Verilog, RTL design, Specman/UVM, verification environments, random-based verification, simulation tools, debug tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and now powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/Manager--DFT---Post-Silicon_JR2023089-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Tel Aviv Tel Aviv 2026-08-13 5ad96105-be6 Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU NVIDIA is seeking a Senior ASIC Compose Verification Infrastructure and Tools Engineer to advance the systems that qualify, integrate, and deliver complex ASIC IP across multiple products.

This role involves working on high-speed IO infrastructure, developing flows for integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows.

Key responsibilities include:

  • Applying practical AI workflows to build leverage in areas such as debug assistance, run triage, summarization, documentation, and workflow automation.
  • Building and improving high-speed IO integration, build, simulation, and pre-submit qualification flows for large ASIC IP development.
  • Improving CI reliability, turnaround time, debuggability, and scalability across distributed compute environments.
  • Root-causing complex failures across development, verification, build systems, tools, infrastructure, and compute environments.
  • Turning recurring integration or qualification difficulties into durable automation and process improvements.
  • Defining, publishing, and actively using metrics for integration latency, flow health, failure trends, and engineering efficiency.
  • Collaborating with ASIC designers, verification engineers, firmware engineers, methodology teams, and infrastructure partners.

Requirements:

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 5+ years of relevant industry experience.
  • Strong understanding of ASIC development workflows, including builds, simulation, regressions, debug, integration, and qualification.
  • Experience with verification methodology such as UVM or similar.
  • Strong working knowledge of Verilog/SystemVerilog, including RTL development or pre-silicon verification/debug experience.
  • Exposure to industry simulation and debug tools such as VCS, Verdi, Xcelium, or similar.
  • Strong programming skills in Python, Perl, or another scripting/systems programming language.
  • Experience with SystemVerilog and object-oriented verification environments.
  • Strong root-cause analysis skills, especially for intermittent or hard-to-isolate infrastructure failures.

NVIDIA offers equity and benefits to its employees.

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]]> full-time senior ASIC development, Verification methodology, SystemVerilog, Verilog, Python, Perl, UVM, VCS, Verdi, Xcelium, AI workflows, Debug automation, Summarization, Tool-assisted development Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company is advancing AI to define the next era of computing. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Verification-Infrastructure-and-Tools-Engineer---GPU_JR2022848?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-08-13 88e33822-b6e Senior ASIC Physical Design Engineer, Cache Coherent Interconnects As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
  • Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.

Requirements:

  • Master's Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
  • 5+ years of experience in processor or other related high-performance semiconductor designs.
  • Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
  • Experience in interconnect/cache/core design is desirable.
  • Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
  • Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

You will also be eligible for equity and benefits.

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]]> full-time senior Electrical Engineering, Computer Engineering, Computer Science, Physical design, Synthesis, Timing analysis, Floor-planning, Verilog, Interconnect/cache/core design, ASIC design flow, RTL design and verification, DFT, ECO Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that impacts product lines ranging from consumer graphics to self-driving cars and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Physical-Design-Engineer--Cache-Coherent-Interconnects_JR2023121?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-11 528a240c-a90 Senior Chip Architect We are seeking a Senior Chip Architect to join our elite team of ~15 employees in the NIC and DPU division. As a hardware architect, you will define the architecture of NVIDIA's next-generation NIC and DPU products, working closely with cross-functional teams to improve performance and debug.

Responsibilities:

  • Learn and understand the NIC microarchitecture thoroughly across all aspects
  • Define the next-generation NVIDIA systems with GPU and CPU teams
  • Balance architecture requirements with backend, execution, and design considerations for sophisticated features
  • Understand system requirements and help define the POR of our NIC and DPU product line
  • Address Full-Chip correctness and performance issues requiring cross-unit understanding
  • Collaborate with board and package design on design limitations
  • Understand SoC flows, PCIe, Ethernet, InfiniBand, and NvLink protocols

Requirements:

  • B.Sc./M.Sc in Electrical Engineering from a reputable university
  • Excellent grades
  • 5+ years of experience in ASIC design/uarch/arch/performance
  • 4+ years of hands-on experience with Verilog/VHDL
  • Strong analytic capabilities, problem-solving skills, and communication skills

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]]> full-time senior ASIC design, Verilog, VHDL, Electrical Engineering, SoC flows, PCIe, Ethernet, InfiniBand, NvLink Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a world-leader in accelerated computing, powering global intelligence and transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-Chip-Architect_JR2023093?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Yokneam, Israel Yokneam Israel IL 2026-08-11 84b17b87-916 LPDDR IP Design Principle Engineer We are seeking a Sr. Staff ASIC Digital Design Engineer to join our LPDDR PHY IP team at Synopsys. As a leader in the mixed-signal IP market, Synopsys develops cutting-edge semiconductor solutions.

In this role, you will contribute to all phases of LPDDR PHY IP design, from specification to productization, and provide customer support.

Responsibilities:

  • Design and micro-architect LPDDR PHY IP, writing Verilog and SystemVerilog code and design specifications
  • Conduct simulation and analysis of designs, working with Verification, Timing, DFT, and Power teams
  • Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues
  • Maintain and improve design automation flow and process

Requirements:

  • BS in Electrical Engineering with 10+ years of experience in complex technical development
  • Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
  • Front-end design flow experience, including linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
  • Excellent communication skills and self-motivation
  • Understanding of memory and memory PHY architecture is a plus

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs, including ETO and FTO
  • Family support, including maternity and paternity leave, parenting resources, and adoption assistance
  • ESPP program with 15% discount on Synopsys stock
  • Retirement plans varying by region and country
  • Competitive salaries

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]]> full-time senior onsite Verilog, SystemVerilog, ASIC design, DFT, Timing analysis, Power optimization, memory PHY architecture Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys supplies essential tools and intellectual properties to enable semiconductor design, verification, and production. https://careers.synopsys.com https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-principle-engineer/44408/94561854112?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, Karnataka Bengaluru Karnataka IN 2026-08-08 e58a711e-e1e Senior IP Design Verification Engineer - XBAR IP NVIDIA is seeking a Senior Verification Engineer to verify the design and implementation of next-generation memory subsystem units for leading GPUs and SOCs. This role offers the opportunity to make a real impact in a dynamic, technology-focused company.

The GPU initially simulated human imagination for video games and films, but now NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars.

Responsibilities:

  • Verify the ASIC design, architecture, and micro-architecture of memory sub-systems/units using advanced verification methodologies.
  • Understand the design and implementation, define the verification scope, develop the verification infrastructure, and verify the correctness of the design.
  • Create test plans, tests, and verification infrastructure for complex IPs/sub-systems.
  • Build reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification methodology.
  • Work on advanced verification methodologies like SV/UVM.
  • Perform functional coverage-driven verification closure.
  • Collaborate with architects, designers, and pre- and post-silicon verification teams.

Requirements:

  • B.Tech./M.Tech., or equivalent experience.
  • 4+ years of relevant experience.
  • Experience in verification of complex IPs/units and sub-systems.
  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
  • Expertise in Verilog.
  • Knowledge in SystemVerilog or similar HVL/UVM or VMM.

Preferred Qualifications:

  • Experience in memory subsystem or network interconnect IP verification.
  • Debugging and analytical skills with sound scripting knowledge.
  • Good communication and excellent team player.

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]]> full-time senior ASIC design, Verification methodologies, SystemVerilog, UVM, VMM, Verilog, Functional coverage, Assertion-based verification, Memory subsystem verification, Network interconnect IP verification, Scripting knowledge, Debugging skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a computing company that produces GPUs and SOCs for various applications including consumer graphics, self-driving cars, and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2022804?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-08-07 7468a2f0-6ab Senior Design Verification Engineer - Interconnect IP As a Senior Design Verification Engineer at NVIDIA, you will be responsible for verifying the ASIC design, architecture, and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies.

Your key responsibilities will include:

  • Defining the verification scope and developing the verification infrastructure
  • Creating test plans, tests, and verification infrastructure for complex IPs/sub-systems
  • Performing performance and deadlock verification of the GPU memory subsystem unit
  • Building reusable bus functional models, monitors, checkers, and scoreboards
  • Conducting functional coverage-driven verification closure
  • Collaborating with architects, designers, and pre- and post-silicon verification teams

To be successful in this role, you will need:

  • A Master's degree or equivalent experience in Electrical/Computer Engineering or a related field
  • 5+ years of ASIC design verification experience on complex IPs, units, or sub-systems
  • Deep understanding of verification methodologies and languages, including Verilog, SystemVerilog, and UVM
  • Hands-on experience across the full verification flow
  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
  • Exposure to industry-standard verification tools for simulation and debug

Experience in memory subsystem or network interconnect IP verification, as well as familiarity with AI techniques to improve verification workflows, would be a plus.

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]]> full-time senior ASIC design verification, Verilog, SystemVerilog, UVM, verification methodologies, GPU memory subsystem unit, memory subsystem verification, network interconnect IP verification, AI techniques for verification workflows Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/Senior-Design-Verification-Engineer---Interconnect-IP_JR2022679?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai 2026-08-07 dbd97e59-7ec ASIC Digital Design, Manager Synopsys is seeking a Senior Staff ASIC Digital Design Engineer to join their LPDDR PHY IP team. The successful candidate will contribute to all phases of DDR PHY IP design, from specification to productization, and provide customer support.

Responsibilities:

  • Design and micro-architect LPDDR PHY IP, writing Verilog and SystemVerilog code and design specifications
  • Conduct simulation and analysis of designs, working with Verification, Timing, DFT, and Power teams
  • Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues
  • Maintain and improve design automation flow and processes

Requirements:

  • BS in Electrical Engineering
  • Minimum 8 years of experience in complex technical development
  • Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
  • Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
  • Excellent communication skills and self-motivation
  • Understanding of memory and memory PHY architecture is a plus

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs, including ETO and FTO
  • Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP, allowing purchase of Synopsys common stock at a 15% discount
  • Retirement plans, varying by region and country
  • Competitive salaries

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]]> employee senior Electrical Engineering, Verilog, SystemVerilog, front-end design flows, linting, synthesis, timing investigation, DFT, power optimization, memory PHY architecture Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys supplies essential tools and intellectual properties for semiconductor design, verification, and production. https://careers.synopsys.com https://careers.synopsys.com/job/noida/asic-digital-design-manager/44408/96858253712?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Noida, Uttar Pradesh Noida Uttar Pradesh IN 2026-08-05 a669e6e0-a06 LPDDR IP Design Engineer We are looking for a Staff ASIC Digital Verification Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution.

Responsibilities:

  • Defining and tracking Verification test plans
  • Designing and writing constrained-random SystemVerilog testbenches using UVM
  • Writing SystemVerilog assertions
  • Writing functional coverage
  • Debugging RTL and GLS failures
  • Code coverage Analysis
  • Providing mentoring and guidance to less experienced team members

Required Skills:

  • BSEE in EE with 5+ years of industry experience
  • Digital verification in UVM environment, Formal Verification is a plus
  • Understanding of memory and memory PHY architecture
  • Knowledge of DFI, Memory Controller or Memory Subsystem
  • Verilog, System Verilog and Perl/Python scripting skills
  • Debugging skills
  • Demonstrates good communication and problem-solving skills
  • Understanding of high-speed interface protocols is a plus

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs
  • Family support
  • ESPP
  • Retirement plans
  • Competitive salaries

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]]> full-time senior onsite Digital verification, UVM, SystemVerilog, Verilog, Perl, Python, Memory architecture, DFI, Memory Controller, Memory Subsystem, Formal Verification, High-speed interface protocols Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys supplies essential tools and intellectual properties to enable semiconductor design, verification, and production. https://careers.synopsys.com https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-engineer/44408/93763201616?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, Karnataka Bengaluru Karnataka IN 2026-08-05 b7cb6134-b37 Senior Front-End Power Engineer We are seeking a Power Optimization and Analysis Engineer to join our u/arch team in the Switch group at NVIDIA. As a Senior Front-End Power Engineer, you will analyze full chip and unit-level power data, drive FE/BE ASIC teams to improve power efficiency, and develop methodologies to make NVIDIA's products more energy efficient.

Key responsibilities include:

  • Analyzing power data and driving ASIC teams to improve power efficiency
  • Researching, developing, and deploying power analysis and reduction techniques
  • Collaborating with architects, performance engineers, software engineers, and physical design teams
  • Developing techniques to model, analyze, and reduce power consumption of NVIDIA Switches product line

Requirements:

  • BSC or MS in Computer Engineering or Electrical Engineering
  • 5+ years of experience in chip design
  • Good interpersonal skills and ability to collaborate with design teams
  • Familiarity with Verilog and ASIC design or verification
  • Strong coding/automation skills in Python, Perl, and C++

Nice to have:

  • Experience with Power Artist, PTPX (Prime Power RTL, RTL Architect)
  • Strong understanding of energy consumption, estimation, data movement, and low power design

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]]> full-time senior Verilog, ASIC design, Python, Perl, C++, Power analysis, Power Artist, PTPX, low power design Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and today powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/Power-U-Architect_JR1998014?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Tel Aviv Tel Aviv 2026-08-05 605d06f7-003 ASIC TOP Floorplan Design Engineer We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's.

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you will be doing:

  • Working with architects, design leads, physical design leads and package leads, you will develop, craft and optimize floorplans during early chip development.
  • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
  • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  • You will build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

What we need to see:

  • Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.
  • Experience in Verilog, System Verilog or similar HVL.
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
  • Python, Perl and C/C++ programming language experience.
  • Experience using AI coding assistants like Cursor or Github copilot or Windchill

Ways to stand out from the crowd:

  • Experience in driving development of large-scale ASIC floorplan is a huge plus.
  • Experience building large projects from the ground up using AI tools.
  • Good command of spoken English

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]]> full-time senior Verilog, System Verilog, CAD, physical design methodologies, Python, Perl, C/C++, AI coding assistants, large-scale ASIC floorplan, AI tools, spoken English Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and its AI infrastructure powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-TOP-Floorplan-Design-Engineer_JR2022676?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai CN 2026-08-04 b0cda847-2f6 Senior Architect, NVLink NVIDIA is seeking a Senior Architect (NVLink) to join a team responsible for defining next-generation communications standards and products building on their current NVLink technology.

The successful candidate will:

  • Research and craft architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
  • Collaborate with other design teams to define interfaces and flows between NVLink blocks and the rest of the chip
  • Perform architectural modeling, validation, definition, and documentation
  • Drive implementation across design, verification, firmware, and software teams
  • Work with switch teams to define NVLink fabric architecture
  • Define network configuration and management flows

Requirements include:

  • Master's or Ph.D. in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience)
  • At least 8 years of relevant experience in architecture, design, and verification
  • Experience with innovative ASIC design processes
  • Proven track record of shipping multiple projects with skills in processor and I/O architecture
  • Proficiency in C++ and Verilog

NVIDIA offers equity and benefits to its employees.

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]]> full-time senior Electrical Engineering, Computer Science, Computer Engineering, ASIC design, C++, Verilog, processor architecture, I/O architecture Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-MA-Westford/Senior-Architect--NVLink_JR2022626?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Westford, MA Westford MA US 2026-08-03 1895fcf6-ae7 Senior Memory System Architect NVIDIA is seeking a Senior Memory System Architect to join their memory system architecture team.

The successful candidate will drive the development of architecture and micro-architecture to improve the state-of-the-art in memory systems, optimizing performance, power efficiency, complexity, area, effort, and schedule.

Key responsibilities include:

  • Developing architecture and micro-architecture for memory systems
  • Performance modeling and simulation of features to improve memory system performance and efficiency
  • Implementing and maintaining detailed and high-level performance models
  • Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations
  • Debugging performance and functional issues with high-level models, RTL simulation, and silicon

Requirements:

  • M.S. or Ph.D. in CS, CE, or EE or equivalent experience
  • 3+ years experience in SoC or memory system architecture and performance
  • Deep understanding of memory subsystems – caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation
  • Strong communication and interpersonal skills along with the ability to work in a dynamic, product-oriented, distributed team
  • Exposure/coursework related to Digital systems and VLSI design, Computer Architecture, C/C++ programming languages
  • Software development experience with C++, Python, and/or Perl; Verilog or SV/UVM are a plus

Preferred qualifications:

  • Significant experience with performance modeling or performance verification
  • Experience debugging and solving complex performance issues

The position offers equity and benefits.

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]]> full-time senior SoC architecture, memory system architecture, performance modeling, C++, Python, Perl, Verilog, SV/UVM, Digital systems, VLSI design, Computer Architecture, performance verification, debugging complex performance issues Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA develops computing hardware and software for deep learning, autonomous vehicles, and other applications. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Memory-System-Architect_JR2022582?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-08-03 7a6f34a9-f3f Senior ASIC Design Engineer – Clocks IP The Clocks team at NVIDIA is seeking a senior ASIC Design Engineer to join their team, focusing on crafting all aspects of GPU and CPU clocking. As a Clocks team member, you will architect the clock domain to satisfy functional, physical, and testing design requirements.

You will engage with multiple teams to design GPU or CPU clocks that meet architectural, design, and physical constraints, while improving Power, Performance, and Area (PPA) of innovative NVIDIA chips.

Key responsibilities include:

  • Designing GPU or CPU clocks with multiple teams to satisfy architectural, design, and physical constraints
  • Improving PPA of NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization, and Ease of timing closure
  • Collaborating with Physical design and timing teams to evaluate Clocking concerns and develop solutions
  • Delivering clock RTL information to GPU, CPU, and SOC verification teams, timing and DFT teams
  • Participating in the end-to-end cycle of ASIC execution from micro-arch to Silicon bringup

Requirements:

  • BS in Electrical Engineering or equivalent experience (MS preferred)
  • 3+ years of relevant work experience
  • Deep understanding of logic optimization techniques and PPA trade-offs
  • Excellent interpersonal skills and ability to collaborate with multiple teams
  • Experience in RTL design (Verilog), verification, and logic synthesis
  • Strong coding skills in Python or other industry-standard scripting languages
  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus

Preferred qualifications:

  • Experience with clocks controller, clocks logic design
  • Understanding of system-level artifacts like power, noise, etc.
  • Experience with scalable designs and architecture
  • Hands-on silicon debug experience

NVIDIA offers competitive salaries and a generous benefits package.

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]]> full-time senior ASIC design, RTL design, Verilog, logic synthesis, Python, DFx, Physical Implementation, Power Optimization, clocks controller, clocks logic design, scalable designs, silicon debug Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA invented the GPU in 1999 and has since evolved into a leader in parallel computing, redefining modern computer graphics and igniting modern AI. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2022532?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-08-03 0c06d513-90c Senior SOC Clocks RTL Design Engineer The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role, you will lead the development of the chip's clocking logic , PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

Responsibilities:

  • Acting as the technical lead for SOC clocks development , leading the implementation of the clocking logic from specification through tape-out and bring-up
  • Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design
  • Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization
  • Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team
  • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence
  • Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure
  • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
  • Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders

Requirements:

  • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
  • 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out
  • Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams
  • Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power
  • Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing
  • Proficiency with design quality tooling , lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) , including the ability to interpret results and drive fixes back into the RTL
  • Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up
  • Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams

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]]> full-time senior RTL design, Verilog, SystemVerilog, clocking and reset design, design quality tooling, SOC-level clocking or reset logic, PLL/clock generator integration, high-speed networking, low-power design techniques Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/Senior-SOC-Clocks-RTL-Design-Engineer_JR2022323?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Tel Aviv Tel Aviv IL 2026-08-01 165db122-7df SOC Clocks RTL Design Engineer The NVIDIA System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips.

In this role, you will own the clock generation, distribution, and control logic for the entire chip , PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

Responsibilities:

  • Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out
  • Defining and implementing the SOC clock and reset architecture together with the micro-architecture team , collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design
  • Owning clock domain crossing infrastructure and CDC closure across the SOC
  • Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power
  • Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness
  • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
  • Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks
  • Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable
  • Supporting emulation, firmware, and post-silicon bring-up customers of your design

Requirements:

  • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
  • 3+ years of relevant experience in RTL/logic design
  • Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation
  • Experience taking a design from micro-architecture specification through verification and physical implementation
  • Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing
  • Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis)
  • Great teammate with strong communication skills across micro-architecture, DV, and backend teams

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]]> full-time senior RTL design, Verilog, SystemVerilog, clocking and reset concepts, design quality tooling, PLL/clock generator integration, clock tree constraint development Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/SOC-Clocks-RTL-Design-Engineer_JR2022321?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Tel Aviv, Israel Tel Aviv Israel IL 2026-08-01 b962642d-a37 Senior Mixed Signal Design Engineer NVIDIA is seeking a Senior Mixed Signal Design Engineer to join their Mixed Signal team. The successful candidate will be responsible for the architecture definition and design of CMOS high-speed interface circuits and mixed-signal circuits. They will also be involved in silicon validation, debugging, characterization, and bring-up.

Key Responsibilities:

  • Design and implement high-speed interface circuits
  • Create projects including high-speed transceivers and high-frequency PLLs
  • Involved in the design, simulation, and verification of mixed-signal circuits
  • Lead mask designers and provide mentorship for floorplan and layout design
  • Support lab characterization of silicon and tackle circuit design challenges in deep submicron CMOS
  • Take designs through implementation and productizing, collaborating with multi-functional teams

Requirements:

  • BS or MS in Electrical Engineering, PhD preferred (or equivalent experience)
  • 5+ years of design experience in CMOS analog/mixed-signal circuits
  • Working knowledge of Cadence custom design tools, circuit simulator, and timing analysis tool
  • Exceptional teamwork and interpersonal skills, with experience in leading and mentoring designers
  • Extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high-speed IO interfaces
  • In-depth understanding of deep submicron CMOS process and related circuit design issues
  • Proven experience in silicon bring-up, debugging, and use of lab instrumentation
  • Knowledge of system-level timing budget, signal integrity, and power integrity is a plus
  • Experience in Verilog, Matlab, Nanotime is helpful

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]]> full-time senior CMOS analog/mixed-signal circuit design, Cadence custom design tools, Circuit simulator, Timing analysis tool, Data Converters, Tx/Rx design, CDR/PLL design, High-speed IO interfaces, Deep submicron CMOS process, Silicon bring-up, Debugging, Lab instrumentation, Verilog, Matlab, Nanotime Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that pioneered accelerated computing and AI infrastructure, powering global intelligence and transforming industries. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Mixed-Signal-Design-Engineer_JR2021877-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-07-30 52cc52e1-e78 Senior Software Engineer, SOC Design Methodology NVIDIA is seeking a Senior Software Engineer for its SOC Design Methodology team. The team develops software that powers how NVIDIA's ASIC engineers design chips, building tools, automating flows, and co-developing with EDA vendors.

The ideal candidate will develop software to automate SoC design and build flows, enabling ASIC engineers to work faster and more reliably. They will build new methodologies and tools in pursuit of ASIC design at Speed of Light (SOL), partner with design and verification engineers, and co-develop EDA tool capabilities with vendors.

Requirements:

  • BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience)
  • 3+ years of EDA tool development experience in the ASIC or SoC design field
  • Hands-on experience with ASIC or SoC design and verification
  • Proficiency in Verilog or SystemVerilog
  • Strong programming skills in C++, Python, Perl, or Tcl
  • Solid understanding of computer algorithms and data structures

Preferred qualifications:

  • Experience with SoC integration , IP connectivity, clock/reset automation, or top-level design flow
  • Familiarity with Synopsys Fusion Compiler or similar next-generation design tools
  • Hands-on use of agentic AI coding tools (Claude Code, Cursor, Copilot) in day-to-day development

NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity.

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]]> full-time senior Electrical Engineering, Computer Engineering, Computer Science, EDA tool development, ASIC design, SoC design, Verilog, SystemVerilog, C++, Python, Perl, Tcl, computer algorithms, data structures, SoC integration, IP connectivity, clock/reset automation, top-level design flow, Synopsys Fusion Compiler, agentic AI coding tools Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company has a 25-year legacy of innovation. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Software-Engineer--SOC-Design-Methodology_JR2022268?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-28 5cad091b-c2d Senior ASIC Design Engineer - GPU We are seeking a Senior ASIC Engineer to develop and implement a memory management unit (MMU) for top SoCs and GPUs. As part of the MMU team, you will work on a state-of-the-art memory management system with complex build requirements, contributing to the company's products used in consumer graphics, autonomous vehicles, and supercomputers.

Key Responsibilities:

  • Develop and design a high-performance MMU for a GPU using advanced verification methodologies.
  • Contribute to architecture decisions and mentor other engineers on the team.
  • Collaborate with architects, designers, and software engineers across different sites.

Requirements:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience.
  • At least 5 years of relevant work or research experience.
  • Experience in crafting memory subsystem units with properties such as memory coherency and arbitration policies.
  • Proficiency in Verilog, VCS or equivalent simulation tools, debug tools like Verdi, Synopsys, and Object-Oriented Programming with C++ and/or SystemVerilog.
  • Strong communication skills are required.

What We Offer:

  • Equity and benefits package.
  • Opportunity to work on cutting-edge technology driving the company's success in AI, deep learning, and graphics.

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]]> full-time senior hybrid Verilog, VCS, SystemVerilog, C++, memory coherency, arbitration policies, Object-Oriented Programming Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA drives innovation in modern computing, particularly in artificial intelligence and deep learning, and is a leader in designing GPUs and SoCs for various applications. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-NC-Durham/Senior-ASIC-Design-Engineer---GPU_JR2011295?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Durham, NC Durham NC US 2026-07-23 5ab4ccf5-9ab Senior Verification Engineer NVIDIA is seeking a skilled Senior Verification Engineer to join the Display Team. You will verify the world's foremost GPU and SoC display engines, working with Architects and ASIC Engineers to deliver high-quality IPs for consumer, professional, automotive, and AI markets.

Responsibilities:

  • Define verification scope, develop and drive testplans, and build scalable UVM-based infrastructure.
  • Develop UVM testbenches and checkers; work with C/C++-based testbenches and debug reference models and designs.
  • Partner with architects to develop well-crafted, silicon-proven designs.
  • Collaborate across NVIDIA sites globally and work closely with external partners and customers.

Requirements:

  • BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 10+ years of relevant experience.
  • Strong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++.
  • Experience with industry EDA tools and strong software engineering practices.
  • Domain knowledge of display pipelines, protocols, and system low-power features.

Benefits:

  • Equity and benefits eligibility

Location: US, CA, Santa Clara

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]]> full-time senior UVM, SystemVerilog, Verilog, Python, C/C++, EDA tools, display pipelines, protocols, Display Unit Verification, pixel processing, ISO performance testing, HLS-based designs Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Verification-Engineer_JR2021700-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-23 170eaa00-99f ASIC Design Engineer - New College Grad 2026 We are seeking a Logic Design Engineer to join our CPU Logic Design Team.

As a member of our team, you will be responsible for CPU on-chip interconnect network, coherency and last-level caches, focusing on tasks such as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation.

Responsibilities:

  • Own and be responsible for crafting and timely delivery of a specific unit on the chip.
  • Write readable high-performance and low-power RTL, perform synthesis and timing closure, and create design documentation.
  • Collaborate with the verification team to verify the correctness of your unit.
  • Work with implementation to achieve timing, area, performance, and power goals.
  • Assist with timing closure of super units.

Requirements:

  • Recent graduate with a BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
  • Experience in processor or other related high-performance semiconductor designs.
  • Verilog expertise required, as well as a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
  • Effective communication and interpersonal skills are required, along with experience working in a dynamic, global team.
  • A strong background in computer architecture, cache coherency, or high-speed interconnects is preferred.

You will also be eligible for equity and benefits.

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]]> full-time entry Verilog, ASIC design flow, RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, lab debug, computer architecture, cache coherency, high-speed interconnects Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that impacts product lines ranging from consumer graphics to self-driving cars and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---New-College-Grad-2026_JR2021534?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-19 e55e9bfd-194 Firmware Engineer We are looking for Engineers to join NVIDIA's network R&D team.

The role involves all aspects of firmware development: Design, Micro-Architecture, Software interfaces and Verification.

Responsibilities:

  • Engage in next-generation SmartNIC firmware development
  • Validate the functionalities of firmware and silicon design before tape-out, bring up new silicon when tape-out is done
  • Implement new features for congestion control, virtualization, QoS, etc.
  • Support local customers to resolve issues in deployment
  • Supply creative ideas to improve products and efficiency

Requirements:

  • Bachelor’s degree and above in EE or equivalent experience.
  • 3+ years of relevant working experience
  • Proven strong capability in C programming. Knowledge of OO, C++, Python, Shell script is plus.
  • Hands-on experience in embedded system design. Knowledge of embedded SoC architecture, network protocols. Be familiar with data structure and embedded OS.
  • Writing & speaking English fluently, be able to read English technical document and organize meetings in English.

Preferred Qualifications:

  • Self-starter, energizing, responsible, phenomenal teammate
  • Enthusiasm and determination to tackle assignments
  • Flexibility to change assignments when necessary
  • Experience with Verilog, VHDL, RDMA, virtio

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]]> full-time senior C programming, embedded system design, network protocols, English language, OO, C++, Python, Shell script, Verilog, VHDL, RDMA, virtio Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and today powers global intelligence, transforming every industry. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Beijing/Firmware-Engineer_JR2021042?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-07-17 b0a79374-5c3 DFT Verification Engineer We are looking for a Chip Design Verification Engineer to develop the next generation of DFT technologies.

As a Chip Design Verification Engineer in the DFT team at NVIDIA, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

Responsibilities:

  • In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
  • As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
  • Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

Requirements:

  • BSc. in Electrical Engineering or Computer engineering, or equivalent experience.
  • 3+ years of practical verification experience.
  • Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy).
  • Experience with Specman is a plus.
  • Good understanding of RTL design (Verilog).
  • Strong debugging, problem solving and analytical skills.
  • Excellent communication and social skills.
  • Ability to work in a geographically diverse team environment.
  • Self motivated, independent and target oriented.

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]]> full-time senior Electrical Engineering, Computer engineering, verification, DFT, design, implementation, micro-architecture, Testbenches, BFMs, Checkers, Monitors, Verilog, Specman, RTL design, debugging, problem solving, analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and today its AI infrastructure powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Tel-Aviv/DFT-Verification-Engineer_JR2020801?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Tel Aviv Tel Aviv 2026-07-15 06e874fe-b73 Senior ASIC Design Engineer - DFX We are seeking a Senior ASIC Design Engineer - DFX to join our team at NVIDIA. As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products.

Your key responsibilities will include:

  • Owning the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
  • Developing, deploying, and enhancing DFT methodologies for scalability and future product needs.
  • Defining and aligning feature sets by working closely with architects, platform, and software teams.
  • Partnering with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
  • Creating and executing test plans to support both functional and DFT full-chip verification.
  • Supporting post-silicon bring-up and validation efforts including debug and issue resolution.
  • Mentoring junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

To be successful in this role, you will need:

  • A Bachelor's degree (or equivalent experience) with 8+ years of experience, or a Master's degree in Electrical Engineering or related field with 6+ years experience.
  • 5+ years of hands-on experience in SoC architecture, RTL design, and verification.
  • Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus.)
  • Deep expertise in DFT design, methodology, and implementation.
  • Familiarity with related domains such as clocking, STA, place & route, and power optimization.
  • Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
  • Proficiency in scripting languages such as Python, Perl, or Tcl.
  • Excellent communication skills and a collaborative mindset,with a curiosity and passion for solving complex technical challenges.

In return for your hard work, we offer competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career.

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]]> full-time senior SoC architecture, RTL design, DFT design, Verilog, Python, Perl, Tcl, UVM experience Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that invented the GPU in 1999 and has since evolved to become a leader in parallel computing and artificial intelligence. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---DFX_JR2020883?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-11 71c85909-76c ASIC Design Engineer - New College Grad 2026 NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and artificial intelligence.

As a key member of the GPU Design team, you will implement, document, and deliver high-performance, area-efficient RTL to achieve design targets and specifications. You will analyze architectural trade-offs based on features, performance requirements, and system limitations. Your responsibilities will include crafting micro-architecture, implementing it in RTL, and delivering a fully verified, synthesis/timing clean design.

You will collaborate with architects, designers, pre- and post-silicon verification teams, synthesis, timing, and back-end teams to accomplish your tasks. You will work on a broad list of IPs such as GPU work schedulers, time distribution systems, interrupt controllers, and DMA engines. Additionally, you will architect features to help silicon debug and support post-silicon validation activities.

Requirements:

  • Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience in micro-architecture and RTL development (Verilog).
  • Understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
  • Exposure to digital systems, VLSI design, computer architecture, and computer arithmetic.
  • Strong interpersonal skills and teamwork abilities.

Preferred qualifications:

  • Strong C/C++, Python, or Perl skills.
  • Good debugging and analytical skills.
  • Experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks, and caches.

You will also be eligible for equity and benefits.

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]]> full-time entry ASIC design, RTL development, Verilog, Digital systems, VLSI design, Computer Architecture, Computer Arithmetic, C/C++, Python, Perl, debugging, analytical skills, arbiters, scheduling, synchronization, bus protocols, interconnect networks, caches Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that creates graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---New-College-Grad-2026_JR2020309?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-10 35ef9c27-37c Formal Verification Engineer - New College Grad 2026 NVIDIA is seeking a Formal Verification Engineer to help verify advanced processor and accelerator designs using mathematical reasoning, assertions, model checking, and formal verification tools. As an NVIDIAN, you will be immersed in an inclusive environment where everyone is inspired to do their best work.

What you will be doing:

  • Learn and apply formal verification techniques to real processor and accelerator designs.
  • Understand design behavior from specifications, RTL, and discussions with design teams.
  • Write assumptions, assertions, and cover properties to verify important microarchitectural behavior.
  • Debug formal failures and counterexamples to identify RTL bugs, property issues, or constraint problems.
  • Use abstraction, modeling, and scripting to improve proof convergence and team productivity.
  • Clearly communicate verification progress, coverage, risks, and findings.

What we need to see:

  • BS/MS/Ph.D. or equivalent experience in CS/CE/EE/Mathematics
  • Strong analytical and collaboration skills to solve complex problems.
  • Familiarity with Verilog, SystemVerilog.
  • Programming or scripting experience in Python, Tcl, Perl, C/C++, or similar.
  • Ability to learn quickly, ask good questions, and collaborate effectively.

Ways to stand out from the crowd:

  • Hands-on experience with formal tools such as JasperGold, VC Formal, or similar.
  • Experience writing SystemVerilog Assertions.
  • Passion for formal verification, digital design, computer architecture, or hardware correctness.
  • Understanding of CPU, GPU, accelerator, SoC, memory-system, or protocol microarchitecture.
  • Proven AI applications on engineering enhancement and improvements

You will also be eligible for equity and benefits.

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]]> full-time entry CS, CE, EE, Mathematics, Verilog, SystemVerilog, Python, Tcl, Perl, C/C++, JasperGold, VC Formal, SystemVerilog Assertions Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that defines the next era of computing by tapping into the potential of AI. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Formal-Verification-Engineer---New-College-Grad-2026_JR2020837?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-10 f6b31ff3-a77 GPU Core Pipeline IP Verification Engineer NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Job Responsibilities:

  • As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.
  • You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.
  • You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.
  • Work with HW architects and designers to make the right implementation choices.
  • You will be working with architects, designers, and other members of your verification teams to accomplish your tasks.

Requirements:

  • B.Tech./ M.Tech. with 2+ years of relevant experience
  • Familiarity with Verilog, C++ and OOPs concepts.
  • Experience in verification and test planning at Unit level.
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Good understanding of computer architecture concepts.
  • Strong technical fundamentals with superior analytical skills and problem-solving skills
  • Knowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable
  • Exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Prior experience in 3D graphics processing, processor verification.
  • C/C++ programming language experience
  • Experience in scripting and tool development using Perl and Python
  • Excellent debugging skills
  • Good interpersonal & communication skills & dream to work as a great teammate

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world.

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]]> full-time mid Verilog, C++, OOPs concepts, SystemVerilog, UVM methodology, computer architecture concepts, verification and test planning, 3D graphics processing, processor verification, C/C++ programming language experience, scripting and tool development using Perl and Python, debugging skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. The company is known for its GPUs used in gaming, professional visualization, datacenter, and automotive applications. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/GPU-Core-Pipeline-IP-Verification-Engineer_JR2020914?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru Bengaluru IN 2026-07-09 fdd36d07-ff8 ASIC Design Engineer, Clocks The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking.

As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints.

Responsibilities include:

  • Collaborating with frontend design team to understand clocking requirements for the chip
  • Working with backend teams to understand physical restrictions
  • Architecting, designing and validating clocks RTL
  • Running and enhancing in-house flow to guarantee good quality of clocks RTL and netlist
  • Delivering clock information to SOC verification team, timing and DFT teams
  • Using Perl/Python to improve productivity
  • Collaborating with software and silicon solution team to debug GPU clock silicon bugs

Requirements:

  • BS or MS in EE or equivalent experience
  • 2+ years of meaningful work experience
  • Validated experience in RTL design (Verilog), verification and logic synthesis
  • Strong coding skills in Perl or Python or other industry-standard scripting languages
  • Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
  • Good understanding of backend flows and requirements is a plus
  • DFT knowledge is a plus
  • Experience in implementing on-chip clocking networks is desirable
  • Excellent analytical and problem-solving skills
  • Fluent English (both written and spoken) and excellent communication skills
  • Good teamwork spirit, easy to cooperate with team members

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]]> full-time senior RTL design, Verilog, verification, logic synthesis, Perl, Python, DFT, sub-micron silicon issues, backend flows, on-chip clocking networks Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and now powers global intelligence, transforming every industry. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/China-Shanghai/ASIC-Design-Engineer--Clocks_JR2020494?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Shanghai Shanghai 2026-07-09 07c25016-ddf ASIC Verification Engineer - New College Grad 2026 NVIDIA is seeking an ASIC Verification Engineer to verify the design and implementation of the world's leading SOCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Job Description:

You will be verifying the ASIC design, architecture, golden models and micro-architecture of GPU and SoC units using Emulation and Prototyping platforms.

Your responsibilities will include:

  • Understanding the design, defining the verification scope, developing the verification infrastructure, and verifying the correctness of the RTL design.
  • Developing tools to manage and improve verification processes.
  • Collaborating with architects, designers, and software teams to accomplish your tasks.

Requirements:

  • Recent graduate with BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent experience.
  • Hardware engineering background with knowledge of Digital Design, VLSI, and/or Computer Architecture.
  • Exposure to design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB).
  • Background in building testbench environments for unit level verification.
  • Expertise in System Verilog and Verilog.
  • C++ programming language experience and Perl/Python scripting knowledge.
  • Excellent debugging, analytical, and problem-solving skills.

Preferred Qualifications:

  • Experience with PCIe and Memory protocols is highly desirable.

Benefits: You will also be eligible for equity and benefits.

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]]> full-time entry Digital Design, VLSI, Computer Architecture, System Verilog, Verilog, C++, Perl, Python, VCS, Verdi, Debussy, GDB, PCIe, Memory protocols Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Verification-Engineer---New-College-Grad-2026_JR2020640?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-07-08 2d21721e-d2c Senior Security Architect - Hardware NVIDIA is seeking a Senior Security Architect to define, craft, and guide the implementation of HW Root of Trust architecture for its SoCs and GPUs. The successful candidate will work with diverse teams across NVIDIA and external partners to meet HW Root of Trust requirements for client, automotive, gaming, and server platforms.

Responsibilities:

  • Collaborate across the company to guide the direction of platform security and develop a long-term roadmap for a flexible HW Root of Trust solution
  • Research, design, and develop architecture solutions meeting internal and external security requirements and standards
  • Review architectural, microarchitectural, and verification specifications to ensure all IPs align with platform security requirements
  • Work with customers, partners to identify and address security issues and threats

Requirements:

  • BS, MS, PhD (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
  • 8+ years of meaningful relevant work or research experience
  • Experience with the ASIC design process and architecture of large SoCs or GPUs
  • Programming and debugging fundamentals across languages such as C/C++, Verilog, ARM assembly, and Python/Perl scripting
  • Strong communication skills and ability to work in a dynamic customer-focused team
  • Direct experience with several of the following:

+ System architecture for mobile, automotive, gaming, or server platforms + SoC security architecture and security fundamentals including secure boot, measured boot, and HW root of trust + ARM or RISCV CPU architectures and related security functionality + Cryptography: algorithms, standards, implementation, and application + Security mitigations against physical attacks including fault injection and side channel attacks + Remote attestation mechanisms based on TPM or other solutions + Digital Rights Management (DRM) standards + Security threat modelling and penetration testing + Certification standards and compliance testing

Benefits:

  • Equity
  • Benefits

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]]> full-time senior ASIC design, SoC architecture, GPU architecture, Security architecture, Cryptography, Secure boot, Measured boot, HW root of trust, ARM CPU architecture, RISCV CPU architecture, Python, Perl, C++, Verilog, Communication skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that invented the GPU in 1999 and has since become a leader in parallel computing and artificial intelligence. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Security-Architect---Hardware_JR2020941?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-07-08 bb590557-f93 Senior Design Engineer - Memory Subsystem NVIDIA is seeking a Senior Design Engineer to work on the design of state-of-the-art memory subsystem components used in their industry-leading GPUs and SOCs.

In this position, you will be responsible for making architectural trade-offs based on features, performance requirements, and system limitations, coming up with micro-architecture, implementing in RTL, and delivering a fully verified, synthesis/timing clean design.

Responsibilities:

  • Own micro-architecture and RTL development of design modules.
  • Micro-architect features to meet performance, power, and area requirements.
  • Work with HW architects to define critical features.
  • Collaborate with verification teams to verify the correctness of implemented features.
  • Interact with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable.
  • Co-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
  • Work on post-silicon verification and debug.

Requirements:

  • BS/MS or equivalent experience.
  • 4+ years of design experience.
  • Experience in micro-architecture and RTL development of complex designs.
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Expertise in Verilog.

Nice to Have:

  • Design experience in memory subsystem or network interconnect IP.
  • Good debugging and problem-solving skills.
  • Scripting knowledge (Python/Perl/shell).
  • Good interpersonal skills and ability & desire to work as part of a team.

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]]> full-time senior ASIC design, RTL development, Verilog, VCS, Debussy, GDB, Python, Perl, shell scripting, memory subsystem, network interconnect IP, debugging, problem-solving, interpersonal skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that produces graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Design-Engineer---Memory-Subsystem_JR2020816?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-07-07 a6921565-b6b Senior ASIC Hardware Design Engineer NVIDIA is seeking a Senior ASIC Hardware Design Engineer to join their NVLink ASIC Design team. The successful candidate will work on designing and implementing next-generation NVLink protocol and GPU subsystem logic.

The role involves:

  • Engaging in and supporting the design and development of NVIDIA's next-generation NVLink protocol and GPU subsystem logic.
  • Contributing to micro-architecture development and documenting specifications of GPU and interconnect sub-systems.
  • Implementing designs in RTL and debugging while collaborating with the verification team.
  • Optimizing designs to meet performance and power goals.
  • Collaborating with the physical design team to ensure a routable and physically implementable solution.
  • Supporting hardware engineering activities including chip floor plan, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back-end verification.
  • Developing flows and tools as necessary in support of design activities.

The ideal candidate will have:

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience and 5+ years of industry experience.
  • A solid practical understanding of Verilog and/or SystemVerilog.
  • Relevant project experience in micro-architecture and RTL development of complex designs.
  • Exposure to computer architecture and digital systems designs.
  • High proficiency in logic development, Verilog and/or SystemVerilog, with an understanding of physical implementation and VLSI.
  • Strength in scripting languages such as Perl or Python.
  • Strong collaboration and communication skills.

NVIDIA offers competitive salaries and a generous benefits package.

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]]> full-time senior Verilog, SystemVerilog, RTL development, micro-architecture, VLSI, Perl, Python, low-power build methodologies, high-speed build methodologies, complex design implementation Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-MA-Westford/Senior-ASIC-Hardware-Design-Engineer_JR2020734?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Westford, MA Westford MA US 2026-07-03 710bca6e-d5a Emulation and Prototyping Engineer NVIDIA is seeking an Emulation and Prototyping Engineer to join our Emulation team.

The successful candidate will work on building FPGA prototypes and hardware emulation environments for our next-generation GPUs, SOCs, NICs, and Switches.

Key Responsibilities:

  • Building FPGA prototypes and hardware emulation environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.
  • Improving performance of FPGA prototypes and emulation platforms, analyzing timing/performance bottlenecks, and generating bitstreams/images.
  • Bringing up designs on FPGA prototyping and hardware emulation platforms and driving complex debug and problem-solving activities.
  • Releasing prototypes and emulation environments to internal customers and supporting them through debug, validation, and software enablement.
  • Understanding the design and implementation, defining configurations, developing/modifying bring-up and testing infrastructure, and verifying correctness of the design.
  • Working closely with architects, designers, verification engineers, validation teams, and software teams to accomplish project goals.

Requirements:

  • B.S. or M.S. in EE, CS, or CE with 3+ years of experience in FPGA prototyping and/or hardware emulation.
  • Strong understanding of FPGA prototyping and hardware emulation architectures, devices, flows, and tools.
  • Hands-on experience with Synopsys ProtoCompiler or Synplify Premier, Xilinx Vivado, and familiarity with emulation platforms such as Synopsys ZeBu or Siemens Veloce.
  • Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB).
  • Knowledge of Verilog, SystemVerilog, and digital design concepts.
  • Understanding of industry-standard protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU-GPU coherency.

Desired Skills:

  • Scripting knowledge (Perl/shell/Tcl/Python).
  • Good documentation, communication, and interpersonal skills.
  • Experience with memory bring-up of LPDDR5/6, DDR5/6, CXL/PCIe, and/or high-speed interfaces such as USB4/3.

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]]> full-time senior onsite FPGA prototyping, hardware emulation, Synopsys ProtoCompiler, Xilinx Vivado, ASIC design, Verilog, SystemVerilog, digital design, PCIe, CXL, NVLINK, USB, CHI, CPU-GPU coherency, scripting, documentation, communication, interpersonal skills, memory bring-up, LPDDR5/6, DDR5/6, CXL/PCIe, USB4/3 Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that pioneered accelerated computing and develops graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Emulation-and-Prototyping-Engineer_JR2020636?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru Bengaluru IN 2026-07-02 18a70365-451 CPU Verification Infrastructure Tools Architect We are seeking a skilled Hardware and Software Developer to join our dynamic SoCV/Emulation Infrastructure and test-frameworks team.

The successful candidate will be responsible for designing and building tools, infrastructure, and test frameworks used in RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon.

Key responsibilities include:

  • Understanding Tegra system architecture, focusing on IPs involved in boot and security features
  • Developing tools that enable Design and Verification teams to access registers/memory/DMA engines and other features in their unit
  • Building C-model or RTL-simulation capability to simulate features before Silicon arrival in a pre-silicon environment
  • Assessing and developing features used for Silicon bring-up, such as FUSE, ATE, Security, Flash/DMA, Board I2Cs, and USB debug devices

Requirements:

  • BS or MS in Computer Science or Electronics Engineering with 5+ years of experience
  • Strong programming skills in C, C++, and Python
  • Understanding of SOC and System Architecture
  • Knowledge of SOC devices, including DMA, interrupt-engines, CPU, boot-devices, and MMU/IOMMU
  • Experience with Operating System and Device-Driver concepts, and ability to write no-OS test frameworks
  • Strong software development skills, with a focus on scalability and maintainability

Preferred qualifications:

  • Previous experience handling Silicon Bringup and enabling Emulation/FPGA-related test frameworks
  • Exposure to Testbench architectures, including C++ testbenches and SV/UVM-based testbenches
  • Verilog and System Verilog coding skills

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]]> full-time senior C, C++, Python, SOC, System Architecture, DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU, Operating System, Device-Driver, Verilog, System Verilog, Testbench architectures, Silicon Bringup, Emulation/FPGA Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Hyderabad/CPU-Verification-Infrastructure-Tools-Architect_JR2020428?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hyderabad, India Hyderabad India IN 2026-07-02 1ba7b843-e06 ASIC Verification Engineer We are seeking an ASIC Verification Engineer to join our dynamic SoCV/Emulation Infrastructure and test-frameworks team.

The role involves building tools, infrastructure, and test frameworks for RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon. You will need to understand the Tegra system architecture, focusing on IPs in the SOC involved in boot and security features.

Key responsibilities:

  • Develop tools that enable Design and Verification teams to access registers/memory/DMA engines and other features in their unit.
  • Build features used for Silicon bring up, such as FUSE, ATE, Security, Flash/DMA, Board I2Cs, and USB debug devices.
  • Assess and build C-model or RTL-simulation capability to simulate features before Silicon arrival in a pre-silicon environment.

Requirements:

  • BS or MS in Computer Science or Electronics Engineering or equivalent experience with 0-2 years of experience.
  • Strong programming skills in C, C++, and Python.
  • Understanding of SOC and System Architecture.
  • Knowledge of SOC devices like DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU.
  • Experience with Operating System and Device-Driver concepts.

Preferred qualifications:

  • Previous experience handling Silicon Bringup and enabling Emulation/FPGA related test frameworks.
  • Exposure to Testbench architectures (C++ testbenches, SV/UVM based testbenches).
  • Verilog and System Verilog coding skills are a plus.

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]]> full-time entry C, C++, Python, SOC, System Architecture, DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU, Operating System, Device-Driver, Silicon Bringup, Emulation/FPGA, Testbench architectures, Verilog, System Verilog Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Hyderabad/ASIC-Verification-Engineer_JR2020484?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hyderabad Hyderabad 2026-07-01 b7f45375-ce4 Senior ASIC Hardware Design Engineer NVIDIA is seeking a Senior ASIC Hardware Design Engineer to join their team in Israel. The successful candidate will be responsible for designing and implementing high-performance, low-power security engines and RISC-V processor modules.

The engineer will participate in micro-architecture development, document specifications, implement designs in RTL, and work with the verification team to ensure functionality.

Responsibilities include:

  • Participating in micro-architecture development and documenting specifications
  • Implementing designs in RTL and working with the verification team
  • Applying logic design skills to optimize performance and power goals
  • Delivering a synthesis/timing clean design while working with the physical design team

Requirements:

  • Bachelor's degree in Electrical Engineering or Computer Engineering
  • 5+ years of relevant experience in chip design development of complex designs
  • Highly proficient in logic design, Verilog, and/or System-Verilog, with a deep understanding of physical design and VLSI
  • Good interpersonal skills and team player

NVIDIA offers competitive salaries and a generous benefits package.

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]]> full-time senior ASIC design, RTL implementation, Verilog, System-Verilog, VLSI, physical design, logic design Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Israel-Beer-Sheva/Senior-ASIC-Hardware-Design-Engineer_JR2020435-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Beer Sheva, Israel Beer Sheva Israel IL 2026-06-29 ccdc56cc-8f3 Senior ASIC Design Engineer - Agentic AI NVIDIA is seeking Senior ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoCs and GPUs.

As part of NVIDIA's 'AI for chip design' team, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of chip design at NVIDIA and throughout the industry.

Responsibilities:

  • As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high-performance, area and power-efficient RTL to achieve design targets and specifications.
  • As part of the AI for Chip Design team, you will develop agentic AI solutions to craft the micro-architecture, implement the RTL, and deliver a fully verified, synthesis/timing clean design.
  • Collaborate and coordinate with other designers as well as tool and flow owners to ensure design guidelines and agentic solutions meet their requirements.
  • Use AI technologies to tackle complex problems in chip design, driving innovation and meaningful impact across the industry.
  • Design and deploy LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems.
  • Engage with the latest advancements in machine learning and AI to create powerful solutions.

Requirements:

  • Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development (Verilog) in complex designs.
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
  • Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
  • Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
  • Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines and vector databases.
  • Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
  • A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.

You will also be eligible for equity and benefits.

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]]> full-time senior ASIC design, Agentic AI, Micro-architecture, RTL development, Verilog, ASIC design flow, RTL design, Verification, Logic synthesis, Timing analysis, Digital systems, VLSI design, Computer Architecture, Computer Arithmetic, Python, Data structures, Algorithms, Software engineering principles, Large language models, Multi-agent systems, RAG pipelines, Vector databases Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. The company is a leader in the field of artificial intelligence and computer graphics. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Agentic-AI_JR2020334?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-06-27 df5b48a1-d5c ASIC Digital Design, Sr Staff Engineer Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building digital IP that has to meet ISO 26262 ASIL D, not just pass functional verification. You know the difference between a controller that works in simulation and one that survives FMEDA, DFMEA, and real-world automotive stress, and you have debugged enough corner cases to know where those gaps usually hide. You think in RTL, but you also think in safety mechanisms, fault injections, and what it takes to qualify hardware for a car that cannot fail.

Responsibilities

  • Design and own RTL for automotive digital IP blocks, with a focus on PCIe, DDR, or UCIe controllers that meet ISO 26262 functional safety requirements
  • Lead RTL coding, lint and CDC analysis, synthesis optimization, and debug across complex IP subsystems
  • Work closely with verification teams to define Verification IP scope, identify feature coverage gaps, and ensure controllers are fully validated before tapeout
  • Drive safety qualification activities including DFMEA, FMEDA, and DFA for IP targeting ASIL D
  • Mentor and guide engineering teams through design flows, coding standards, and best practices for synthesizable Verilog and System Verilog
  • Apply and evaluate AI-driven design tools and methodologies to improve design quality and automation

Requirements

  • Bachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience in Automotive SoCs or Digital IPs
  • Proven IP-level experience with protocols like PCIe, DDR, or UCIe, with PCIe experience strongly preferred
  • Demonstrated ability to work as an individual contributor while mentoring and leading engineering teams through RTL coding, lint/CDC analysis, synthesis, and debug
  • Experience qualifying embedded hardware systems to ISO 26262 ASIL levels up to ASIL D, and working with DFMEA, FMEDA, and DFA
  • In-depth experience writing synthesizable Verilog/System Verilog for ASIC design and simulation tools
  • Strong command of ASIC design flows, including lint, CDC, synthesis, Static Timing Analysis, and formal verification

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family
  • Time away programs, including ETO and FTO
  • Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
  • Retirement plans that vary by region and country
  • Competitive salaries

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]]> full-time senior onsite RTL development, ISO 26262, PCIe, DDR, UCIe, Verilog, System Verilog, ASIC design, lint, CDC analysis, synthesis optimization, PCIe experience Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com https://careers.synopsys.com/job/dublin/asic-digital-design-sr-staff-engineer/44408/96919787104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Dublin, Leinster Dublin Leinster IE 2026-06-25 3928e2d6-207 Senior ASIC Design Engineer - XBAR IP NVIDIA is seeking a Senior ASIC Design Engineer to join its Graphics team, working on state-of-the-art memory subsystem components used in industry-leading Graphics Processors. The successful candidate will have the opportunity to make a real impact in a dynamic, technology-focused company.

The role involves making architectural trade-offs, coming up with micro-architecture, implementing in RTL, and delivering a fully verified, synthesis/timing clean design. The engineer will work with architects, designers, verification teams, synthesis, timing, and backend teams.

Responsibilities:

  • Own micro-architecture and RTL development of design modules.
  • Micro-architect features to meet performance, power, and area requirements.
  • Work with HW architects to define critical features.
  • Collaborate with verification teams to verify the correctness of implemented features.
  • Co-operate with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable.
  • Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
  • Work on post-silicon verification and debug.

Requirements:

  • BS/MS or equivalent experience.
  • 5+ years of design experience.
  • Experience in RTL design of complex design units for at least two or three projects.
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Expertise in Verilog.

Preferred Qualifications:

  • Design experience in memory subsystem or network interconnect IP.
  • Good debugging and problem-solving skills.
  • Scripting knowledge (Python/Perl/shell).
  • Leadership experience in leading small 2-3 member teams.
  • Good interpersonal skills and ability & desire to work as part of a team.

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]]> full-time senior ASIC design, RTL design, Verilog, VCS, Debussy, GDB, DFT, timing analysis, memory subsystem, network interconnect IP, Python, Perl, shell scripting, leadership Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that designs and manufactures graphics processing units and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-ASIC-Design-Engineer---XBAR-IP_JR2020168?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-06-25 cb734b13-506 PCIe IP Verification Engineer NVIDIA is seeking a Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world's leading GPUs and SOCs.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Responsibilities:

  • Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

  • B.Tech./ M.Tech or equivalent experience
  • 2+ years of relevant experience
  • Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
  • Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Excellent knowledge of PCIE protocol - Gen3 and above
  • Good understanding of the system level architecture of PCIE/CXL-based designs
  • Perl, Python or similar scripting and SW programming language experience
  • Good debugging and analytical skills
  • Good interpersonal skills & dream to work as a great teammate

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]]> full-time senior ASIC design, Verification methodologies, UVM, SystemVerilog, Verilog, PCI Express, IP verification, PCIE protocol, Python, Perl, Debugging, Analytical skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a computing company that produces GPUs and SOCs for various applications including graphics, artificial intelligence, and autonomous vehicles. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/PCIe-IP-Verification-Engineer_JR2019919-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-06-25 098c0826-8ff IP Verification Engineer - GPU Core Pipeline NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the world’s leading GPUs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.
  • You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.
  • You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.
  • Work with HW architects and designers to make the right implementation choices.
  • You will be working with architects, designers, and other members of your verification teams to accomplish your tasks.

Requirements:

  • B.Tech./ M.Tech. with 2+ years of relevant experience
  • Familiarity with Verilog, C++ and OOPs concepts.
  • Experience in verification and test planning at Unit level.
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Good understanding of computer architecture concepts.
  • Strong technical fundamentals with superior analytical skills and problem-solving skills
  • Knowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable
  • Exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

  • Prior experience in 3D graphics processing, processor verification.
  • C/C++ programming language experience
  • Experience in scripting and tool development using Perl and Python
  • Excellent debugging skills
  • Good interpersonal & communication skills & dream to work as a great teammate

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]]> full-time mid Verilog, C++, OOPs concepts, verification, test planning, UVM methodology, SystemVerilog, computer architecture, 3D graphics processing, processor verification, C/C++ programming, scripting, tool development, Perl, Python, debugging Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/IP-Verification-Engineer---GPU-Core-Pipeline_JR2019962?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-06-25 8db36956-2c2 Senior GPU Floorplan Design Engineer NVIDIA is seeking a talented GPU Floorplan design Engineer to design and implement the world’s leading GPU's as part of a completely new team being built in Bangalore.

This role sits at the intersection of architecture, RTL, performance analysis, and physical design, with a strong focus on path forward, early planning, feasibility studies, and physical trade-off exploration.

Responsibilities:

  • Working with architects, design leads, physical design leads, and package leads, you will develop and craft and optimize floorplans during early chip development.
  • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect, and floorplan improvement opportunities.
  • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Requirements:

  • B.Tech./M.Tech. with 5+ years of experience in floorplan, SOC planning, ASIC Physical design, or related roles.
  • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
  • Hands-on experience with chip-level or subsystem-level floorplanning and physical planning.
  • Solid understanding of timing, congestion, power distribution, and physical constraints.
  • Experience in Verilog, System Verilog, or similar HVL.
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
  • Strong communication and interpersonal skills and ability & desire to work as a great teammate.
  • Python, Perl, and C/C++ programming language experience.

Preferred Qualifications:

  • Experience in driving development of large-scale ASIC floorplan is a huge plus.

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]]> full-time senior VLSI, Computer Architecture, ASIC Physical design, Floorplan, SOC planning, Verilog, System Verilog, CAD, Physical design methodologies, Python, Perl, C/C++, Large-scale ASIC floorplan development Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA pioneered accelerated computing and now powers global intelligence, transforming every industry. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-GPU-Floorplan-Design-Engineer_JR2020167?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru Bengaluru 2026-06-25 97a49f52-fff Senior Mixed Signal Design Engineer As a Senior Mixed Signal Design Engineer at NVIDIA, you will be part of the Mixed Signal team, responsible for architecture definition and design of CMOS high-speed interface circuits and mixed-signal circuits.

You will be working on the design and implementation of high-speed interface circuits, creating projects including high-speed transceivers and high-frequency PLLs, and becoming involved in the design, simulation, and verification of mixed-signal circuits.

Key responsibilities include:

  • Leading mask designers and providing mentorship for floorplan and layout design
  • Supporting lab characterization of silicon and pursuing circuit design challenges in deep submicron CMOS
  • Taking designs through implementation and productizing, collaborating with multi-functional teams

Requirements:

  • BS or MS in Electrical Engineering, PhD preferred (or equivalent experience)
  • 5+ years of design experience in CMOS analog/mixed-signal circuits
  • Working knowledge of Cadence custom design tools, circuit simulator, and timing analysis tool
  • Exceptional teamwork and interpersonal skills, with experience leading and mentoring designers
  • Extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high-speed IO interfaces
  • Proven experience in silicon bring-up, debugging, and use of lab instrumentation

Preferred skills:

  • Experience in Verilog, Matlab, Nanotime
  • Knowledge in system-level timing budget, signal integrity, and power integrity

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]]> full-time senior CMOS analog/mixed-signal circuits, Cadence custom design tools, circuit simulator, timing analysis tool, Data Converters, Tx, Rx, CDR, PLL, Verilog, Matlab, Nanotime Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA invented the GPU in 1999 and has since become a leader in parallel computing and AI infrastructure. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Mixed-Signal-Design-Engineer_JR2020083?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Hsinchu Hsinchu 2026-06-25 975a384a-f88 Design Engineer, Coherent High Speed Interconnect NVIDIA is seeking a Senior Design Engineer for its Coherent High Speed Interconnect team. The NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • Work on architecture and design of state-of-the-art high-speed coherent interconnects (NVLINK-C2C) for mobile SoCs and GPUs.
  • Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class-leading high-speed coherent interconnect.
  • Optimize design based on features, requirements, and system limitations.

Requirements:

  • BS or equivalent experience in Electrical Engineering or Computer Engineering or related degree required.
  • Relevant design experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
  • Knowledge of industry-standard interconnect protocols like PCIE, CXL, AXI, CHI will be useful.
  • Strong working knowledge of Verilog or System Verilog.
  • Good communication skills and interpersonal skills are required.

Preferred Qualifications:

  • Master's or PhD degree will be preferred.
  • A history of mentoring junior engineers and interns is a plus.

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]]> full-time senior Electrical Engineering, Computer Engineering, RTL design, Verilog, System Verilog, PCIE, CXL, AXI, CHI, Master's degree, PhD degree, Mentoring experience Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that creates graphics processing units (GPUs), deep learning platforms, and high-performance computing hardware. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Design-Engineer--Coherent-High-Speed-Interconnect_JR2019673?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply 2026-06-22 485eabfc-377 ASIC Design Engineer - Hardware Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects!

What you'll be doing:

  • Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
  • Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
  • Deliver IP and support projects by applying the performance monitoring system
  • Run and debug RTL checks to ensure design quality (e.g., cross clock domains, clocks, reset, latency, and more)
  • Design and implement RTL features (microarchitecture and RTL)
  • Work with architects, designers, and software engineers to accomplish your tasks

What we need to see:

  • BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus
  • 2+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages
  • Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automation
  • Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow
  • Excellent debugging and analytical skills
  • Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
  • Great communication and collaboration skills to interact within the team and with cross-functional teams

Ways to stand out from the crowd:

  • Hands-on experience in object-oriented programming
  • Prior design on system level IP (Clocks/DFT/Resets)
  • Experience developing methodologies used by others
  • Hands-on silicon debug is a plus
  • Exposure to physical design

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers.

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]]> full-time senior onsite RTL design, Verilog, SystemVerilog, System-On-Chip design, design automation, Perl, Python, object-oriented programming, physical design, silicon debug Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company has been doing so for over 25 years. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-TX-Austin/ASIC-Design-Engineer---Hardware_JR2019840?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Austin, TX Austin TX US 2026-06-18 ed8c1938-37f Senior Verification Engineer NVIDIA is seeking a Senior SoC/CPU Verification Engineer to verify the world's most powerful CPUs/Socs with AI capabilities for self-driving cars, gaming consoles, and other automated machines. As a Senior Verification Engineer, you will work alongside brilliant engineers on NVIDIA's next-generation CPU, verifying micro-architecture/architecture features at the unit level or subsystem or full chip testbenches, including FPGA/Silicon.

Responsibilities:

  • Work on verifying micro-architecture/architecture features at unit level or subsystem or full chip testbenches including FPGA/Silicon
  • Partner with CPU architects in crafting verifiable designs
  • Work on full stack development - from verifying sequences at SW simulator level, to getting the overall end-to-end sequence working on silicon with a full SW stack

Requirements:

  • Strong verification fundamentals and ability to juggle working on SW simulators vs Silicon
  • Proficiency in CPU architecture (ARM knowledge is desirable), Coherent fabric designs, Verilog, System Verilog, and possess strong debugging skills
  • 3+ years of experience with Bachelors/Masters in Computer Science or Electronics Engineering or equivalent experience

Nice to Have:

  • Experience working on various pieces of CPU unit/microarchitecture verification, Interconnect, system memory coherency
  • Experience working on complex coverage-driven verification projects
  • Experience collaborating with geographically diverse multi-functional teams

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]]> full-time senior CPU architecture, Coherent fabric designs, Verilog, System Verilog, debugging skills, ARM knowledge, complex coverage-driven verification projects, collaboration with multi-functional teams Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-Verification-Engineer_JR2017972?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, India Bengaluru India IN 2026-06-18 de86dac3-d17 FPGA Engineer As an FPGA Engineer you'll be responsible for the architecture, design, verification, and test of RTL designs for the FPGAs that go into the spacecraft. You will work closely with the software, DSP and hardware teams to achieve design requirements.

Responsibilities:

  • Design RTL for high performance systems including software defined radios, avionics and ground systems, for commercial and US Government projects
  • Work with multiple FPGAs and toolchains
  • Interface FPGAs with high speed data converters, memories, MCUs
  • Design, implement and test radiation mitigation schemes on FPGA
  • Collaborate closely with DSP/radio algorithm designer
  • Collaborate closely with embedded firmware and software engineers
  • Assist in recruiting, interviewing, and hiring additional teammates to our rapidly-growing team.

Requirements:

  • US Citizenship or Green Card (This is a legal requirement; no exceptions)
  • Bachelor of Science degree in electrical engineering, computer science, computer engineering, or equivalent
  • 2+ years of experience
  • A passion for hardware development, including working in a fast-paced environment and hands-on design and development
  • Experience in designing, implementing, verifying and testing high throughput systems implemented on FPGAs
  • Strong proficiency with Verilog (preferably SystemVerilog) for both synthesis and verification

Bonus:

  • MS or PhD in computer engineering or equivalent
  • Experience in at least 1 domain beyond just the logic design. This could be DSP/radio design, software, hi-reliability design (e.g. fault analysis & recover), etc.
  • Experience with Xilinx FPGAs
  • Experience with modern communication systems (RF, IF/IQ, time/freq domains, modulation)
  • Experience with Vivado IDE, TCL
  • Familiarity with system level estimates and implications of power, thermal, and real estate
  • Experience with high speed data converters (ADCs, DACs, JESD204)
  • Experience with circuit level debugging
  • Experience with digital communication theory and implementation, such as LDPC implementations
  • Experience with space-based systems
  • Experience with UVM

What we offer: All our positions offer a compensation package that includes equity and robust benefits.

Base pay is just one component of Astranis's total rewards package. Your compensation also includes a significant equity package via incentive stock options, high-quality company-subsidized healthcare, disability and life insurance, 401(k) retirement planning, flexible PTO, and free on-site catered meals.

The actual base salary offered to a successful candidate will be influenced by a variety of factors including experience, credentials & certifications, educational attainment, skill level requirements, and the level and scope of the position.

Base Salary: $140,000-$205,000 USD

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]]> full-time mid onsite $140,000-$205,000 USD FPGA design, RTL design, Verilog, SystemVerilog, FPGA architecture, digital design, hardware development, Xilinx FPGAs, Vivado IDE, TCL, DSP/radio design, software development, hi-reliability design, fault analysis & recover, space-based systems, UVM Engineering Technology Astranis https://logos.yubhub.co/astranis.com.png Astranis builds advanced satellites for high orbits, expanding humanity's reach into the solar system. The company has raised over $750 million from investors and employs a team of 450 engineers and entrepreneurs. https://astranis.com USD 140000 205000 yearly https://job-boards.greenhouse.io/astranis/jobs/4325685006?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply San Francisco San Francisco 2026-06-18 a1986336-e8c Senior Verification Engineer - Hardware NVIDIA is seeking a Senior Verification Engineer for its Emulation division in Santa Clara, CA. The engineer will work on emulation environments, bring up SOCs on emulation, and collaborate with various teams.

Key Responsibilities:

  • Support multiple emulation environments using the latest techniques such as C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, and Accelerated UVM Testbenches.
  • Bring up SOCs on emulation, root cause SoC/Processor test fails, and resolve emulator environment issues.
  • Collaborate continually with Design, DV, Power, Silicon Validation, Performance, and Software teams.
  • Lead emulation vendors to debug issues using various tools.

Requirements:

  • Master's degree or equivalent in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • At least 3 years of proven experience.
  • Proficiency in Verilog and/or VHDL, C/C++, and SystemVerilog.
  • Essential experience with UVM verification environments and scripting with Perl, Python, and C/C++.
  • Familiarity with hierarchical design approaches, top-down design, SoC, and system-level verification.
  • This role is based on-site at NVIDIA's Santa Clara, CA office.

NVIDIA offers highly competitive salaries and a comprehensive benefits package, including eligibility for equity.

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]]> full-time senior onsite Verilog, VHDL, C/C++, SystemVerilog, UVM verification environments, Perl, Python, hierarchical design approach, top-down design, SoC verification, system-level verification Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA transforms computer graphics, PC gaming, and accelerated computing. The company invented the GPU in 1999 and recently ignited modern AI through GPU deep learning. https://www.nvidia.com https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Verification-Engineer---Hardware_JR2019800-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-06-18 42a62d82-219 Software R&D Engineer, RTL Optimization Tools We are seeking an innovative CAD Software Engineer with particular interest in strategies and algorithms for large scale RTL quality, timing, and power optimization. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++.

In this role, you will be responsible for inventing new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation. You will also devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.

Requirements:

  • MS or PhD in Electrical Engineering or Computer Science or equivalent experience
  • 3+ years of relevant experience in CAD software and VLSI hardware design
  • Demonstrated ability in software development with C++, particularly in algorithm development related to graph traversal, pattern matching, and optimization
  • Familiarity with RTL design, including Verilog and SystemVerilog code, as well as general hardware design concerns such as scan chain insertion, MBIST, clock and power distribution, and bus architectures
  • Familiarity with related EDA techniques, including logic synthesis, global route, static timing analysis, and SAT solvers
  • Strong communication and interpersonal skills

Preferred qualifications include experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization. Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc. is also desired.

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]]> full-time senior hybrid Competitive salary and benefits package C++, RTL design, Verilog, SystemVerilog, graph traversal, pattern matching, optimization, EDA techniques, logic synthesis, global route, static timing analysis, SAT solvers, Verific, Espresso, logic rewriting, tree coverage, combinatorial optimization, multithreading, distributed computing, efficient memory and I/O use Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a leading technology company that specializes in designing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ USD 120000 180000 yearly https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Software-R-D-Engineer--RTL-Optimization-Tools_JR2019332?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Santa Clara, CA Santa Clara CA US 2026-06-12 02423838-827 DFX CAD Tools Development Engineer DFX CAD Tools Development Engineer

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locationsIndia, Bengaluru

time typeFull time

posted onPosted Today

job requisition idJR2019454

As part of the CAD team, our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in the area of Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL.

What you will be doing:

  • Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object-oriented techniques.
  • Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.
  • Support development of tools using C++/Python/TCL.
  • Work cross-functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.

What we need to see:

  • 2+ years of relevant work experience.
  • Smart, diligent, and motivated to work in our CAD group.
  • BE or BTech or MTech in Computer Science, or Electronics Engineering, or Electrical Engineering, or equivalent experience.
  • Knowledge or experience with DFT, DFP is a plus.
  • Familiar with Verilog, VLSI, and ASIC design principles, including knowledge of logic cells.
  • Software engineering: software design, algorithms, and QA.
  • Strong C++ programming experience.
  • Solid programming and scripting skills in Python or TCL desired.
  • Knowledge of GenAI, LLM, AI Code Generation is a plus.
  • Having strong interpersonal skills will serve you well in this role.

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you!

#LI-Hybrid

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]]> full-time mid onsite C++, Python, TCL, Verilog, VLSI, ASIC design principles, Logic cells, Software design, Algorithms, QA, GenAI, LLM, AI Code Generation Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specializes in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/DFX-CAD-Tools-Development-Engineer_JR2019454?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, KA Bengaluru KA IN 2026-06-12 44827f8b-be9 ASIC Design Engineer ASIC Design Engineer

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locations India, Bengaluru

time type Full time

posted on Posted Today

job requisition id JR2019598

NVIDIA is seeking outstanding ASIC Design Engineers to design and implement world's leading SoC's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you will be doing:

  • Work with system architects to understand the functional and performance requirements of a unit or feature.
  • Define micro-architecture and develop RTL for owned unit and/or feature.
  • Work with verification and physical design teams to ensure that the unit or feature is accurately verified and implemented.
  • Own silicon bring-up in conjunction with post silicon validation and SW teams.
  • Mentor junior engineers and guide them in their work.

What we need to see:

  • BS / MS or equivalent experience.
  • 2+ years of experience.
  • Proven knowledge in implementation of complex features or units.
  • Expertise in micro architecture definition, RTL coding using Verilog or System Verilog.
  • Expertise in using design and verification tools (Synthesis, lint, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
  • Experience in memory controller, memory management unit, interconnect design and cache controller design desirable.
  • Good debugging and problem solving skills. Scripting knowledge.
  • Good interpersonal skills and ability & desire to work as a teammate are a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.

#LI-Hybrid

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

Learn more about NVIDIA.

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]]> full-time mid onsite Verilog, System Verilog, Synthesis, Lint, VCS, Debussy, GDB, Memory Controller, Memory Management Unit, Interconnect Design, Cache Controller Design Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for over 25 years. It's a technology company that has made significant contributions to various industries. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Design-Engineer_JR2019598?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, IN Bengaluru IN IN 2026-06-11 0f2e0ca7-5ed ASIC Digital Design, Staff Engineer Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years in the trenches of digital design where the difference between RTL that synthesizes cleanly and RTL that becomes someone else's nightmare is a decision you made on Tuesday. You know that writing Verilog is the easy part. The hard part is writing Verilog that closes timing, passes CDC without waivers, and does not make the implementation team want to rewrite your entire block.

You think about synthesis while you write RTL. Timing arcs are not abstract concepts, they are the reason you structured that state machine the way you did. When a design review surfaces a potential CDC issue, you are already three steps ahead, sketching the synchronizer and thinking through the corner cases. At Synopsys, you will work on real IP that ships in real products.

Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog. Refine micro-architecture with focus on synthesizability, timing, testability, area, and power tradeoffs. Drive synthesis and front-end implementation activities. Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure. Work with implementation teams on STA fundamentals, timing constraints, and timing arc understanding. Collaborate with verification teams on functional debug, test planning, assertions, and coverage. Support debug and issue resolution using Verdi or similar debug tools. Participate in design reviews and help resolve integration and interoperability issues across product lines. Develop automation scripts for design, debug, reporting, and productivity.

Your RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide. You will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs. Your collaboration will catch issues earlier, reducing costly respins and late-stage fixes. The automation you build will improve design productivity across multiple product lines. Your attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in digital design and/or RTL development. Practical knowledge of Verilog/SystemVerilog. Practical understanding of the ASIC design flow. Strong background in synthesis, front-end implementation, and design-for-closure methodology. Practical understanding of STA, timing constraints, and timing arcs. Experience with CDC/RDC/Lint concepts and signoff-ready design practices. Ability to collaborate effectively with verification, implementation, and validation teams. Scripting experience in Python, Tcl, Perl, or Shell. Strong communication and cross-team collaboration skills.

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]]> employee staff onsite Verilog, SystemVerilog, ASIC design flow, Synthesis, Front-end implementation, Design-for-closure methodology, STA, Timing constraints, Timing arcs, CDC/RDC/Lint, Python, Tcl, Perl, Shell Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a leading provider of electronic design automation (EDA) software and services. It was founded in 1986 and has since grown to become a global company with over 9,000 employees. https://careers.synopsys.com https://careers.synopsys.com/job/yerevan/asic-digital-design-staff-engineer/44408/96215645408?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Yerevan Yerevan AM 2026-06-10 9ccd1c3f-18d Verification Engineer - PCIE Verification Engineer - PCIE

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world's leading GPUs and SOCs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

  • Responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
  • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

  • B.Tech./ M.Tech. with 2+ years of relevant experience.
  • Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog.
  • Background with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA).
  • Experience in developing and working in functional coverage based constrained random verification environments.
  • Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.

Nice to Have:

  • Excellent problem solving skills.
  • Knowledge of PCIE protocol - Gen3 and above.
  • Proficiency in Testbench development using SystemVerilog.
  • Perl, Python or similar scripting and SW programming language experience.
  • Good debugging and analytical skills.
  • Good interpersonal skills & dream to work as a great teammate.

With competitive salaries and a generous benefits package, Nvidia is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.

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]]> full-time mid onsite UVM, SystemVerilog, Verilog, PCI Express, USB, SATA, DV methodologies, industry standard verification tools, Perl, Python, scripting, SW programming language, debugging, analytical skills, interpersonal skills Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---PCIE_JR2019560?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, IN Bengaluru IN US 2026-06-10 6ad643d1-286 Senior Staff RTL Design Engineer Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

  • Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
  • Optimize designs to meet timing, power, and area targets across multiple process nodes
  • Develop Perl automation for design generation and flow integration
  • Collaborate with cross-functional teams to resolve timing and power challenges
  • Contribute to design reviews and methodology development

The Impact You Will Have

  • Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products
  • You will contribute to a major revenue-generating product line for Synopsys
  • Your work will define performance characteristics for customer systems-on-chip
  • Your automation will improve design efficiency across the engineering team
  • Your expertise will influence architectural decisions for future products

What You'll Need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 10+ years of ASIC digital design experience with RTL ownership in production silicon
  • Expert Verilog proficiency for timing-critical designs
  • Strong Perl scripting skills for design automation
  • Deep knowledge of synthesis, timing analysis, and power optimization
  • Experience with PHY IP or high-speed interfaces is preferred

Who You Are

  • You understand how RTL structure affects timing and power outcomes
  • You communicate effectively across technical disciplines
  • You produce maintainable code that supports collaboration
  • You identify process improvements proactively
  • You resolve technical issues through systematic analysis

The Team You'll Be Part Of

You will join the team responsible for microarchitecture and front-end design of LPDDR PHY IP. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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]]> full-time senior onsite $138,000 - $208,000 RTL design, ASIC digital design, Verilog, Perl scripting, Synthesis, Timing analysis, Power optimization, PHY IP, High-speed interfaces Engineering Technology Synopsys https://logos.yubhub.co/careers.synopsys.com.png Synopsys is a leading provider of engineering solutions for silicon to systems, enabling customers to rapidly innovate AI-powered products. https://careers.synopsys.com USD 138000 208000 yearly https://careers.synopsys.com/job/boxborough/senior-staff-rtl-design-engineer-16908/44408/93816738832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Boxorough, Massachusetts Boxorough Massachusetts 01719 US 2026-06-09 26f3d4a3-906 Senior IP Design Verification Engineer - XBAR IP We are seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world's leading GPUs and SOCs.

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Responsibilities:

  • Verify the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.
  • Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
  • Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
  • Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Work on advanced verification methodologies like SV/UVM.
  • Perform functional coverage driven verification closure.
  • Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Requirements:

  • B.Tech./ M.Tech., or equivalent experience.
  • 4+ years of relevant experience.
  • Experience in verification of complex IPs/units and sub-systems.
  • Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
  • Expertise in Verilog.
  • Knowledge in SystemVerilog or similar HVL / UVM or VMM.

Nice to Have:

  • Experience in memory subsystem or network interconnect IP verification.
  • Debugging and analytical skills with sound scripting knowledge.
  • Good communication and excellent team player.

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]]> full-time senior onsite Verification, ASIC design, SystemVerilog, UVM, Verilog, Random stimulus, Functional coverage, Assertion-based verification Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Senior-IP-Design-Verification-Engineer---XBAR-IP_JR2019350?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru, KA Bengaluru KA IN 2026-06-08 4e1f470d-d2f Verification Engineer - GPU Fullchip As a Verification Engineer - GPU Fullchip at NVIDIA, you will be responsible for verifying the design and implementation of the industry's leading GPUs. This involves working with architects, designers, and pre and post silicon verification teams to ensure the correctness of the design. You will also be required to build reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.

Key responsibilities include:

  • Verifying the ASIC design, architecture, golden models and micro-architecture of the GPUs and full-chip level using advanced verification tools and methodologies.
  • Building reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.
  • Defining the verification scope, developing the verification infrastructure and verifying the correctness of the design.

Requirements include:

  • B.Tech./ M.Tech or equivalent experience with 2+ years of relevant experience.
  • Proficiency in Verilog and C.
  • Familiarity with OOPs concepts.
  • Hands-on experience in verification at Unit/Sub-system/SOC level.
  • Good understanding of computer architecture concepts.
  • Strong technical fundamentals with superior analytical skills and problem-solving skills.

Preferred qualifications include:

  • Prior experience in 3D graphics processing or processor verification.
  • C/C++ programming language experience.
  • Experience in scripting and tool development using Perl and Python.
  • Excellent debugging skills.
  • Good interpersonal and communication skills & dream to work as a great teammate.

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]]> full-time mid onsite Verilog, C, OOPs, Computer Architecture, Verification, 3D Graphics Processing, Processor Verification, C/C++, Perl, Python Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a technology company that specialises in designing and manufacturing graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---GPU-Fullchip_JR2019166?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru Bengaluru 2026-06-05 ec9c855b-aa6 Verification Engineer - GPU Fullchip As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs.

Your responsibilities will include verifying the ASIC design, architecture, golden models, and micro-architecture of the GPUs and full-chip level using advanced verification tools and methodologies.

You will build reusable bus functional models, traffic generators, monitors, checkers, and scoreboards following coverage-driven verification methodology.

You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure, and verify the correctness of the design.

Working with architects, designers, and pre- and post-silicon verification teams to accomplish your tasks.

We are looking for a skilled Verification Engineer with a strong background in digital design and verification.

Key qualifications include:

  • B.Tech./M.Tech or equivalent experience with 2+ years of relevant experience
  • Proficiency in Verilog and C
  • Familiarity with OOPs concepts
  • Hands-on experience in verification at Unit/Sub-system/SOC level
  • Good understanding of computer architecture concepts
  • Strong technical fundamentals with superior analytical skills and problem-solving skills
  • Knowledge of SystemVerilog or similar HVL is highly desirable
  • Experience in verification methodologies like UVM/VMM is highly desirable
  • Exposure to industry-standard verification tools for simulation and debug

Prior experience in 3D graphics processing or processor verification is a plus.

C/C++ programming language experience is also highly desirable.

Excellent debugging skills and good interpersonal and communication skills are essential for success in this role.

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]]> full-time mid onsite Verilog, C, OOPs, SystemVerilog, UVM/VMM, 3D graphics processing, processor verification, C/C++ Engineering Technology NVIDIA https://logos.yubhub.co/nvidia.com.png NVIDIA is a leading technology company that designs and manufactures graphics processing units (GPUs) and high-performance computing hardware. https://www.nvidia.com/ https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/Verification-Engineer---GPU-Fullchip_JR2019165?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply Bengaluru Bengaluru 2026-06-04