You are a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification. You thrive in a collaborative environment and have a keen eye for detail. Your technical expertise is complemented by your ability to communicate effectively and work well within a team. You are self-motivated and enthusiastic about technology and problem-solving. With a minimum of 5 years of experience in design verification, you have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You have a solid understanding of digital and mixed-signal designs and are eager to contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.
\nYour key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.
\nTo be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nAs a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.
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","url":"https://yubhub.co/jobs/job_24670b19-cee","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/digital-verification-sr-engineer/44408/92669904832","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["VCS/Verdi simulation tools","Formal verification tools (vc_formal)","UPF","UVM (Universal Verification Methodology)","SVA (SystemVerilog Assertion)","Perl/TCL/Python scripting"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:58.502Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"VCS/Verdi simulation tools, Formal verification tools (vc_formal), UPF, UVM (Universal Verification Methodology), SVA (SystemVerilog Assertion), Perl/TCL/Python scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_74dccfda-69a"},"title":"Digital Verification Sr Engineer","description":"Our organisation is seeking a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification to join our Digital and Verification Development team.
\nAs a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.
\nKey responsibilities include:\nPlanning tests, checklists, coverage, and assertion planning.\nCreating detailed verification environments from functional specifications.\nApplying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.\nWriting test cases, checkers, and coverage that implement the verification test plan.\nDebugging simulations, including those of real signals modeled using SystemVerilog for analog.\nPerforming RTL, GLS, and co-simulations and ensuring coverage closure.\nParticipating in technical reviews and contributing actively.\nProviding customer support with the bring-up of IP in customer simulation environments.\nFollowing and improving development processes to ensure high-quality output.
\nRequirements include:\nBS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.\n2+ years of experience in design verification.\nStrong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).\nKnowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.\nProficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nIdeal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written.\nA great team player, willing to support others.\nSelf-motivated and highly enthusiastic about technology and solving problems.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_74dccfda-69a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/digital-verification-sr-engineer/44408/92715864496","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["VCS/Verdi simulation tools","Formal verification tools (vc_formal)","UPF","UVM (Universal Verification Methodology)","SVA (SystemVerilog Assertion)","Perl/TCL/Python scripting"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:13.133Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"VCS/Verdi simulation tools, Formal verification tools (vc_formal), UPF, UVM (Universal Verification Methodology), SVA (SystemVerilog Assertion), Perl/TCL/Python scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f7fbae2c-358"},"title":"Senior Digital Verification Engineer","description":"Overview
\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nDate posted 02/24/2026
\nCategory EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
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\nWorkplace Resources, Sr Director
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\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nGet an idea of what your daily routine around the office can be like
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\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_f7fbae2c-358","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/asic-digital-design-sr-engineer/44408/92122114032","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","System Verilog","UVM","netlist simulations","industry-standard development and verification tools and methodologies","pre-silicon verification of complex PHY IPs, ASIC, or SoC designs"],"x-skills-preferred":["formal verification","System Verilog Assertions","code/functional coverage implementation and analysis","scripting languages such as Perl, TCL, and Shell scripting","high-speed interface protocols such as DDR and LPDDR"],"datePosted":"2026-03-09T11:04:17.847Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, System Verilog, UVM, netlist simulations, industry-standard development and verification tools and methodologies, pre-silicon verification of complex PHY IPs, ASIC, or SoC designs, formal verification, System Verilog Assertions, code/functional coverage implementation and analysis, scripting languages such as Perl, TCL, and Shell scripting, high-speed interface protocols such as DDR and LPDDR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_798ace47-ff9"},"title":"Staff Design Verification Engineer","description":"Overview
\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_798ace47-ff9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/staff-design-verification-engineer/44408/91940192160","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","System Verilog","UVM","netlist simulations","Perl","TCL","Shell scripting","formal verification","System Verilog Assertions","code/functional coverage analysis","high-speed interface protocols"],"x-skills-preferred":["RTL","digital design","verification","architecture","scripting languages","high-speed interface protocols"],"datePosted":"2026-03-09T11:04:17.561Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, System Verilog, UVM, netlist simulations, Perl, TCL, Shell scripting, formal verification, System Verilog Assertions, code/functional coverage analysis, high-speed interface protocols, RTL, digital design, verification, architecture, scripting languages, high-speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4a684387-7a2"},"title":"ASIC Digital Design, Sr Staff Engineer","description":"We are seeking a highly skilled ASIC Digital Design, Sr Staff Engineer to join our team. As a key member of our team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your primary focus will be on interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB.
\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_4a684387-7a2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/asic-digital-design-sr-staff-engineer/44408/91018694688","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["FPGA design and verification","Verilog and MATLAB","Python, C/C++, TCL","digital and mixed-signal circuit evaluation"],"x-skills-preferred":["test automation and data analytics","digital architecture and SerDes standards documentation"],"datePosted":"2026-03-06T07:24:11.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira, Porto, Portugal"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"FPGA design and verification, Verilog and MATLAB, Python, C/C++, TCL, digital and mixed-signal circuit evaluation, test automation and data analytics, digital architecture and SerDes standards documentation"}]}