The Air Dominance and Strike (AD&S) Chief Engineering Team is the technical authority for critical programs, responsible for owning the technical baseline, leading multi-disciplinary engineering teams, and delivering revolutionary airborne systems.

As the Chief Engineer, Next Generation ISR, you will own the technical development from concept refinement through detailed design, build, and flight test of new aircraft concepts.

Responsibilities:

• Lead Technical Execution: Own the technical baseline and lead a multi-disciplinary engineering team through detailed design, system integration, and verification.
• Oversee Prototype Build & Integration: Coordinate the fabrication and assembly of prototype and development articles, resolving engineering challenges.
• Drive the Test Campaign: Lead the engineering team in planning and executing a comprehensive test program.
• Manage System Design & Architecture: Guide the team through critical design trades, sub-system optimization, and interface management.
• Ensure Airworthiness & Safety: Serve as the technical authority for system safety and partner with test teams.
• Problem Solve & Troubleshoot: Act as the lead technical problem-solver, driving root cause analysis and implementing effective solutions.
• Prepare for Production: Partner with the manufacturing engineering team to ensure the design is production-ready.
• Support deployed flight test and demonstration activities.

Required Qualifications:

• Experience as a Chief Engineer, Integrated Product Team (IPT) Lead, or senior technical leader on a Low-Observable ISR and/or strike platform.
• Deep, hands-on experience leading a multi-disciplinary team through at least one major phase of aircraft EMD.
• Proven track record of taking a complex aircraft system from design into build and successful flight testing.
• Strong technical foundation across multiple core aircraft disciplines.
• Experience working on mission-critical DoD or advanced development aircraft programs.
• Bachelor’s degree in Aerospace, Mechanical, or a related engineering field.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications:

• Experience with developmental flight test, including test planning, risk management, and data analysis.
• Direct experience leading the prototype build of a UAS at Group 3 or above.
• Prior experience with DOW technology development organizations.
• Background in a "Skunk Works," "Phantom Works," or fast-paced startup environment.
• Experience with a wide range of manufacturing processes.
• A "player-coach" leadership style.
• An active Top Secret security clearance.

Salary Range: $191,000-$253,000 USD

Benefits: Anduril offers top-tier benefits for full-time employees, including comprehensive health, recovery, and other support programs.

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Responsibilities:

• Lead Technical Execution: Own the technical baseline and lead a multi-disciplinary engineering team through detailed design, system integration, and verification.
• Oversee Prototype Build & Integration: Coordinate the fabrication and assembly of prototype and development articles, resolving engineering challenges.
• Drive the Test Campaign: Lead the engineering team in planning and executing a comprehensive test program, including ground test, SIL/HIL integration, and developmental flight test.
• Manage System Design & Architecture: Guide the team through critical design trades, sub-system optimization, and interface management.
• Ensure Airworthiness & Safety: Serve as the technical authority for system safety and partner with test teams to achieve military flight releases.
• Problem Solve & Troubleshoot: Act as the lead technical problem-solver, driving root cause analysis and implementing effective solutions.
• Prepare for Production: Partner with the manufacturing engineering team to ensure the design is production-ready.
• Support deployed flight test and demonstration activities.

Requirements:

• Experience as a Chief Engineer, Integrated Product Team (IPT) Lead, or senior technical leader on a carrier-based Navy aircraft program.
• Deep, hands-on experience leading a multi-disciplinary team through at least one major phase of aircraft EMD.
• Proven track record of taking a complex aircraft system from design into build and successful flight testing.
• Strong technical foundation across multiple core aircraft disciplines.
• Bachelor’s degree in Aerospace, Mechanical, or a related engineering field.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications:

• Experience with developmental flight test, including test planning, risk management, and data analysis.
• Direct experience leading the prototype build of a UAS at Group 3 or above.
• Prior experience with DOW technology development organizations.
• Background in a "Skunk Works," "Phantom Works," or fast-paced startup environment.
• Experience with a wide range of manufacturing processes.
• A "player-coach" leadership style.
• An active Top Secret security clearance.

Salary Range: $191,000-$253,000 USD

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You are a seasoned expert in high-speed interface principles with a deep understanding of mixed-signal design and off-chip signaling. You have a proven track record of generating and supporting comprehensive documentation through written specifications and possess exceptional communication skills to convey these specifications within a design team and to external customers. You are adept at custom analog design, simulation, test planning, and verification of complex integrated circuit components. With at least 12 years of relevant experience, you have honed your skills in troubleshooting and debugging mixed-signal interfaces.

What You'll Be Doing:

• Understanding marketing and customer desires for Synopsys’ DDR and HBM PHY interface performance and functionality.
• Translating those desires into a set of product design features and functions.
• Guiding the custom analog designers.
• Optimizing the design for performance, power, and area.
• Interacting and communicating with design teams performing logical design, logical verification, analog circuit design and verification, and layout design.
• Supporting customers in their implementation of the product.
• Tracking industry developments through standards committees, representing Synopsys in these committees.

The Impact You Will Have:

• Drive the innovation and development of high-performance DDR and HBM PHY interfaces.
• Ensure Synopsys’ products meet and exceed market and customer expectations.
• Enhance the functionality and performance of Synopsys’ IP portfolio through cutting-edge design and optimization.
• Strengthen Synopsys’ presence and influence in standards committees and industry developments.
• Facilitate seamless integration and implementation of Synopsys products for customers worldwide.
• Contribute to the overall success and technological advancement of Synopsys.

What You'll Need:

• Deep understanding of high-speed interface principles, such as mixed-signal design and off-chip signaling.
• Expertise in generating and supporting documentation through written specifications.
• Proficiency in custom analog design, simulation, test planning, and verification of complex integrated circuit components.
• Strong troubleshooting and debugging skills for mixed-signal interfaces.
• Minimum of 12 years of related experience.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
• Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.

Requirements:

• B.Tech./ M.Tech or equivalent experience
• 4+ years of relevant experience
• Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
• Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
• Experience in developing and working in functional coverage based constrained random verification environments
• Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

• Excellent knowledge of PCIE protocol - Gen3 and above
• Good understanding of the system level architecture of PCIE/CXL-based designs
• Perl, Python or similar scripting and SW programming language experience
• Good debugging and analytical skills
• Good interpersonal skills & dream to work as a great teammate

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Key Responsibilities:

• Lead a team of verification engineers through full IP verification cycles
• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores
• Define test plans that cover corner cases, protocol compliance, and system-level interactions
• Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers
• Extract, analyze, and drive functional coverage and code coverage metrics to closure

Requirements:

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

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Responsibilities:

• Own the full innovation program lifecycle for DFX technologies
• Collaborate with engineering teams to compose architecture, workflows, and integration requirements
• Develop and manage project schedules, dependencies, and deliverables
• Participate in key build reviews and technical forums
• Act as primary liaison between DFX Engineering, Silicon Design, Software, Manufacturing, and datacenter/field operations teams
• Identify technical and schedule risks and develop mitigation strategies
• Provide clear status updates and communicate issues to leadership
• Gather takeaways across programs and institutionalize standard methodologies

Requirements:

• BS (Masters preferred) in Electrical Engineering, Computer Engineering, or a related field
• 6+ years of experience in technical program management with a strong focus on semiconductor development
• Deep, hands-on knowledge of the ASIC/SoC Build, Verification, and/or Bring Up/Validation/Productization flow
• Experience managing innovation programs or research-to-silicon initiatives
• Ability to handle rapid development cycles and constant change
• Proven ability to manage complex, ambiguous programs in a fast-paced environment
• Experience scripting and automating project management tasks; proficiency in Python preferred
• Self-motivated and proactive with demonstrated critical thinking and technical judgment and outstanding communication and organizational skills

Benefits:

• Highly competitive salaries
• Comprehensive benefits package
• Equity eligibility

Salary Range: 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5

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Widely considered to be one of the technology world's most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence, and Visualization.

The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables outstanding creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars.

Responsibilities

• Bare-metal Firmware development for NVLINK-C2C, validation, and debug of firmware and silicon bring-up for NVIDIA products.
• Collaborate in pre-silicon firmware development and testing to validate features.
• Drive silicon-bringup, feature enablement, and debug on silicon.
• Triage and resolve firmware issues observed during bringup.
• Debug hardware/firmware interaction issues, boot failures, training failures, and silicon issues; isolate root cause and drive fixes.
• Develop and maintain automation and AI-assisted flows to improve firmware development and verification.
• Work closely with system Software, RTL Design, DV, emulation, and post-silicon teams to unblock progress.
• Refine our Interface bring-up and validation strategy.

Requirements

• BS or MS EE degree with a focus in embedded systems (or equivalent experience).
• 6+ years of proven experience in low-level firmware design and verification in pre and post silicon.
• Must have hands-on experience debugging bare-metal firmware in RTL/SystemVerilog/UVM testbenches using Verdi or similar debug tools and correlating firmware execution with RTL behavior.
• Excellent RTL, digital debug skills, and understanding and coding skills in C/C++/Python.
• Experience with high-speed IO interfaces and understanding of data structures.
• Experience in developing firmware with AI agents would be beneficial.
• Proven understanding of PC systems, Windows OS, and Linux.
• Hands-on debugging skills. Able to break problems down based on first principles.
• Comfortable assuming different responsibilities over the life of a product.

Nice to Have

• Strong collaborative and interpersonal skills, with shown success in guiding and influencing others within a nuanced environment.
• Proven track record of leading chip bring-up activities.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.

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Responsibilities

• Participate in RTL design and verification of SysASIC and clock-related IPs
• Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions
• Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification
• Collaborate with cross-functional teams to improve design quality, verification coverage, and development efficiency
• Develop scripts, automation tools and AI agent to improve design and verification flows

Requirements

• Pursuing a BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Understanding of digital logic design and front-end ASIC development flow, including RTL design, simulation, synthesis, STA, lint, and CDC/RDC
• Familiarity with clocking concepts, such as clock gating, clock-domain crossing, reset synchronization, PLLs, and timing fundamentals
• Proficiency in Verilog and/or SystemVerilog; knowledge of UVM, SVA, or functional coverage is a plus
• Familiarity with formal verification concepts and tools, including property specification, assertion-based verification (SVA), equivalence checking, or formal property verification
• Experience with Python, Perl, Tcl, shell scripting, C, or C++ is preferred
• Familiarity with Linux development environments and common EDA tools
• Strong analytical and debugging skills, attention to detail, and willingness to learn
• Good English communication skills and the ability to work effectively in a global team

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The Networking Chip Design team in India is a new team that is growing rapidly.

Responsibilities:

• Understand all features of a given project and define project milestones based on internal roadmaps, assign them, and track them through an agile framework
• Define and develop system-level methodologies, tools, and IPs to build SOCs efficiently and scalably
• Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution
• Integrate all pieces for a given defined project milestone and deliver the model to relevant teams for further verification
• Have a good grasp of Perl, Python, or other industry-standard scripting languages

Requirements:

• BS/MS with 4+ years of practical semiconductor design and architecture experience building complex SoCs
• Firsthand experience and solid understanding of all phases of SOC development in multiple ASIC projects, including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure, and Physical design
• Exposure to design and verification tools (Verilog/SV, Cadence, or equivalent simulation tools, debug tools like Indago, GDB, etc.)
• C/C++ programming or Python or any other industry-standard scripting language experience desirable
• Experience working with software teams to tightly define the HW/SW interface
• Hands-on experience in successful tape-outs of multiple complex, high-volume SoCs in advanced process nodes
• Exposure to various Chip Design Functions to collaborate and solve complex cross-functional problems
• Excellent verbal and written communication skills to interact with cross-functional teams
• Good teamwork spirit and collaboration skills with team members

Benefits:

• Highly competitive salaries
• Comprehensive benefits package (visit www.nvidiabenefits.com/ for more information)

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As the Director of Applications Engineering, this role leads a team of Application Engineers who partner with Synopsys’ customers to successfully integrate leading-edge Interface IP (IIP) into ASIC SoCs/systems for next-generation products utilizing our PCIe/SERDES IPs.

You will be accountable for team execution, technical quality, customer success, and cross-functional alignment,hiring and developing talent, setting priorities, driving best practices, and owning escalations to ensure predictable, high-quality outcomes across multiple customer programs.

Responsibilities:

• Lead and develop a team of Application Engineers (hiring, onboarding, coaching, and performance management) to deliver excellent customer outcomes.
• Set priorities, allocate resources, and manage execution across multiple customer engagements and internal deliverables; establish operating rhythms and clear accountability.
• Own customer escalations for Interface IP integration, driving structured debug and resolution plans in partnership with R&D, Product, and Program teams.
• Define and standardize best practices for pre-silicon integration reviews, signoff checklists, and milestone-based customer engagement to improve predictability and quality.
• Lead AI initiatives to define and implement an AI-empowered flow that accelerates pre-silicon IP integration, debug, and customer engagement processes.
• Drive strong cross-functional collaboration and feedback loops to improve product quality, documentation, collateral, and enablement based on field learnings.
• Track and report on key metrics (e.g., milestone health, issue trends, response times, customer satisfaction) and continuously improving team processes.
• Stay current on relevant standards and market trends (e.g., PCIe, SERDES and related ecosystem requirements) and translate them into team readiness and customer guidance.
• Travel occasionally to support strategic customer engagements, executive reviews, and critical milestones.

The Impact You Will Have:

• Enhancing the usability and adoption of Synopsys' Interface IP products by providing expert technical support.
• Facilitating successful integration of IP into customer designs, contributing to their product development timelines.
• Improving customer satisfaction by resolving technical issues efficiently and effectively.
• Driving innovation by working with cutting-edge technologies and industry specifications.
• Strengthening Synopsys' market position through successful customer engagements and support.
• Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP.

Requirements:

• Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or related field.
• 20+ years of experience in SoC/ASIC development, applications engineering, design, verification, or silicon/IP bring-up; with a track record of customer-facing technical leadership.
• Strong project/program management skills with a focus on execution and problem-solving: build and drive plans, manage risks/dependencies, lead escalations, and communicate clearly with internal and external executives.
• Proven people leadership: set team vision and operating rhythm; hire, coach, and develop an inclusive, high-performing team; drive execution across multiple customer programs.
• Experience with high-speed protocols such as PCIe, Ethernet; Experience with High-Speed SerDes development or support is a plus.
• Technical depth in at least one domain: Front-End (RTL/SystemVerilog, CDC/RDC, lint, verification) and/or Back-End (synthesis, STA, place & route, signoff), or Analog/Mixed-Signal design and integration.
• Strong understanding of SoC tape-out flows and milestones (integration, verification signoff, timing closure, and handoff), and experience supporting customers through critical tape-out schedules.

Who You Are:

• Creative and results-oriented, capable of managing multiple tasks concurrently.
• Strong verbal and written communication skills in English.
• Ability to work collaboratively across teams to deliver solutions to customers.
• Strong analytical, reasoning, and problem-solving skills.
• Willingness to travel occasionally to support customer engagements.

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You will work with world-class systems architects, RAS experts, design teams, verification teams, validation teams, firmware teams, and software partners to define end-to-end hardware RAS features that improve system resiliency, observability, debuggability, error containment, recovery, and serviceability.

Responsibilities:

• Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
• Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
• Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
• Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
• Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
• Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other relevant modeling environments where applicable.
• Plan and review verification and validation strategies for RAS mechanisms, including error injection, recovery validation, coverage analysis, resiliency modeling, and cross-functional architecture reviews.
• Assist in failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
• Apply RAS architecture principles to high-reliability deployment environments, including space-aware and radiation-aware use cases where single-event effects, memory corruption, logic corruption, or cumulative radiation exposure may impact system reliability.
• Follow industry standards and best practices related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing.
• Patent novel hardware architecture techniques that improve system resiliency, observability, serviceability, and recovery.

Requirements:

• MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
• At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
• Strong understanding of Reliability, Availability, and Serviceability (RAS) in the SoC context, including fault detection, correction, containment, telemetry, recovery, degradation modes, debug visibility, and serviceability mechanisms.
• Experience defining and driving hardware architecture features through the full development lifecycle, including architecture definition, design implementation, verification planning, validation, debug, and production readiness.
• Strong understanding of overall SoC architecture and the ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.
• Meaningful industry expertise in one or more SoC architecture areas such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure.
• Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology.
• Familiarity with radiation effects, space operation, or other high-reliability deployment environments is strongly valued, including understanding how hardware architecture can mitigate single-event effects and related reliability risks.
• Excellent analytical, written, and verbal interpersonal skills with the ability to work effectively across architecture, design, verification, firmware, software, validation, and customer-facing teams.

Benefits:

• Equity
• Benefits

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As a Capital Markets, FX Specialist, you will partner with Engineering, Data Science, Product, and Finance to maintain operational rigor today while shaping long-term pricing and hedging strategies.

Responsibilities

• Monitor FX risks, execute trades, reconcile position, and attribute costs
• Build automated risk monitors, alerting tools, and analytical models using SQL and quantitative coding to enable observability and minimize operational toil
• Collaborate with Product and Engineering to guide the design and scaling of core FX infrastructure, trade execution flows, and liquidity provider integrations
• Develop risk-based FX pricing methodologies across products and currency pairs, factoring in volatility, transaction costs, netting efficiency, and embedded optionality like rate guarantees.
• Design hedging strategies to mitigate FX risks on financial statements while maintaining robust policies, controls, and operational runbooks

Requirements

• 5+ years in FX, market risk, trading, quantitative research, or treasury operations, with working knowledge of FX market structure and instruments
• Proficiency in Python and SQL to build analytics and tools, backed by a strong foundation in statistics, time series, and risk measurement
• Exceptional attention to detail and a proven ability to turn complex, imperfect datasets into clear insights
• Practical experience using AI tools to streamline analysis and automation, paired with a critical eye for model validation and verification
• Strong cross-functional collaboration skills, with the ability to turn complex data into clear narratives and escalate issues concisely under time pressure
• Bachelor's degree

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Your responsibilities will include:

• Owning the pre-sales technical lifecycle for Interface IP opportunities
• Working directly with customer SoC architects and design teams to understand requirements and constraints
• Leading technical evaluations and IP selection processes
• Partnering with Sales/Account teams to shape win strategies and qualify opportunities
• Driving customer-facing technical engagements such as architecture workshops and design reviews
• Supporting competitive situations with strong technical differentiation
• Translating customer issues into actionable engineering requests and ensuring timely resolution

You will need:

• Bachelor's degree in Electrical Engineering, Electronics, or related field with 12+ years of experience
• Strong hands-on background in ASIC/SoC design and/or verification
• Technical expertise in at least one major Interface IP domain such as SerDes, PCIe, DDR, USB, MIPI, D2D, or Ethernet
• Proven experience in a customer-facing pre-sales technical role
• Strong communication skills in Korean and English (written and verbal)

The impact you will have:

• Enabling customers to de-risk SoC programs by selecting the right IP early
• Accelerating IP adoption and customer success across Korea
• Increasing technical win rates by driving high-quality discovery and evaluation success
• Reducing escalations and project friction by proactively identifying gaps
• Strengthening Synopsys credibility with customer engineering teams and executives

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The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The salary range for this role is $176K - $224K per year, with generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits include:

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees
• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI's Forward Deployed Engineering (FDE) team turns research breakthroughs into production-grade systems. We embed deeply with customers to solve high-leverage problems and act as the delivery engine for our most complex large-scale engagements.

About the Role

As a Technical Deployment Lead (TDL), you will define how OpenAI delivers complex systems to Semiconductor customers. You will own how solutions are scoped, built, shipped, and adopted across high-value engineering workflows such as RTL design, verification, and physical implementation. You'll translate business outcomes into a technical plan, run day-to-day execution across FDEs, Researchers, and Customer Engineers, and partner with customer teams to ensure delivery supports their goals.

You will focus on the semiconductor vertical to deploy next-generation AI capabilities. You will own delivery end-to-end: embedding with customers to map workflows and success criteria, ensuring components ship on time, and leading readiness and change management for adoption. You'll track progress, manage dependencies, make sequencing decisions, and drive 0→1 prototypes through MVP and scale.

Responsibilities

• Own the technical delivery plan for multiple interdependent work streams, translating customer objectives into a roadmap with milestones, dependencies, and acceptance criteria.
• Run day-to-day engineering execution by tracking and driving delivery across OpenAI FDE and customer teams.
• Embed with Semiconductor customer teams to land production deployments and drive adoption.
• Shape production deployments that integrate with customer infrastructure, data systems, and engineering toolchains, including export-controlled environments.
• Partner with Product and Research so platform components and research work streams land in time to support deployment goals.
• Codify solution patterns and evals.
• Own value cases and ROI.
• Help define how OpenAI engages Semiconductor customers.

Requirements

• Bring 7+ years of customer-facing technical delivery leadership.
• Have deep expertise in Semiconductor workflows, including RTL design, verification, EDA tooling, and physical implementation.
• Track record of successfully leading large, complex, high-stakes customer engagements where customer outcomes depended on tight coordination and fast decision making, ideally involving AI.
• Excel in high ambiguity environments.
• Move fluidly between system level understanding and execution level detail.
• Think strategically and pattern-match.
• Have strong technical fluency and sharp sequencing instincts.
• Have shipped AI/LLM systems.

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As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

Responsibilities

• Work in a combined design and verification team which develops some of the switch silicon core units.
• Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
• Build reference models, verify and simulate chip blocks/entities according to specifications.
• Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW.

Requirements

• B.Sc. in Electrical Engineering or Computer Engineering.
• 4+ years of experience in RTL design or RTL verification.
• Previous experience in networking - an advantage.
• A team player with good communication and interpersonal skills.

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Key responsibilities include:

• Owning execution, resource planning, and delivery from architecture through silicon validation and customer deployment.
• Driving design and verification excellence through robust methodologies, quality standards, and coverage closure.
• Partnering across architecture, analog, physical design, firmware, and applications engineering to ensure successful product releases.
• Developing technical talent, building leadership capability, and fostering a culture of innovation and accountability.

The impact you will have:

• Delivering industry-leading Interface IP enabling AI, cloud, networking, and next-generation SoC platforms.
• Shaping technical direction, product quality, and engineering best practices across multiple product lines.
• Improving engineering efficiency through scalable design, verification, and automation methodologies.
• Influencing product strategy and customer success through strong technical leadership.
• Building and mentoring future technical and people leaders within Synopsys.

Requirements:

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of related experience in ASIC design and verification experience.
• Strong expertise in RTL design, SystemVerilog, UVM, and modern EDA development environments.
• Experience delivering high-performance Interface IP products from concept through production.
• Proven success building teams, driving execution, and making sound technical decisions in complex environments.

Rewards and Benefits: Synopsys offers a comprehensive rewards package that includes competitive compensation, health and wellness programs, retirement benefits, and professional development opportunities.

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Potential NCG opportunities in this field include:

• IP and SoC Level Design and Verification (including multimedia IP)
• Custom SoC Design and Verification
• Networking Chip Design and Verification
• Architectural Power and Energy-Efficiency Modeling
• DFT
• Formal Verification
• Post-Silicon Validation

To be considered, you should:

• Be expected to graduate in 2027 with a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field
• Have course or internship experience related to areas such as digital systems, digital design, VLSI design, RTL design, chip blueprint, power and performance optimization, testbench creation, computer architecture, computer arithmetic, object-oriented programming, CMOS transistors, circuits, infrastructure development, architectural tradeoff analysis, power and noise analysis, silicon instrumentation and measurement, CAD and physical design methodologies, chop floorplan, power/clock distribution, packaging, P&R and timing closure, performance, verification, and emulation methodology
• Be familiar with hardware verification methodologies, particularly UVM (Universal Verification Methodology), and have a working knowledge of formal verification tools
• Possess fundamental knowledge of hardware and board-level design, such as power integrity (PI), signal integrity (SI), and PCB-level design

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Job Description:

As a 2027 New College Graduate: GPU Architecture Engineering, you will have the opportunity to work on various projects, including:

• GPU Architecture Modeling and Performance Analysis: Conduct quantitative studies of current and future GPU architectures; develop performance and functional models; analyze graphics and parallel-compute pipelines; identify bottlenecks and propose architectural improvements.
• SoC Performance Simulation and Workload Analysis: Build and enhance performance simulators and modeling frameworks; capture, replay, and profile complex real-world application workloads; evaluate current and next-generation SoC performance across use cases.
• GPU/System Functional Validation Platform Development: Develop pre-silicon programming and test environments for next-generation GPU and system features; work across architecture, hardware, and software teams throughout the chip development lifecycle.
• GPU Functional Verification and Test Generation: Create directed and constrained-random test plans with strong coverage; generate, run, and debug tests across functional simulators, unit- and full-chip RTL, emulators, and post-silicon platforms.
• GPU and Memory-System Architecture Exploration: Explore novel GPU composition, processing, storage, and memory-system capabilities; partner with architects to validate new features and improve performance, functionality, and test coverage.
• Performance Profiling, Debugging, and Optimization: Profile system and application behavior, diagnose GPU/SoC performance bottlenecks, and develop tools and methodologies that improve analysis efficiency and overall application performance.
• Simulation, Emulation, and Silicon Bring-Up: Validate designs across multiple stages,from architectural models and RTL simulation to emulation and real silicon,and debug functional or performance issues before and after product release.

Requirements:

• Expected to graduate in 2027 with a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field
• Computer Architecture, GPU Architecture, Microprocessor Design, or Memory Systems
• C/C++, Python, Linux, and object-oriented software development
• GPU programming and debugging, including CUDA
• Performance/functional modeling, profiling, trace-driven or execution-driven simulation
• Computer systems, compilers, assembly language, and system modeling tools such as SystemC
• ASIC design, verification, RTL, random-test development, or post-silicon validation
• Deep learning model development or AI workload optimization

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Responsibilities:

• Review verification submissions for compliance, conduct KYC checks, verify brand legitimacy, and analyze digital footprints to prevent fraud.
• Perform QA on AI-generated decisions and agent-resolved submissions to ensure accuracy, consistency, and compliance with verification standards.
• Analyze verification processes and appeals to detect patterns, optimize workflows, and mitigate risks.
• Handle escalations for complex verification cases, working with internal teams to resolve issues efficiently.
• Collaborate with internal teams to streamline onboarding, improve compliance enforcement, and align on best practices.
• Maintain process documentation, contribute to best practices, and support team efficiency.
• Support a positive, high-performing team culture by sharing insights and collaborating with colleagues.
• Provide prompt, high-quality support via email, Slack, and ServiceNow.
• Investigate verification issues, assess inefficiencies, and develop solutions to improve workflows.
• Manage high-volume inquiries, meet SLAs, and effectively balance multiple priorities.
• Stay informed on compliance and industry changes, proactively refining workflows and compliance strategies.
• Monitor onboarding progress, troubleshoot verification issues, and guide internal teams & customers to ensure a seamless experience.

Qualifications:

• Ability to work effectively in a remote environment, demonstrating strong time management, self-discipline, and communication skills.
• Availability to work Monday-Friday, 8:00 AM – 5:00 PM CT or 9:00 AM – 6:00 PM CT
• 1-2 years of experience in an operations and customer-facing role, with exposure to cross-functional collaboration.
• Strong ability to prioritize tasks, manage workloads efficiently, and meet SLAs.
• Excellent verbal and written communication skills, with strong attention to detail in document review and risk assessment.
• A customer-centric mindset, with a commitment to delivering high-quality support and ensuring a seamless experience.
• Problem-solving mindset, with the ability to assess situations, think critically, and make sound decisions.
• Quick adaptability to new systems, workflows, and evolving business needs.
• A collaborative team mindset, with the ability to work both independently and cross-functionally.
• Self-motivated, receptive to feedback, and committed to continuous improvement.
• Willingness to take on new challenges and grow with evolving business needs

Benefits: Working at Twilio offers many benefits, including competitive pay, generous time off, ample parental and wellness leave, healthcare, a retirement savings program, and much more.

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Your responsibilities will include:

• Providing technical support to customers integrating DesignWare USB Mixed Signal PHY IP from initial integration through silicon bring-up and debug
• Troubleshooting customer issues across synthesis, static timing analysis, design-for-test, and clock domain crossing in USB PHY and SoC integration contexts
• Guiding customers through USB 2.0, USB 3.x, and Type-C implementation considerations and design tradeoffs, and helping define bring-up and debug plans that reduce time-to-silicon
• Collaborating closely with the Korea AE team and Synopsys R&D and product teams to escalate complex issues, drive root-cause analysis, and ensure timely closure during critical milestones
• Contributing to customer support coverage for other high-speed interface PHY IP in collaboration with colleagues, leveraging similar integration and debug fundamentals
• Delivering technical presentations and integration best practices to customer engineering teams during design reviews and key program checkpoints
• Traveling occasionally to customer sites across Korea and the region to support critical milestones

The impact you will have:

• Enabling customer success on high-stakes tapeouts by resolving USB PHY integration issues that would otherwise delay schedules
• Reducing time-to-silicon by providing clear, actionable guidance during integration, constraints closure, and silicon bring-up
• Building deep technical relationships with leading semiconductor companies in Korea as their trusted advisor
• Shaping future IP releases by channeling real customer pain points back into the product team
• Expanding Synopsys footprint in customer accounts through technical depth, responsiveness, and cross-team collaboration

To be successful in this role, you will need:

• A Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10 to 20+ years of ASIC design, verification, or SoC integration experience
• Strong working knowledge of synthesis, static timing analysis, design-for-test, and clock domain crossing
• Ability to work independently and drive ambiguous, customer-driven issues to resolution
• Excellent communication skills in Korean and English, able to explain complex concepts clearly
• USB 2.0, USB 3.x, Type-C, or USB PHY integration experience is a strong plus
• Broader high-speed interface background is a plus and helps with collaborative cross-IP support coverage
• Willingness to travel occasionally within Korea and the region

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As we extend our project management team for High-Performance Computing (HPC) developments, we have a great job opportunity for you. In this interesting and challenging position as a project engineering manager (PEM) you will be responsible for the planning and execution of development projects which deliver leading-edge products for HPC applications.

You are a seasoned engineering professional with a passion for innovation and excellence. With a solid background in project management and engineering (at least 6 years of experience), you thrive in dynamic environments and excel at leading cross-functional teams to success. Your analytical mindset allows you to navigate complex challenges, and your communication skills ensure that all stakeholders are aligned and informed.

What You'll Be Doing:

• Collaborating with cross-functional teams to define project requirements, scope, and objectives;
• Developing detailed project plans, including timelines, resource allocation, and risk management strategies;
• Monitoring project progress and performance, identifying potential issues, and implementing corrective actions as needed;
• Communicating project status, updates, and milestones to stakeholders, ensuring transparency and alignment;
• Representing R&D on customer relationships, tracking execution to plan, aligning with senior leadership of team on mitigation and escalation management;
• Mentoring and guiding team members, fostering a collaborative and innovative work environment.

The Impact You Will Have:

• Driving the successful execution of engineering projects, contributing to Synopsys' reputation for excellence and innovation;
• Enhancing the efficiency and effectiveness of project management processes, leading to improved project outcomes;
• Facilitating cross-functional collaboration, ensuring that all teams are working towards common goals;
• Providing leadership and mentorship to team members, fostering their professional growth and development;
• Ensuring that projects are delivered on time, within scope, and within budget, contributing to the overall success of the organization;
• Identifying opportunities for process improvements and implementing best practices to enhance project delivery.

What You'll Need:

• Excellent communication skills, both oral and written, ability to summarize key points in succinct and objective way;
• A background in ASIC Design/Verification/Implementation - preferably digital;
• Excellent organizational and time-management skills, with the ability to manage multiple projects simultaneously;
• Proficiency in project management tools and software, MS Project preferred, PMP certification an advantage;
• Knowledge/experience of developing or using 3rd party IP - preferably digital;
• Proven experience in project management, with a track record of successfully leading semiconductor engineering projects, ideally in ASIC Design/verification;
• Bachelor's or master's degree in engineering or a related field;
• Strong knowledge of engineering principles and practices.

Who You Are:

• A natural leader with strong interpersonal and communication skills.
• A strategic thinker with excellent problem-solving abilities.
• Detail-oriented and highly organized.
• Proactive and able to work independently with minimal supervision.
• Collaborative and able to work effectively in a team environment.

The Team You'll Be A Part Of:

You will be part of a dynamic and innovative team focused on delivering cutting-edge engineering projects. Our team is dedicated to excellence and continuous improvement, and we work collaboratively to achieve our goals. We value diversity, creativity, and a strong work ethic, and we are committed to fostering an inclusive and supportive work environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Responsibilities:

• Review verification submissions for compliance, conduct KYC checks, verify brand legitimacy, and analyze digital footprints to prevent fraud.
• Perform QA on AI-generated decisions and agent-resolved submissions to ensure accuracy, consistency, and compliance with verification standards.
• Analyze verification processes and appeals to detect patterns, optimize workflows, and mitigate risks.
• Handle escalations for complex verification cases, working with internal teams to resolve issues efficiently.
• Collaborate with internal teams to streamline onboarding, improve compliance enforcement, and align on best practices.
• Maintain process documentation, contribute to best practices, and support team efficiency.
• Support a positive, high-performing team culture by sharing insights and collaborating with colleagues.
• Provide prompt, high-quality support via email, Slack, and ServiceNow.
• Investigate verification issues, assess inefficiencies, and develop solutions to improve workflows.
• Manage high-volume inquiries, meet SLAs, and effectively balance multiple priorities.
• Stay informed on compliance and industry changes, proactively refining workflows and compliance strategies.
• Monitor onboarding progress, troubleshoot verification issues, and guide internal teams & customers to ensure a seamless experience.

Qualifications:

• Ability to work effectively in a remote environment, demonstrating strong time management, self-discipline, and communication skills.
• Availability to work Monday-Friday, 8:00 AM – 5:00 PM CT or 9:00 AM – 6:00 PM CT
• 1-2 years of experience in an operations and customer facing role, with exposure to cross-functional collaboration.
• Strong ability to prioritize tasks, manage workloads efficiently, and meet SLAs.
• Excellent verbal and written communication skills, with strong attention to detail in document review and risk assessment.
• A customer-centric mindset, with a commitment to delivering high-quality support and ensuring a seamless experience.
• Problem-solving mindset, with the ability to assess situations, think critically, and make sound decisions.
• Quick adaptability to new systems, workflows, and evolving business needs.
• A collaborative team mindset, with the ability to work both independently and cross-functionally.
• Self-motivated, receptive to feedback, and committed to continuous improvement.
• Willingness to take on new challenges and grow with evolving business needs

Location: Remote - Colombia

What We Offer: Working at Twilio offers many benefits, including competitive pay, generous time off, ample parental and wellness leave, healthcare, a retirement savings program, and much more.

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You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers. You will enjoy working in a meaningful, growing environment where you make a huge impact in a technology-focused company.

Responsibilities:

• Full-Chip Verification & Execution: Own system-level features by defining verification plans and driving the end-to-end execution.
• System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance.
• Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC.
• AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks.

Requirements:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 3-5 years of experience in Verification or HW simulation.
• Strong debugging, problem-solving and analytical skills.
• Innovation Mindset - a proactive approach to adopting new methodologies and coding tools to solve complex challenges.
• A team player with good communication and interpersonal skills.

Nice to Have:

• Prior verification experience of SoC.
• Knowledge in network flows and protocols.

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The ideal candidate will have experience with full-stack development, from verifying scenarios at SW simulator level to getting the overall end-to-end test working on silicon with a full SW stack. They will also have strong verification fundamentals, experience with Verilog, SystemVerilog, C/C++, and possess strong debugging skills.

Key responsibilities:

• Work on NVIDIA's next-generation SOC
• Verify CPU, GPU, high-speed interfaces, DFD, and horizontal functions
• Develop and implement test plans collaborating with SOC architects
• Work on developing verification testbenches, flows, and automation

Requirements:

• Experience with full-stack development
• Strong verification fundamentals
• Experience with Verilog, SystemVerilog, C/C++
• Bachelors/Masters, or equivalent experience, in Computer Science or Electrical Engineering with 3+ years of industry experience

Benefits:

• Competitive salaries
• Generous benefits package

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Your role will involve:

• Analyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.
• Establishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.
• Collaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
• Assessing new tool releases and methodology capabilities, coordinating their integration into project environments.
• Improving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.

We are seeking a professional with:

• A Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 3+ years of proven experience in ASIC or SoC RTL design or design-methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Knowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• The ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

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Key Responsibilities:

• Foster quality, automation, and scalability
• Oversee development and optimization of APIs, tools, and libraries, and maintain OS verification infrastructure
• Enhance automation workflows for rapid and reliable SDK releases and drive CI/CD pipeline evolution
• Collaborate with hardware, firmware, DevOps, and software teams
• Align on verification methodologies and infrastructure improvements
• Guide design reviews and architecture discussions, defining best practices for verification excellence

Requirements:

• B.Sc. or higher in Computer Science, Software, Electrical Engineering, or similar
• 3+ years of experience in software development or verification
• Strong Python coding skills
• Experience with large-scale verification or automation frameworks
• Strong networking background (L2/L3)
• Solid Linux knowledge
• Proficiency with CI/CD & DevOps tools (Jenkins, Git, Gerrit, Docker)
• Excellent communication and organization skills, with the ability to align multiple teams and deliver results

Preferred Qualifications:

• Background in scalable or distributed systems
• Experience with multi-node testing or performance validation
• Strong debugging skills, especially for concurrency issues
• Deep understanding of networking and system architecture

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You will define and execute product and go-to-market strategy for Synopsys' industry-leading AI portfolio.

Key responsibilities include:

• Defining and executing product and go-to-market strategy for Synopsys' industry-leading AI portfolio.
• Assimilating customer requirements, technology trends, and competitive intelligence to shape product roadmaps.
• Driving integrated marketing strategies encompassing thought leadership, demand generation, and customer-focused campaigns.
• Developing and executing innovative go-to-market plans, including packaging, pricing, and new business models.
• Engaging directly with customers to understand requirements, anticipate market shifts, and identify future design trends.
• Building business cases for future development, negotiating product line priorities, and guiding technology roadmaps.
• Exploring inorganic growth opportunities such as M&A and partnerships and supporting technology due diligence.
• Collaborating with cross-functional stakeholders to foster ecosystem partnerships and drive product life cycle management.
• Owning messaging and positioning for digital implementation optimization and signoff timing analysis domains.
• Training, motivating, and guiding the sales force to advance the AI portfolio's market presence.
• Developing and tracking the sales pipeline to meet financial targets and strategic objectives.
• Performing financial analysis and revenue forecasting to align business strategy and inform executive decisions.
• Serving as a recognized expert and role model in the field, representing Synopsys internally and externally.

The Impact You Will Have:

• Shape the future of AI-driven design automation and semiconductor innovation on a global scale.
• Drive the evolution and success of Synopsys' AI portfolio, influencing industry standards and best practices.
• Accelerate customer outcomes by delivering cutting-edge products that address real-world challenges.
• Enhance Synopsys' market share and financial performance through strategic product leadership.
• Foster a culture of collaboration, innovation, and continuous improvement across multi-disciplinary teams.
• Establish Synopsys as a thought leader in AI for EDA and semiconductor industries.
• Enable rapid adoption of new AI technologies through compelling go-to-market strategies.
• Expand the company's reach via strategic partnerships, acquisitions, and ecosystem development.
• Mentor and develop future leaders in product management and AI technology.
• Elevate customer satisfaction through tailored solutions and proactive engagement.

What You'll Need:

• 15+ years of relevant experience in product management, ideally within EDA or semiconductor industries.
• Bachelor's degree in electrical engineering (BS EE) or equivalent technical discipline.
• Expertise in Generative AI technologies, including frameworks, foundation models, training, and inferencing methodologies.
• Proven experience in one or more domains: Digital Design/Implementation, Verification, Signoff, Analog Design.
• Demonstrated ability to negotiate, influence, and lead in a matrixed organization.
• Successful track record in launching, managing, and growing technology products.
• Exceptional verbal and written communication and public speaking skills.
• Experience with financial analysis, revenue forecasting, and strategic planning.
• Understanding of go-to-market planning, packaging, pricing, and product lifecycle management.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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This team helps build new and innovative products tailored to NVIDIA's world-changing solutions for data center, autonomous vehicles, deep learning, and gaming.

Responsibilities:

• Developing architecture and micro-architecture to improve the state-of-the-art in memory system optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.
• Performance modeling and simulation of features to improve memory system efficiency.
• Implementing and maintaining high-level performance and functional models.
• Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.
• Debugging performance and functional issues with high-level models, RTL simulation, and silicon.
• Working with various cross-functional teams like ASIC design and verification, software, product development team, marketing in developing the comprehensive solution.

Requirements:

• Master's degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field (or the equivalent experience).
• 4+ years of meaningful work experience in SoC Architecture and development specifically in one or more domains of MMU and address translation, memory caching, interconnects, and DRAM controllers.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product-oriented, distributed team.

Nice to have:

• Significant understanding of Performance (Bandwidth and Latency), Quality of Service and its impact on the overall system performance.
• Practical experience in developing and using Performance model for early Architecture analysis.

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Anthropic is building custom silicon for Claude. The hardware our models run on is one of the most direct levers we have on capability, cost, and reliability , and we've decided to take design authority over it ourselves.

We're looking for a Technical Program Manager to own end-to-end execution of our silicon, from architecture definition through tapeout, first-silicon bring-up, and production ramp. You'll be working alongside a small group of domain experts across front-end design, verification, physical design, DFT, analog/mixed-signal, foundry, and packaging. There is no process to inherit , you'll build the execution machinery this program runs on.

This is a partner-heavy program by design. You'll drive a portfolio of external engagements , ASIC design services, IP vendors, foundry, and OSAT. You should have shipped chips before, know what a realistic silicon schedule looks like and its failure modes, and be comfortable making consequential program calls without a large organization behind you. And because this is Anthropic, you'll have Claude as a collaborator , we expect the TPMs on this team to push hard on what AI-assisted program management can look like.

Key responsibilities

• Own the integrated silicon program plan , architecture closure, RTL freeze, DV milestones, IP delivery, PD closure, DFT, tapeout, and post-silicon bring-up.

• Drive external partner execution across ASIC design partners, IP vendors, foundry, and packaging/test.

• Run technology and IP selection as a program: track candidate vendors and options, drive evaluations to a decision, and land the build / buy / license calls with engineering leadership.

• Build the execution mechanisms a silicon team needs , milestone definitions, risk and dependency tracking, design reviews, release management, exec reporting , and keep them lightweight enough that engineers actually use them.

• Manage the interface between silicon and its consumers: hardware systems for package/board/bring-up, and inference/kernels/compiler teams for hardware-software co-design, so trade-offs land as coordinated decisions rather than late surprises.

• Own the post-silicon program , bring-up planning, ATE/test handoff, sample distribution, validation, and the path to production readiness.

• Develop and share AI-assisted approaches to program management , schedule and dependency modeling, spec and milestone consistency checking, partner-deliverable tracking, status synthesis.

Minimum qualifications

• 8+ years in silicon/SoC program management, chip lead, or an equivalent role that owned a chip schedule end to end.

• Direct ownership of at least one program that taped out and reached production, with milestones you can speak to in detail , including where it slipped and what you did about it.

• Working technical fluency across the silicon lifecycle , front-end, DV, PD, DFT, foundry, packaging.

• Experience running external silicon partners , ASIC houses, IP vendors, foundry, or OSAT , including SOW scoping, delivery tracking, and escalation.

• Track record of building program mechanisms from scratch on an ambiguous, fast-moving effort.

• Strong written communication , plans, reviews, and exec updates that many teams depend on.

• Comfort operating with high autonomy and limited process on a highly dynamic program.

Preferred qualifications

• Experience on ML accelerators, high-performance compute, networking, or other large, high-bandwidth SoCs at advanced process nodes.

• Experience on a first-generation or early silicon program, including standing up flows, methodology, or vendor relationships from nothing.

• Experience with both partner-executed and fully in-house programs, and a view on the trade-offs between them.

• Prior hands-on engineering background in one or more silicon domains (design, DV, PD, DFT, or SI/PI).

• Familiarity with the chip-package-system interface and co-design with a hardware systems team.

• Experience with hardware-software co-design programs , working directly with compiler, kernel, or runtime teams.

• Practical experience using AI tools in your own workflow, and clear ideas about where they help and where they don't.

• BS/MS in EE, CE, CS, or a related field, or equivalent experience.

The annual compensation range for this role is $365,000-$435,000 USD.

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Responsibilities:

• Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and develop creative solutions, including building frameworks, optimizing regressions, and accelerating simulation throughput.
• Multi-Language Development: Work with a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting), writing code and solving problems across various layers.
• System-Level Debug & Analysis: Understand chip micro-architecture and features, investigate and resolve cross-block issues to ensure feature correctness and compliance.
• AI-Enhanced Development: Leverage cutting-edge AI coding tools and frameworks for verification and infrastructure challenges.
• Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware, and all units inside the NIC.

Requirements:

• B.Sc. in Electrical Engineering or Computer Engineering with high scores or equivalent experience.
• 8+ years of experience in verification, HW simulation, or infrastructure development for silicon projects.
• Proven ability to enhance and scale verification systems, including regression frameworks, simulation performance, tooling, and flow automation.
• Creativity, proactivity, and innovation mindset with a proactive approach to adopting new methodologies and coding tools.
• Strong debugging, problem-solving, and analytical skills.
• Good communication and interpersonal skills.

Preferred Qualifications:

• Experience with AI tools for verification automation or infrastructure acceleration.
• Experience working in multi-language environments.

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You’ll be part of a forward-thinking team dedicated to advancing the tools and frameworks that are used to develop the cutting-edge networking adapter technologies.

Your role will be to drive the success of NVIDIA's current and upcoming networking devices by working across various platforms, including C++ object-oriented simulation, verification frameworks and C layer interfacing hardware and firmware.

Responsibilities

• Develop a network adapter simulator that will be used for both development and testing of pre-silicon networking features
• Take part in implementing and assimilating frameworks for Design and Verification both for real-time and simulator environments
• Addressing and solving automation and performance challenges
• Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows

Requirements

• B.Sc./M.Sc. in Computer Science or Computer Engineering
• 5+ years of proven experience with verification and testing methodologies
• Good understanding of the Linux operating system and computer structure
• Solid knowledge in C++ and Object-Oriented Programming
• Strong multi-disciplinary capabilities and ability to work with wide entities – chip design, verification, FW, SW, and architecture
• Ability to lead feature development and take full ownership of tasks from A to Z
• Outstanding teammate, strong interpersonal skills, and self-learning ability

Nice to Have

• Experience in simulator development for real-time systems
• Background in Embedded C programming
• Knowledge in networking protocols and scripting languages
• Strong interests towards groundbreaking technologies and ability to take initiatives and drive them across multiple functional teams

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What You'll Be Doing:

• Work in a design/verification team which develops core units within the Switch silicon as a dynamic verification or RTL design engineer.
• Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
• Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
• RTL synthesis, timing, supporting verification, and silicon post TO activities.
• Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

What We Need To See:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in chip design.
• Knowledge in network protocols and/or HPC and distributed calculations - advantage.
• A team player with good communication and interpersonal skills.

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You will work in a combined design and verification team which develops some of the switch silicon core units.

Your responsibilities will include:

• Building reference models, verifying and simulating chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
• Working closely with multiple teams within organisations such as Architecture, Micro-Architecture, and FW.

To be successful in this role, you will need:

• A B.Sc. in Electrical/Computer Engineering or equivalent experience.
• 5+ years of experience in Verification or RTL design.
• Knowledge in network protocols and/or HPC.
• Good communication and interpersonal skills.

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Responsibilities:

• Work in a Full Chip verification team integrating and verifying Nvidia's Switch products at system level.
• Collaborate closely with multiple teams within organisations such as Architecture, u-arch, Firmware, and all units inside the switch.
• Drive the FullChip verification execution, including staging plans and project deliveries.

Requirements:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in verification, with an advantage for FullChip/SoC.
• Knowledge in network protocols is an advantage.
• Deep knowledge in Specman is an advantage.
• A team player with good communication and interpersonal skills.

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Job Description

As a Senior Director R&D Engineering (Interface PHY / Ethernet SerDes) at Synopsys, you will lead an R&D organization developing 112G/224G Ethernet SerDes and Interface PHY IP for AI/HPC, networking, and data center markets.

Key Responsibilities:

• Lead an R&D organization developing 112G/224G Ethernet SerDes and Interface PHY IP for AI/HPC, networking, and data center markets
• Own execution planning, staffing, and delivery commitments across multiple concurrent programs and customer milestones
• Drive technical alignment across architecture, analog, digital, verification, firmware, and customer support teams
• Partner with product and program management to translate roadmap priorities into executable engineering plans
• Define processes for milestone reviews, risk management, and decision-making that keep programs moving
• Lead resolution of customer-critical issues from triage through root-cause analysis and corrective action
• Develop engineering talent through coaching, performance management, hiring, and succession planning

The Impact You Will Have:

• Deliver production-quality Ethernet SerDes IP that enables customers to meet performance and time-to-market goals
• Build execution discipline that consistently meets delivery commitments without burning out the team
• Establish quality practices that reduce post-release issues and customer escalations
• Develop future technical and managerial leaders through structured coaching
• Drive methodology improvements and automation that measurably improve productivity
• Shape the technical direction of next-generation SerDes platforms

Requirements:

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related discipline
• 15+ years of semiconductor development experience with progression into engineering leadership
• Proven experience leading engineering teams with significant schedule, quality, and customer impact
• Strong understanding of SerDes PHY digital development flows including architecture, RTL, verification, firmware, integration, and release
• Experience with Ethernet, PCIe/CXL, or other high-speed protocols; Ethernet SerDes experience strongly preferred
• Track record managing execution across distributed teams and multiple stakeholders

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support programs
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries

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Key responsibilities:

• Design widely used APIs, frameworks, and abstractions for other engineers and researchers.
• Own platform layers beneath every environment, including the agent runtime.
• Build tooling for environment owners to understand, debug, and maintain their environments in production.
• Embed with research teams on a rotational basis and transfer ownership when rotating off.
• Anticipate and prevent silent failure modes through type safety, testing, and refactors.
• Drive adoption of new frameworks across the organisation.
• Help define engineering standards and mentor researchers and engineers.

Minimum qualifications:

• Deep expertise in Python, including static typing and safe async patterns.
• Strong taste in API and framework design.
• Experience designing or operating stateful concurrent or distributed systems.
• Habit of verification: measuring before concluding and building checks for correctness.
• Experience working productively in large, evolving codebases.
• Strong written and verbal communication.

Preferred qualifications:

• Experience building infrastructure or frameworks for machine learning research or RL workflows.
• Experience building agent frameworks, orchestration engines, or multi-agent systems.
• Experience using AI coding tools on code where correctness matters.
• Experience building client libraries or SDKs on top of sandboxed platforms.
• Experience with large-scale data processing or dataset lifecycle management.

The annual compensation range for this role is $405,000-$605,000 USD.

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You will be a strong fit if you have deep expertise in Python, API and framework design experience, and intuition for complex system failures.

Key Responsibilities:

• Design widely used APIs, frameworks, and abstractions for engineers and researchers.
• Own platform layers beneath every environment, including the agent runtime.
• Build tooling for environment owners to understand, debug, and maintain their environments.
• Embed with research teams, work directly in their codebases, and transfer ownership.
• Anticipate and prevent silent failure modes through type safety, testing, and refactors.
• Drive adoption of new frameworks and define engineering standards.

Minimum Qualifications:

• Deep expertise in Python, static typing, and performance.
• Strong taste in API and framework design.
• Experience with stateful concurrent or distributed systems.
• Verification mindset with measurement and checks.
• Experience in large, evolving codebases.
• Strong written and verbal communication.

Preferred Qualifications:

• Experience with machine learning research or RL workflows.
• Building agent frameworks, orchestration engines, or multi-agent systems.
• Using AI coding tools for verifiable code.
• Client libraries or SDKs on sandboxed platforms.
• Large-scale data processing or dataset lifecycle management.

The annual compensation range for this role is $405,000-$605,000 USD.

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Responsibilities

• Apply, demonstrate, and champion best-in-class methods, tools, and practices to ensure embedded software achieves safety.
• Lead the development of the FuSa Software Health Dashboard for the enterprise, including its metrics and criteria for maturity.
• Collaborate closely with cross-functional teams, including product engineering, program management, validation and verification, software, hardware, design, integration, quality, and architecture.
• Apply system engineering, risk analysis, troubleshooting, and root cause analysis methods to find software-related issues and close the loop to process, methods, and tools gaps.
• Align and exploit synergies with SQA to drive FuSa maturity.
• Drive continuous improvement initiatives to optimize software development and deployment processes, tools, and methodologies.
• Provide consistent health status, insights, risks, and opportunities to executive leadership and stakeholders.

Qualifications

• Bachelor’s degree in Software Engineering, Computer Science, Electrical Engineering, Mechanical Engineering, or a related field.
• FuSa Professional Accreditation: UL, TUV, Exida, or equivalent.
• Minimum of 7 years of hands-on experience in embedded automotive safety software verification.
• Demonstrable deep understanding of ISO-26262 Part 6.
• Experienced with tools commonly used in safety software test.
• Working knowledge of ISO-26262 Part 3,4 Concept and Systems Engineering process.
• Excellent communication and collaboration skills.
• Leadership abilities, with a track record of initiative and problem-solving.

Benefits

• Immediate medical, dental, vision, and prescription drug coverage
• Flexible family care days, paid parental leave, new parent ramp-up programs, subsidized back-up child care, and more
• Family building benefits, including adoption and surrogacy expense reimbursement, fertility treatments, and more
• Vehicle discount program for employees and family members and management leases
• Tuition assistance
• Established and active employee resource groups
• Paid time off for individual and team community service
• A generous schedule of paid holidays, including the week between Christmas and New Year’s Day
• Paid time off and the option to purchase additional vacation time

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You will work with Ford Connected Vehicle Software and Product Data Integrity, and supplier engineering teams to identify safety-related process and work product gaps and recommend best practice solutions.

You will develop a FuSa V&V capability maturity plan working with engineering stakeholders.

You will report to the Director of the Office of Functional Safety Assurance (OFSA).

Responsibilities

• FuSa Technical Leadership: Apply, demonstrate and champion best-in-class methods, tools, practices to ensure embedded software achieves safety.
• FuSa Software V&V Health Dashboard Ownership: Lead the development of the FuSa Software Health Dashboard for the enterprise, including its metrics and criteria for maturity. Develop AI-enhanced tracking and analytic tools to determine status and priority actions.
• Cross-functional collaboration: Collaborate closely with cross-functional teams including product engineering, program management, validation and verification, software, hardware, design, integration, quality, and architecture to drive maturity of enterprise FuSa Health metrics.
• FuSa Software related escapes: Apply system engineering, risk analysis, troubleshooting and root cause analysis methods to find software-related issues and close the loop to process, methods and tools gaps.
• Alignment of FuSa and Quality Assurance: Align and exploit synergies with SQA where this helps drive FuSa maturity.
• Continuous improvement: Drive continuous improvement initiatives to optimize software development and deployment processes, tools, and methodologies, enhancing effectiveness.
• Communication: Provide consistent health status, insights, risks and opportunities to executive leadership and stakeholders.

Qualifications

• Education: Bachelor’s degree in Software Engineering, Computer Science, Electrical Engineering, Mechanical Engineering, or a related field.
• Experience: Minimum of 5 years of hands-on experience in embedded automotive safety software verification.
• Technical expertise: Demonstrable deep understanding of ISO-26262 Part 6 e.g. software requirements analysis, decomposition, allocation, verification. Software architectural design, safety analysis, safety mechanism design and implementation, software unit test, integration and verification, FFI, DFA, software design practices to ensure safety, software structural design and verification, the inter-relationship between software, hardware and systems engineering as it relates to the safety lifecycle. Use of AI in embedded software development and verification.
• Experienced with tools commonly used in safety software test including requirements analysis, IDEs, static code analysis, code complexity metrics, code and requirement coverage, MISRA and Safe C rules checkers, debuggers, configuration management, change control, CI/CD pipelines, regression test, SIL, HIL, MIL. Model-based software development. Development of software test strategies including fault injection.
• Working knowledge of ISO-26262 Part 3,4 Concept and Systems Engineering process, tools, methods, including HARA, HAZOP, Functional Safety Concept. Able to understand the translation of systems work products into software.
• Communication & collaboration: Excellent communication and collaboration skills, with the ability to effectively engage with cross-functional teams, external partners, and stakeholders to drive successful feature system development projects.
• Leadership: Leadership abilities, with a track record of initiative and problem-solving, delivering high-quality software that meets safety, security, and performance objectives.

Benefits

• Immediate medical, dental, vision and prescription drug coverage
• Flexible family care days, paid parental leave, new parent ramp-up programs, subsidized back-up child care and more
• Family building benefits including adoption and surrogacy expense reimbursement, fertility treatments, and more
• Vehicle discount program for employees and family members and management leases
• Tuition assistance
• Established and active employee resource groups
• Paid time off for individual and team community service
• A generous schedule of paid holidays, including the week between Christmas and New Year’s Day
• Paid time off and the option to purchase additional vacation time.

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As a DFT engineer at the networking group at NVIDIA, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

Responsibilities:

• In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

• As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

• Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Requirements:

• B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

• 10+ years of practical experience.

• Exposure to rtl implementation and coding.

• Familiarity with verification tools.

• Familiarity with backend flows.

• Strong debugging, problem solving and analytical skills.

• Strong communication and social skills are required.

• Ability to work in a geographically diverse team environment.

• Self motivated, independent and target oriented.

Preferred Qualifications:

• Prior Design, Verification experience.

• Experience in working with back-end on area, power and timing closures.

• Experience with CDC flows and tools.

• Experience with silicon testing.

• Cad tool development experience.

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You are a highly skilled and passionate engineer, eager to make a tangible impact on the semiconductor industry by leveraging your expertise in design flows and customer applications.

What You'll Be Doing:

• Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.
• Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.
• Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.
• Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.
• Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.
• Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.

The Impact You Will Have:

• Enhancing customer satisfaction by delivering tailored, high-quality technical solutions and ongoing support.
• Driving successful adoption of Synopsys products within key foundries, solidifying long-term partnerships and business growth.
• Contributing to the continuous improvement of runset programming and installation processes, raising industry standards.
• Supporting the sales team with technical insights, helping to win new business and expand Synopsys's market reach.
• Identifying opportunities for innovation and improvement in EDA tools, directly influencing product development and competitiveness.
• Mentoring junior team members and sharing best practices, fostering a collaborative and high-performing work environment.

What You'll Need:

• Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.
• Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.
• Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.
• Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.
• Demonstrated ability to manage projects from start to completion, contributing to moderately complex aspects of technical initiatives.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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As a member of our team, you will be responsible for CPU on-chip interconnect network, coherency and last-level caches, focusing on tasks such as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation.

Responsibilities:

• Own and be responsible for crafting and timely delivery of a specific unit on the chip.
• Write readable high-performance and low-power RTL, perform synthesis and timing closure, and create design documentation.
• Collaborate with the verification team to verify the correctness of your unit.
• Work with implementation to achieve timing, area, performance, and power goals.
• Assist with timing closure of super units.

Requirements:

• Recent graduate with a BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
• Experience in processor or other related high-performance semiconductor designs.
• Verilog expertise required, as well as a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up, and lab debug.
• Effective communication and interpersonal skills are required, along with experience working in a dynamic, global team.
• A strong background in computer architecture, cache coherency, or high-speed interconnects is preferred.

You will also be eligible for equity and benefits.

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Responsibilities:

• Manage and provide ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.
• Deliver post-sales technical expertise during runset programming, implementation, and maintenance of Synopsys products.
• Implement detailed customer installation requirements and customize solutions to fit unique client environments.
• Ensure client needs are met and Synopsys solutions function according to technical specifications and industry standards.
• Collaborate with sales teams to provide pre-sales technical support, contributing to successful business development and customer onboarding.
• Troubleshoot and resolve moderately complex technical issues.
• Empower customers to efficiently deploy and maximize the value of Synopsys EDA solutions in their design workflows.
• Enhance customer satisfaction and strengthen long-term partnerships with key foundry clients.
• Drive successful product adoptions and implementations, contributing directly to Synopsys' market leadership.
• Support the technical excellence of customer projects, enabling innovative chip design and verification outcomes.
• Facilitate knowledge transfer, helping customers understand and leverage advanced product features.
• Identify opportunities for product improvements and feed insights back to development teams for continuous innovation.

Requirements:

• Basic understanding of the design process, with a preference for Design Rule Checking (DRC).
• Solid grasp of ASIC design flow, VLSI concepts, and/or CAD engineering principles.
• Familiarity with competitive EDA tool products and expertise in areas such as Verification, Place and Route, Design Reuse, and/or Physical Design.
• Ability to manage projects from initiation through completion, delivering high-quality technical solutions.
• Creative problem-solving skills and the ability to exercise judgment in selecting methods and techniques to obtain solutions.

Who You Are:

• Collaborative and effective communicator, able to build strong relationships with customers and internal teams.
• Resourceful and adaptable, thriving in dynamic, fast-paced environments.
• Detail-oriented with strong analytical skills and a commitment to delivering exceptional results.
• Open-minded and inclusive, embracing diverse perspectives and fostering an environment of belonging.
• Self-motivated and eager to learn, continuously seeking opportunities for growth and innovation.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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The Networking Chip Design team in India is a growing team.

Responsibilities

• Understand all features of a given project and define project milestones based on internal roadmaps, assign them, and track them through an agile framework.
• Develop system-level methodologies, tools, and IPs to build SOCs efficiently and scalably.
• Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.
• Integrate all pieces for a given defined project milestone and deliver the model to relevant teams for further verification.
• Have a good grasp of Perl, Python, or other industry-standard scripting languages.

Requirements

• BS/MS with 4+ years of practical semiconductor design and architecture experience building complex SoCs.
• Firsthand experience and solid understanding of all phases of SOC development in multiple ASIC projects, including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure, and Physical design.
• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB, etc.).
• C/C++ programming or Python or any other industry-standard scripting language experience desirable.
• Experience working with software teams to tightly define the HW/SW interface.
• Hands-on experience in successful tape-outs of multiple complex, high-volume SoCs in advanced process nodes.
• Exposure to various Chip Design Functions to collaborate and solve complex cross-functional problems.
• Excellent verbal and written communication skills to interact with cross-functional teams.
• Good teamwork spirit and collaboration skills with team members.
• Experience in synthesis, physical design, and DFT is a plus.
• Background in RTL Build and Design Automation is a plus.

Benefits

NVIDIA offers highly competitive salaries and a comprehensive benefits package. You can find more information about our benefits at www.nvidiabenefits.com/

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You are a seasoned engineering professional with a deep passion for advancing semiconductor technology. With at least a decade of experience in ASIC design, verification, or applications engineering, you bring a robust understanding of both front-end and back-end development.

What You'll Be Doing:

• Guiding customers through the integration of Synopsys UCIe IP into their ASIC SoC and systems, addressing both technical and process challenges.
• Providing expert advice on IIP configuration, simulation, synthesis, floorplanning, static timing analysis (STA), and design-for-test (DFT) strategies.
• Conducting in-depth integration reviews at key SoC development milestones to ensure optimal IP performance and compatibility.
• Delivering comprehensive training and workshops to customer engineering teams on the latest UCIe specifications and integration best practices.
• Collaborating with Synopsys R&D to develop application notes and technical collateral on advanced integration topics.
• Supporting pre-sales activities, including technical demos, conference presentations, and responding to technical inquiries from prospective clients.
• Providing feedback and insights to R&D for continuous improvement of Synopsys IIP products based on customer experiences and emerging industry trends.
• Participating in internal design reviews to align product development with evolving customer needs and market demands.

The Impact You Will Have:

• Accelerating customer success by ensuring seamless integration of Synopsys UCIe IP, reducing time-to-market for innovative SoC solutions.
• Enhancing the reliability and performance of next-generation semiconductor products across diverse market segments.
• Driving adoption of the latest chiplet interconnect standards through effective customer education and support.
• Contributing to the evolution of Synopsys' IP portfolio by relaying critical customer feedback and identifying opportunities for product enhancement.
• Influencing the direction of industry standards and best practices through thought leadership and technical collaboration.
• Representing Synopsys at industry events, reinforcing our leadership position in IP integration and semiconductor innovation.
• Building long-term partnerships with key customers, fostering trust and collaboration across the semiconductor ecosystem.

What You'll Need:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Minimum 10 years of experience in ASIC design, verification, or applications engineering within advanced technology nodes (10nm/7nm/5nm/3nm).
• Hands-on expertise in mixed-signal and high-speed interface design and integration, ASIC front-end and/or back-end implementation, including simulation, synthesis, floorplanning, and DFT.
• Strong knowledge of EDA tools and methodologies, with additional experience in P&R, Physical Verification, and Signal/Power Integrity highly valued.
• Proven ability to debug and troubleshoot silicon and/or FPGA/hardware, with familiarity in Die-to-Die and PCIe/CXL protocols considered a significant advantage.

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As a Chip Design Verification Engineer in the DFT team at NVIDIA, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

Responsibilities:

• In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

• As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

• Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

Requirements:

• BSc. in Electrical Engineering or Computer engineering, or equivalent experience.

• 3+ years of practical verification experience.

• Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy).

• Experience with Specman is a plus.

• Good understanding of RTL design (Verilog).

• Strong debugging, problem solving and analytical skills.

• Excellent communication and social skills.

• Ability to work in a geographically diverse team environment.

• Self motivated, independent and target oriented.

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We are looking for a top-tier firmware engineer who is motivated by the full craft , writing the firmware, proving it accurate, crafting the tooling and infrastructure strategy that makes the whole team faster, and setting the technical bar for everyone around them.

Responsibilities:

• Own the technical architecture and roadmap for NVLink and high-performance interconnect firmware across next-generation GPU platforms , staying hands-on in C, C++, and Python on the highest-leverage problems.
• Take end-to-end ownership of sophisticated interconnect features, driving seamless execution from design through final verification.
• Architect correctness models, verification plans, and test cases , primarily in Python , to prove firmware functionality across both pre-silicon and post-silicon environments.
• Shape silicon bring-up, design-for-debug, and program-level validation strategy with architecture, hardware, and design leads across Bangalore and US sites.
• Define the verification methodology, engineering standards, and quality gates the team builds to , and the automation strategy that scales them.
• Advance the team’s AI-assisted, agentic debug and root-cause tooling, raising how fast the team resolves the hardest failures.
• Grow the team’s technical capability , mentoring engineers, raising the quality bar, and de-risking the hardest cross-generation problems before they land.

Requirements:

• BS or MS degree (or equivalent experience) in Electrical Engineering, Computer Science, or a related field.
• 10+ years of experience in firmware or software development and verification.
• Deep programming proficiency in Python, C, and C++, with strong command of object-oriented design.
• Strong understanding of computer architecture, microprocessors, and microcontroller fundamentals.
• Expert debugging and analytical skills that span the hardware/software boundary.
• A track record of technical leadership , setting direction, mentoring engineers, and raising quality across a team.
• Excellent collaboration and communication skills, with proven success in a multi-national, multi-time-zone environment spanning on-site and remote teams.
• A highly motivated, creative problem-solver with a passion for deep-tech and a bias toward rigorous testing.
• A versatile, self-motivated approach , equally at home in development, verification, and infrastructure.

Nice to Have:

• Depth in test automation and test-case design , building maintainable frameworks that cover edge cases and critical scenarios.
• Familiarity with secure development techniques: threat modeling, static and dynamic code analysis, fuzzing, and negative testing.
• Experience with multi-core, multi-process, and multi-threaded programming.
• Exposure to high-performance computing systems, interconnects, or networking protocols and architectures.
• Passion for unlocking the potential of yourself and those around you.

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$198K – $294K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
• 401(k) retirement plan with employer match
• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
• Mental health and wellness support
• Employer-paid basic life and disability coverage
• Annual learning and development stipend to fuel your professional growth
• Daily meals in our offices, and meal delivery credits as eligible
• Relocation support for eligible employees
• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Forward Deployed Engineering (FDE) team turns research breakthroughs into production-grade systems. We embed deeply with customers to solve high-leverage problems and act as the delivery engine for our most complex large-scale engagements. We move quickly from prototype to production and surface reusable patterns that shape our platform. We operate at the intersection of deployment and development – working closely with OpenAI Research, Product and Partnerships.

About the Role

As a Technical Deployment Lead (TDL), you will define how OpenAI delivers complex systems to Semiconductor customers. You will own how solutions are scoped, built, shipped, and adopted across high-value engineering workflows such as RTL design, verification, and physical implementation. You’ll translate business outcomes into a technical plan, run day-to-day execution across FDEs, Researchers, and Customer Engineers, and partner with customer teams to ensure delivery supports their goals.

You will focus on the semiconductor vertical to deploy next-generation AI capabilities. You will own delivery end-to-end: embedding with customers to map workflows and success criteria, ensuring components ship on time, and leading readiness and change management for adoption. You’ll track progress, manage dependencies, make sequencing decisions, and drive 0→1 prototypes through MVP and scale. You will also share field insights with Product and Research to guide roadmap and priorities.

Success will be measured first and foremost by impact - deployments that deliver measurable value against customer goals, drive adoption, and become critical to their workflows. Additional measures of success include delivery reliability (milestones hit, low reopen/churn), operating leverage (patterns reused across deployments), judgment under pressure, and product impact (field signal that shifts roadmaps/architectures).

Responsibilities

• Own the technical delivery plan for multiple interdependent work streams, translating customer objectives into a roadmap with milestones, dependencies, and acceptance criteria.
• Run day-to-day engineering execution by tracking and driving delivery across OpenAI FDE and customer teams. Keep progress unblocked and sequenced. Make real-time trade-offs on scope and priority to protect the critical path.
• Embed with Semiconductor customer teams to land production deployments and drive adoption. Map workflows, shape tools/integrations, and translate requirements into a delivery plan.
• Shape production deployments that integrate with customer infrastructure, data systems, and engineering toolchains, including export-controlled environments.
• Partner with Product and Research so platform components and research work streams land in time to support deployment goals.
• Codify solution patterns and evals. Extract reusable patterns and package field signals to improve product and models.
• Own value cases and ROI. Set impact hypotheses, baselines, and KPIs; run pre-/post-deployment measurement and report to exec sponsors.
• Help define how OpenAI engages Semiconductor customers.

Requirements

• Bring 7+ years of customer‑facing technical delivery leadership.
• Have deep expertise in Semiconductor workflows, including RTL design, verification, EDA tooling, and physical implementation.
• Track record of successfully leading large, complex, high-stakes customer engagements where customer outcomes depended on tight coordination and fast decision making, ideally involving AI.
• Excel in high ambiguity environments. Know how to simplify complex and dynamic work.
• Move fluidly between system level understanding and execution level detail; can dive into customer workflows/data, map constraints, sketch architectures and move ambiguous problems to shipped systems.
• Think strategically and pattern-match. Able to step back from execution detail, recognize broader trends across deployments, and connect customer needs to scalable, reusable solutions.
• Have strong technical fluency and sharp sequencing instincts. Confident discussing technical details, pressure-testing architectures, and making trade-offs.
• Have shipped AI/LLM systems. You understand solution patterns, integration basics, and production pitfalls.
• You’re a translator with executive presence. You make complex technical trade-offs legible to business leaders and convert strategy into day-to-day technical execution.
• Enjoy being onsite with customers to accelerate delivery (often 25-50%, sometimes higher).

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You will own and work with cross-functional teams to architect, develop, and deploy DFT methodologies for our next-generation products, including RTL design, verification, pattern generation, and partnering with teams like timing, physical design, software, bring-up, and production.

Additionally, you will mentor junior engineers on test designs and trade-offs, including cost and quality.

The ideal candidate will have a Master's degree in Electrical Engineering or a related field with proven experience in DFT or related domains. You should have 10+ years of hands-on experience in SoC architecture, RTL design, and verification, with excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.

Good exposure to cross-functional areas, including RTL & clocks design, STA, place-n-route, and power, is required to ensure the right trade-offs are made. Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development is also necessary.

Knowledge of DFT security and hardware system security is a plus. Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges are essential.

NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity and benefits.

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Responsibilities

• AI Ecosystem Development: Build and deploy an AI verification environment, moving from manual testbenches to automated stimulus generation and coverage closure.

• Next-Gen Tooling: Develop and integrate AI agents and ML models directly within the verification toolchain to automate intent-to-testbench workflows.

• Intelligent Debugging: Create and refine AI-based debug assistants that can analyze simulation failures, categorize bugs, and suggest fixes autonomously.

• Methodology Innovation: Research and apply groundbreaking AI approaches (such as Reinforcement Learning or LLMs) to address the "state-space explosion" in chip verification.

• Collaborative Intelligence: Work with design automation teams and EDA vendors to ensure our AI solutions provide end-to-end efficiency from RTL to GDS.

• Leadership & Training: Act as the authority, training the broader team on how to bring to bear AI tools and "human-in-the-loop" methodologies.

Requirements

• Bachelor’s Degree in Electrical Engineering, Computer Science, or equivalent experience.

• 8+ years of hands-on pre-silicon verification experience.

• Strategic Innovation: A perspective geared toward automation and a desire to redefine traditional "manual" verification workflows.

Preferred Qualifications

• AI for EDA: Experience building or using AI tools specifically designed for hardware verification (e.g., automated coverage, log analysis, or bug prediction).

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As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints.

Responsibilities include:

• Collaborating with frontend design team to understand clocking requirements for the chip
• Working with backend teams to understand physical restrictions
• Architecting, designing and validating clocks RTL
• Running and enhancing in-house flow to guarantee good quality of clocks RTL and netlist
• Delivering clock information to SOC verification team, timing and DFT teams
• Using Perl/Python to improve productivity
• Collaborating with software and silicon solution team to debug GPU clock silicon bugs

Requirements:

• BS or MS in EE or equivalent experience
• 2+ years of meaningful work experience
• Validated experience in RTL design (Verilog), verification and logic synthesis
• Strong coding skills in Perl or Python or other industry-standard scripting languages
• Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
• Good understanding of backend flows and requirements is a plus
• DFT knowledge is a plus
• Experience in implementing on-chip clocking networks is desirable
• Excellent analytical and problem-solving skills
• Fluent English (both written and spoken) and excellent communication skills
• Good teamwork spirit, easy to cooperate with team members

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As a Program Chief Engineer you will be responsible for defining and driving the system's architecture, technical roadmap, and overall engineering excellence. You will lead a multi-disciplinary team of high-performing engineers, ensuring that the system meets stringent performance, reliability, and mission requirements in challenging maritime environments. This role combines strategic technical leadership with direct hands-on involvement in critical design and integration challenges.

This is a highly visible and impactful role where your deep technical expertise, strategic thinking, and leadership will directly contribute to delivering transformative capabilities for national security.

Responsibilities

• Technical Leadership & Vision: Define and articulate the technical vision and strategic roadmap for the system, ensuring alignment with Anduril's broader Dive-XL Core Platform and customer needs.

Work directly with the product team to ensure tactical development is executed on plan.

• Architectural Design Authority: Serve as the ultimate technical authority for the system architecture, design decisions, and critical trade-offs across all engineering disciplines.
• System Integration & Performance: Oversee the end-to-end development lifecycle, from requirements definition and conceptual design through detailed design, integration, test, and deployment.
• Test & Evaluation: Define and oversee the test and evaluation strategy, including acceptance criteria, test readiness reviews, and support to customer acceptance testing.
• Technical Problem Solving: Lead the resolution of complex technical challenges, acting as a hands-on expert and guiding teams through difficult design, integration, or operational issues.
• Technical Trade-offs: Drive build vs. buy decisions, manage technical debt, and balance speed of delivery against long-term system sustainability.
• Team Mentorship & Development: Provide technical mentorship, guidance, and critical review for engineering teams, fostering a culture of innovation, excellence, and rigorous problem-solving.
• Risk and Opportunity Management: Identify, assess, and mitigate technical risks throughout the program lifecycle, developing contingency plans and advising program leadership.
• Customer & Stakeholder Engagement: Act as a primary technical point of contact for internal stakeholders, customers, and partners.

Clearly communicate complex technical information, program status, and strategic direction.

• Cross-Site Coordination: Collaborate closely with the US Chief Engineer counterpart to ensure technical alignment across program variants, share lessons learned, and maintain architectural consistency.
• Requirements Management: Ensure robust requirements decomposition, traceability, and verification plans are in place for all subsystems.
• Innovation & Research: Stay abreast of cutting-edge technologies, research, and industry trends relevant to autonomous underwater systems, incorporating best practices and innovative solutions.

Requirements

• Bachelor's, Master's, or Ph.D. in Mechanical Engineering, Electrical Engineering, Aerospace Engineering, Robotics, Computer Science, or a related technical discipline.
• 15+ years of experience in the design, development, integration, and deployment of complex autonomous systems.
• 5+ years of demonstrated experience as a Chief Engineer, Technical Director, Lead Architect, Engineering Fellow, or equivalent senior technical leadership role on a major hardware/software program.
• Proficiency in systems engineering principles, including requirements management, interface control, verification, and validation.
• Proven ability to lead and mentor highly technical, multi-disciplinary engineering teams.
• Exceptional communication, presentation, and interpersonal skills, with the ability to articulate complex technical concepts to diverse audiences.
• Must be able to obtain and maintain an Australian National Security Clearance (NV2 or higher).

Preferred Qualifications

• Deep expertise across multiple AUV sub-domains, such as hydrodynamics, propulsion, power systems, underwater acoustics, navigation, autonomy, materials science, mechanical design, and software architectures.
• Active Australian National Security Clearance (NV2 or higher).
• Experience with the full lifecycle of Australian Defence Force (ADF) acquisition programs.
• Demonstrated understanding of Australian defence contracting frameworks.
• Experience with system safety engineering practices and familiarity with submarine/AUV safety certification processes.
• Familiarity with cybersecurity best practices for autonomous systems.
• Expertise in AI/ML applications for AUV autonomy, perception, and decision-making.
• Experience with advanced manufacturing techniques for marine systems.

Benefits

Anduril offers a comprehensive, competitive benefits package, including top-tier benefits for full-time employees.

Salary

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full-time offers; and are considered part of Anduril's total compensation package.

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Responsibilities

• Lead end-to-end planning and execution of AI for Chip Design initiatives, ensuring timely, on-scope, and scalable delivery
• Define program plans and timelines for AI capabilities, tracking progress, partnership status, risks, opportunities, and reporting status to leadership
• Lead technical discussions between AI engineers, hardware teams, platform groups, and third-party tool providers to ensure alignment on requirements, architecture, integration, and delivery expectations
• Operationalize the evaluation of both internal and external AI tools, drive their availability and adoption by collaborating with hardware teams, providing guidance, and gathering feedback for continuous improvement
• Act as a product and program interface between silicon design teams, internal AI platform teams, and third-party partners, helping prioritize requirements and translate user needs into actionable roadmaps
• Establish and monitor key program metrics to measure execution success, identify bottlenecks, and ensure delivery meets quality, performance, and scalability targets
• Serve as the central point of communication for all collaborators, providing clear status updates and insights into dependencies
• Partner with engineering leaders to prioritize initiatives that improve impact for silicon development and hardware workflows

Requirements

• Bachelor’s degree or equivalent experience in Computer Science, Electrical Engineering, or a related field, with proven experience leading complex, multi-functional technical programs in AI, silicon, or infrastructure
• 10+ years of technical program management spanning AI and ASIC chip design
• Strong understanding of RTL design, simulation, and formal verification, as well as software engineering fundamentals, system architecture, and scalable infrastructure
• Hands-on experience building, deploying, integrating, or enabling AI agents, LLM-powered systems, or AI productivity tools in real-world engineering workflows
• Proven ability to collaborate deeply with engineering teams and influence technical decisions, architecture, prioritization, and trade-offs
• Experience driving programs from concept through production, including planning, execution, risk management, team alignment, and delivery at scale
• Ability to gather, synthesize, and prioritize requirements from technical users, and communicate them clearly to internal engineering teams and external partners
• Excellent communication and leadership, with the ability to translate complex technical concepts into clear program direction and updates

Benefits

• Equity
• Benefits

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You are a passionate and driven professional with a profound mastery of hardware-assisted verification (HAV), using emulation and FPGA prototyping methodologies, with a sharp focus on performance optimization. Your expertise covers the entire lifecycle of HW/SW product development, from early RTL verification to software bring up and platform delivery.

What You'll Be Doing:

• Architecting custom emulation methodologies using ZeBu to solve high-value problems for customers.
• Serving as the primary technical interface for debugging and resolving issues in ZeBu flow/methodology.
• Providing technical leadership and product evaluation support to key emulation customers globally.
• Leading comprehensive root cause analyses to resolve and prevent emulation performance bottlenecks.
• Ensuring the highest standards of verification for SoC designs, contributing to the creation of robust and reliable products.
• Collaborating with internal R&D teams to define product requirements and validate new tool features based on real-world customer usage.

The Impact You Will Have:

• Elevating emulation runtime performance through the development and deployment of cutting-edge technologies.
• Delivering effective root cause analysis that drives measurable improvements in performance and customer satisfaction.
• Enhancing verification processes for SoC designs, ensuring the delivery of high-quality, reliable silicon products.
• Building strong, collaborative relationships that drive customer success and foster innovation.
• Contributing to the global deployment of advanced performance technologies in ZeBu platforms.
• Driving a culture of continuous innovation and technical excellence within the team and broader organization.

What You'll Need:

• Minimum 15+ years of experience in emulation methodology, spanning early RTL verification to software bring up.
• Proven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation.
• Comprehensive knowledge of the architecture of emulation/FPGA prototyping platforms and their ecosystems.
• A good understanding of the compilation and runtime flows on these emulation platforms.
• Demonstrated experience in using debug features of these emulation platforms, and in conducting root cause analysis for emulation runtime performance issues.
• Strong collaborative skills, with a track record of working effectively with cross-functional teams to drive product and customer success.
• Proficient with HDL (Verilog/VHDL), HVL(e/vera/SystemVerilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering.
• Experience on VMM/OVM/UVM and knowledge of simulator-emulator co-emulation are preferred.

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The BESS Product Lifecycle Management Engineer is responsible for the architectural integrity, configuration discipline, and product data control of Ford Energy’s BESS platforms. This role will lead the setup and evolution of Ford Energy’s PLM environment, ensuring that engineering, manufacturing, purchasing, commissioning, and aftersales activities are fully supported through controlled, traceable, and scalable lifecycle processes.

Responsibilities

PLM System Setup and Control

• Execute PLM setup and governance tasks for Ford Energy BESS programs, supporting the configuration, workflow design, and maintenance of systems such as Siemens Teamcenter, SAP PLM, 3DEXPERIENCE, or similar platforms.
• Define lifecycle states, access roles, release paths, and data structures to ensure stable, controlled product development and deployment.
• Drive PLM configuration management and standard work, ensuring consistent usage across engineering and manufacturing functions.
• Define and maintain process health metrics, workflow reporting, and governance routines to support scalable PLM operations.

Product Structure, Data, and Release Control

• Define and maintain EBOM, MBOM, CAD data, part metadata, specifications, and revision control within PLM.
• Ensure accurate configuration management across product variants, effectivities, manufacturing sites, and field-deployed systems.
• Support traceability of engineering data throughout the product lifecycle, including as-designed, as-built, and as-maintained states.
• Support linkage of visualization assets, assembly instructions, controlled documentation, and product structures.
• Manage product records to support deployed systems, retrofits, and service activity.

Engineering Change and Release Management

• Support and administer engineering change processes within PLM systems.
• Ensure proper review, approval, and implementation of engineering changes from request through release.
• Coordinate with engineering, manufacturing, supply chain, purchasing, quality, commissioning, and service teams to assess the impact of changes.
• Support design release of hardware components, including electrical, mechanical, and electromechanical parts, in automotive or non-automotive environments.
• Support implementation of corrective actions, design changes, and field-driven updates with full configuration traceability.

Commissioning and Aftersales Enablement

• Support commissioning and aftersales teams with accurate product configuration records, build documentation, and field issue resolution.
• Help ensure project delivery requirements are met through disciplined data control and configuration traceability.
• Support corrective actions related to released hardware, field changes, service parts, and customer-specific configurations.
• Institutionalize lessons learned by updating PLM standards, change processes, and release documentation.
• Support service BOMs, spare parts definitions, and retrofit documentation as required.

Process Improvement and Enterprise Integration

• Improve PLM workflows to increase efficiency and reduce manual effort.
• Standardize PLM processes across departments and sites.
• Identify gaps in current PLM usage and propose system and process improvements.
• Support integration of PLM with ERP, MES, manufacturing, purchasing, service, and document control systems.
• Contribute to digital thread and digital traceability initiatives across engineering and manufacturing.

Governance, Compliance, and Audit Readiness

• Ensure product data complies with internal standards and relevant industry expectations.
• Maintain audit-ready documentation within PLM systems.
• Support configuration audits, lifecycle reviews, release reconciliation, and process compliance checks.
• Support secure collaboration by enforcing role-based visibility and controlled access to sensitive data.
• Support data stewardship practices that improve accuracy, accountability, and long-term product record integrity.

Qualifications

• Bachelor’s degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, Computer Science, Systems Engineering, or related field.
• 7+ years of experience in PLM engineering, product data management, configuration management, or related engineering operations.
• Experience with PLM systems such as Teamcenter, SAP PLM, 3DEXPERIENCE, Windchill, or similar platforms.
• Proven experience in design and release of hardware components in automotive or non-automotive applications.
• Strong understanding of PLM concepts: BOM structures, lifecycle states, configuration management, effectivity, and engineering change processes.
• Experience supporting manufacturing or engineering environments with multiple stakeholders.
• Strong written and verbal communication skills with the ability to engage technical and executive audiences.
• Ability and willingness to travel occasionally.

Benefits

• Immediate medical, dental, vision and prescription drug coverage
• Flexible family care days, paid parental leave, new parent ramp-up programs, subsidized back-up child care and more
• Family building benefits including adoption and surrogacy expense reimbursement, fertility treatments, and more
• Vehicle discount program for employees and family members and management leases
• Tuition assistance
• Established and active employee resource groups
• Paid time off for individual and team community service
• A generous schedule of paid holidays, including the week between Christmas and New Year’s Day
• Paid time off and the option to purchase additional vacation time.

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As part of NVIDIA's 'AI for chip design' team, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of chip design at NVIDIA and throughout the industry.

Responsibilities:

• As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high-performance, area and power-efficient RTL to achieve design targets and specifications.
• As part of the AI for Chip Design team, you will develop agentic AI solutions to craft the micro-architecture, implement the RTL, and deliver a fully verified, synthesis/timing clean design.
• Collaborate and coordinate with other designers as well as tool and flow owners to ensure design guidelines and agentic solutions meet their requirements.
• Use AI technologies to tackle complex problems in chip design, driving innovation and meaningful impact across the industry.
• Design and deploy LLM-powered solutions for engineering assistants and multi-turn, multi-modal dialogue systems.
• Engage with the latest advancements in machine learning and AI to create powerful solutions.

Requirements:

• Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
• 8+ years of meaningful work experience.
• Experience in micro-architecture and RTL development (Verilog) in complex designs.
• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required.
• Proficiency in rapid prototyping using Python with strong foundational knowledge of data structures, algorithms, and software engineering principles.
• Experience with fine-tuning large language models, building advanced multi-agent systems, RAG pipelines and vector databases.
• Strong analytical, communication, and interpersonal skills, with a proven track record to thrive in dynamic, product-focused, and distributed teams.
• A proactive approach to problem-solving and a willingness to acquire new skills and knowledge as needed to achieve results.

You will also be eligible for equity and benefits.

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This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• As a key member of our ASIC Verification team, you will contribute to verifying graphics and compute features within an IP.
• You will be responsible for IP-level verification of GPU ASICs, including the design, architecture, golden models, and micro-architecture, using advanced verification tools and methodologies.
• You will work with the specifications, develop test plans, tests and verification infrastructure using UVM methodology and ensure functional and code coverage of all the RTL which you will verify.
• Work with HW architects and designers to make the right implementation choices.
• You will be working with architects, designers, and other members of your verification teams to accomplish your tasks.

Requirements:

• B.Tech./ M.Tech. with 2+ years of relevant experience
• Familiarity with Verilog, C++ and OOPs concepts.
• Experience in verification and test planning at Unit level.
• Experience in developing and working in functional coverage based constrained random verification environments
• Good understanding of computer architecture concepts.
• Strong technical fundamentals with superior analytical skills and problem-solving skills
• Knowledge in SystemVerilog or similar HVL, experience in verification methodologies like UVM/VMM is highly desirable
• Exposure to industry standard verification tools for simulation and debug

Preferred Qualifications:

• Prior experience in 3D graphics processing, processor verification.
• C/C++ programming language experience
• Experience in scripting and tool development using Perl and Python
• Excellent debugging skills
• Good interpersonal & communication skills & dream to work as a great teammate

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Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

The IODFX Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for IO and interconnect testing for some of the industry's most complex semiconductor chips.

Responsibilities

• POR to Post Silicon Testing of DFX features for high-speed IOs, including crafting test features crucial for manufacturing testability of High-Speed IOs
• Architect, design, and validate these test features with a robust and scalable test plan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools
• Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign-off on Test coverage for various products using standard coverage metrics
• Work on automation, flow development and improvement, coverage metrics, test execution, bug identification/fix, and IO-test productization
• Solve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms
• Collaborate with IP teams for design/verification of IOBIST test-logic, Mixed Signal Circuit design teams, and other DFX teams

Requirements

• BTech/BE/BS or MTech/ME/MS in EE/ECE or equivalent experience
• Solid analytical and problem-solving skills
• Good understanding and exposure to logic design, architecture, and verification
• Strong coding skills in industry-standard scripting languages
• 3+ years of experience in DFT and/or industry-standard verification flows like constrained random testing, UVM, coverage metrics, profiling tools, etc.
• Outstanding written and oral communication skills with a curiosity to learn

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This role is at the intersection of software engineering and hardware design. You'll work on the software that accelerates the development of NVIDIA's industry-leading networking chips – the backbone for the AI revolution.

The ideal candidate will combine strong coding skills with a solid understanding of chip design or verification. If you're excited about solving technical bottlenecks, building scalable tools, and collaborating with designers and verification experts, you'll fit right in.

Responsibilities

• Develop software tools for NVIDIA's chip design and verification flows.
• Collaborate closely with designers and verification engineers to identify bottlenecks, propose improvements, and build software solutions that boost productivity and quality.
• Own your solutions end-to-end , from idea to delivery to support.

Requirements

• B.Sc. or M.Sc. in Computer Science, Computer Engineering, or Electrical Engineering.
• Total of 5+ years of experience developing software tools for chip design/verification.
• Proficiency in software engineering, with strong debugging and system design skills.
• Strong communication skills and a proactive approach to working with users and cross-functional teams.

Nice to Have

• 2+ years of hands-on experience in chip design or verification.
• Proven ability to identify quality or efficiency gaps in design/verification workflows and deliver impactful methodology or automation improvements.
• Experience in leading or contributing to cross-team technical discussions to define software solutions.
• Passion for building usable tools, with a deep understanding of user needs, pain points, and design/verification/debug scenarios.
• Proficiency in Python.

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Responsibilities:

• Understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework.

• Define and develop system-level methodologies, tools, and IPs to build subsystems in an efficient and scalable manner.

• Work with SOC Assembly team and drive cross-functional teams towards SOC milestone execution.

• Integrate all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.

Requirements:

• BS (or equivalent experience) / MS with 3+ years of practical semiconductor design and architecture experience building complex SoC’s.

• Firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• C/C++ programming or python or any other industry-standard scripting language experience desirable.

• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.

• Hands on experience in successful tape outs of multiple sophisticated, high-volume SoCs in advanced process nodes.

• Exposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross functional problems.

• Excellent verbal and written communication skills to interact with cross functional teams to build consensus.

• Experience in synthesis, physical design and DFT is a plus.

• Experience in RTL Build and Design Automation is a plus.

Benefits:

NVIDIA delivers highly competitive salaries and a thorough benefits package. You can see what we can offer to you and your family at www.nvidiabenefits.com/

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The responsibilities of this role include:

• Receiving problem statements guidelines, requirements, and reporting milestones
• Independently performing trade studies, designs, and generating solutions for approval
• Executing the procurement of hardware as necessary to implement solutions
• Testing, verifying, and demonstrating the effectiveness of your solutions

This is a paid, in-person, 12-week internship. As an intern, you will have the opportunity to work on real-world projects and gain hands-on experience in the field of manufacturing engineering.

To be eligible for this internship, you must be pursuing a Bachelor's degree in Aerospace Engineering, Mechanical Engineering, or a related field, and be a rising senior at the time of the internship. You must also be a U.S. Person and be able to access Controlled Unclassified Information.

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This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Responsibilities:

• Verify the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies.
• Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Work on advanced verification methodologies like SV/UVM.
• Perform functional coverage driven verification closure.
• Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Requirements:

• B.Tech./ M.Tech., or equivalent experience.
• 4+ years of relevant experience.
• Experience in verification of complex IPs/units and sub-systems.
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
• Expertise in Verilog.
• Knowledge in SystemVerilog or similar HVL / UVM or VMM.

Nice to Have:

• Experience in memory subsystem or network interconnect IP verification.
• Debugging and analytical skills with sound scripting knowledge.
• Good communication and excellent team player.

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Key responsibilities include:

• Verifying the ASIC design, architecture, golden models and micro-architecture of the GPUs and full-chip level using advanced verification tools and methodologies.
• Building reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.
• Defining the verification scope, developing the verification infrastructure and verifying the correctness of the design.

Requirements include:

• B.Tech./ M.Tech or equivalent experience with 2+ years of relevant experience.
• Proficiency in Verilog and C.
• Familiarity with OOPs concepts.
• Hands-on experience in verification at Unit/Sub-system/SOC level.
• Good understanding of computer architecture concepts.
• Strong technical fundamentals with superior analytical skills and problem-solving skills.

Preferred qualifications include:

• Prior experience in 3D graphics processing or processor verification.
• C/C++ programming language experience.
• Experience in scripting and tool development using Perl and Python.
• Excellent debugging skills.
• Good interpersonal and communication skills & dream to work as a great teammate.

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The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.

Responsibilities:

• Designing and implementing SOC level clock requirements
• Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
• Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues

Requirements:

• B.SC. in Electrical Engineering/Computer Engineering.
• 3+ years of confirmed experience in chip design
• Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
• Proficiency in at least one common scripting languages like perl, python, bash, Tcl.
• Phenomenal teammate.

Ways to stand out from the crowd:

• Passion for quality. Experience with delivery back to RTL, to physical design, and other customers

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Your responsibilities will include owning execution quality and outcomes for complex, high-visibility customer engagements,from IP configuration and integration to silicon bring-up and production.

You will serve as a trusted partner to customer engineering leadership, shaping collaboration models and long-term technical engagement strategies.

Driving cross-functional alignment to translate customer challenges into structured technical strategies and influencing IP roadmaps by surfacing systemic pain points and execution bottlenecks.

Acting as the AI and digital transformation leader, championing adoption of AI tools in daily workflows and defining success metrics for efficiency, quality, and engineer enablement.

Building, mentoring, and retaining senior technical leaders and next-generation experts across a geographically distributed team, fostering a culture of ownership and continuous improvement.

You will scale expertise through AI and disciplined execution, bringing the agentic AI revolution into the real world of engineering at enterprise scale.

Strengthen customer confidence by delivering consistent, predictable, and high-quality technical outcomes across engagements.

Elevate organisational maturity by standardising best practices and modernising execution models for speed, quality, and repeatability.

Build the next generation of leaders, enabling the business to scale and innovate.

Drive transformation initiatives that position Synopsys as a leader in interface IP solutions for high-impact industries.

Expand Synopsys' influence and market share through strategic customer partnerships and technical credibility.

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As a key member of our design team, you will be responsible for the micro-architecture and build implementation of NOC/interconnect Xbar. You will work closely with verification engineers to deliver a fully verified build and ensure a synthesis/timing clean build to guarantee a routable and physically implementable design.

Key responsibilities include:

• Designing micro-architect features to meet area, performance, and power requirements
• Collaborating with architects, verification engineers, software engineers, and physical build engineers to accomplish your goals
• Delivering a fully verified build by working closely with verification engineers
• Delivering a synthesis/timing clean build to ensure a routable and physically implementable design

Requirements include:

• Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience
• 8+ years of build/RTL experience working on complex units in xbar/memory system
• Highly proficient in logic design, Verilog and/or System-Verilog, with a solid understanding of Computer Architecture and Digital Systems build
• A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug
• Strong interpersonal and communication skills to collaborate across teams
• Prior experience building arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches
• Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, and virtual channels
• Good debugging and analytical skills

You will also be eligible for equity and benefits.

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Automotive Business Development – Semiconductor & Ecosystem Strategy

Shanghai, Shanghai Municipality, China

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Primary Responsibilities

• Own and drive Synopsys automotive business development strategy in China, with clear linkage to semiconductor platforms, system architecture and long-term ecosystem evolution.

• Engage top management (CTO, Chief Architect, VP Engineering, BU Heads) at OEMs, Tier 1s and automotive semiconductor customers to influence strategic technology decisions.

• Identify, develop and execute strategic partnerships and ecosystem initiatives that enable adoption of Synopsys solutions across EDA, System, and IP, etc.

• Work hand-in-hand with Sales to:

o Shape customer strategy and account plans

o Enable high-impact executive engagements

o Convert ecosystem and partnership activities into tangible business outcomes

• Collaborate closely with Business Units to translate local automotive customer needs into solution requirements, orchestrating alignment across function units, influencing product positioning, integration and roadmap priorities.

• Act as a trusted strategic advisor to key customers on semiconductor architecture, design flows, platform strategies and future automotive technology directions.

• Represent Synopsys Automotive at executive briefings, customer workshops and selected industry forums, reinforcing Synopsys’ thought leadership in automotive semiconductor and system innovation.

Key Qualifications & Experience

• At least five years of Automotive market experience, with a focus on new applications (AD, ADAS, next generation infotainment, connectivity services) previous experience at and/or working with semiconductor companies, Tier 1s and OEMs

• Solid technical background preferred, especially related to: Automotive semiconductors, SoC / chip platforms, system or domain architectures; EDA, IP, verification, system design, software quality or related technologies.

• Demonstrated business development or strategic role experience in the automotive, semiconductor or system platform domain; proven ability to engage, influence and communicate at executive level, including framing value propositions for top-down decision making.

• Strong capability to work in matrix environments, influencing without authority and driving alignment across Sales, Marketing, Business Units and global teams.

• Bachelor’s degree in Engineering required; advanced degree in Engineering or Business is a plus.

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Key responsibilities include:

• Leading end-to-end physical implementation of PVT Sensor IP digital modules from floorplanning through GDSII across 1.4nm to 7nm foundry nodes, driving timing closure, power optimization, and sign-off
• Managing and growing a team of ASIC physical design engineers, setting technical direction, reviewing work, and mentoring engineers through complex multi-corner, multi-mode closure challenges
• Working hands-on when needed, jumping into critical path analysis, congestion fixes, or tricky STA scenarios to unblock your team and keep projects moving
• Collaborating daily with front-end design, verification, and product engineering teams to align RTL quality, design constraints, and implementation strategy from the start
• Owning project planning, resource allocation, and budget management for your team, balancing workload across multiple concurrent programs and node bring-ups
• Interface directly with customers to gather requirements, provide technical updates, resolve design issues, and ensure delivery meets their performance and schedule expectations

The ideal candidate will have 10+ years of experience in ASIC or IP physical design, with a proven track record of delivering complex designs at 7nm or below. You should have deep technical expertise across the full design flow from RTL to GDSII, including front-end understanding of synthesis and verification, and back-end mastery of STA, power analysis, and sign-off. Additionally, you should have direct experience managing and mentoring engineering teams, with a track record of developing engineers and delivering projects on time.

As a leader, you will shape the technical direction of physical implementation, drive continuous improvement in design flows using Synopsys EDA tools, and optimize methodology for faster convergence, better PPA, and cleaner handoffs to sign-off. You will also contribute to Synopsys IP portfolio competitiveness by ensuring every tapeout meets or exceeds PPA benchmarks and schedule commitments.

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Responsibilities:

• Work closely with the architecture and different software and hardware design teams.
• Implement new features for NVIDIA NIC and Switch firmware.
• Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.
• Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.
• Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.

Requirements:

• Bachelor's or master's Degree in Electrical/Computer Engineering, or equivalent experience.
• 8+ years of experience in Firmware.
• Strong C/C++ and OOP capabilities.
• Excellent Data analysis, debugging and problem-solving skills.
• Strong understanding of digital design, computer architecture, Linux, drivers and CPU/GPU/SOC architecture.
• Familiar with the fundamentals of Linux scripting languages and python hands-on.
• Strong analytical, debugging and problem solving skills.
• Motivated and independent with strong communication skills.

Nice to Have:

• Coding and automation skills in scripting languages like Python.
• Experience with RISCV architecture and verification.
• Ability to multitask and prioritize in a fast paced environment.
• Strong interpersonal and communication skills and ability to work effectively across different teams
• Hands-on lab experience with board bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).

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Key responsibilities include:

• Architecting, designing, developing, and supporting tools for RTL generation across all NVIDIA products
• Improving algorithms for automated connectivity, auto logic insertion, and post-processing Verilog RTL
• Improving the quality of existing tools and flows used by the team

Requirements include:

• BS or MS degree or equivalent experience in CE or EE
• At least 3+ years of work experience
• Strong coding skills in C++
• Good understanding of ASIC Design and understanding of Verilog RTL
• Strong interpersonal and collaboration skills

Preferred qualifications include:

• Prior experience in RTL design (Verilog), verification, and synthesis
• Proficiency in C++, Perl, Python, Make scripting
• Knowledge of Clocks/Resets design and verification

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing.

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We are looking for someone who brings deep expertise in analog and mixed-signal layout, along with the leadership to improve execution at scale through AI-enabled productivity, automation, and methodology innovation. At Synopsys, you will work on SerDes analog layout in advanced nodes, lead execution across complex programs, and help modernize how layout engineering gets done.

Key Responsibilities:

• Lead delivery of SerDes analog layout programs in advanced process nodes, owning execution quality, schedule predictability, and technical risk management
• Drive layout methodology improvements across floorplanning, matching, shielding, ESD integration, and physical verification workflows
• Collaborate regularly with design engineers, ESD teams, reliability engineers, CAD teams, and program managers to align layout execution with design intent and program milestones
• Deploy automation, scripting, dashboards, and AI-assisted workflows to reduce manual effort, improve consistency, and scale engineering productivity
• Mentor layout engineers on advanced techniques, design tradeoffs, and execution rigor, raising the technical bar across the team
• Influence cross-functional decisions on layout planning, resource allocation, tool adoption, and process improvements

Impact:

• Deliver high-speed analog layouts that meet performance, reliability, and manufacturability requirements in advanced nodes
• Reduce layout cycle time and rework through better automation, clearer handoffs, and smarter use of verification tools and AI-enabled workflows
• Strengthen cross-team collaboration so design, layout, ESD, and CAD work as one integrated execution engine, not siloed functions
• Build reusable layout methodologies and automation frameworks that scale across programs and geographies
• Elevate engineering capability through mentorship, technical leadership, and clear execution standards that make the team stronger over time
• Contribute to successful tapeouts of industry-leading SerDes IP that powers next-generation semiconductor products

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field
• 12+ years experience in analog or custom layout for high-speed analog and mixed-signal designs
• Deep expertise in layout implementation and related methodology in advanced process nodes
• Proven track record working across design, layout, ESD, CAD, and program teams to deliver complex layouts on schedule
• Experience improving engineering productivity through automation, methodology enhancement, dashboards, or workflow optimization
• This role requires experience in leading teams, planning execution, mentoring engineers, owning delivery outcomes, technical leadership, deep problem-solving ability, and cross-team methodology influence; experience or strong interest in applying AI and automation to layout workflows is a plus

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Your primary responsibilities will include:

• Verifying chip blocks/entities according to specifications
• Integrating and creating Full-Chip models
• Collaborating with organisation-wide groups

To succeed in this role, you'll need:

• A Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Communication Engineering
• At least two years of experience in verification or a similar position
• A high level of English proficiency
• Excellent teamwork skills

To stand out from the crowd, you'll have:

• Validated experience in Verification
• Experience with Specman
• Background in UVM/SV
• Knowledge of HDL (Verilog/VHDL)

If you're passionate about verification and want to be part of a dynamic team, apply now!

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We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.

As a Sr Staff Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship, continuously improving design methodologies and processes to enhance efficiency and quality.

The impact you will have is driving the development of high-performance physical IP that powers next-generation technologies, ensuring the reliability and efficiency of physical design solutions in our products, contributing to the success of Synopsys' strategic goals through innovative design solutions, sharing technical expertise to elevate team capabilities, fostering a culture of continuous improvement and excellence within the engineering team, and supporting the adoption and usability of our products by providing top-tier engineering expertise.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a driven and insightful Emulation Expert, passionate about pushing the boundaries of what's possible in ASIC digital design. With a deep understanding of IP interfaces--especially PCIe and DDR--you are skilled in leveraging advanced emulation platforms like Zebu to accelerate verification and product development. Your career is marked by a proven ability to deliver robust, production-ready IP through rigorous emulation and verification cycles. You thrive in highly collaborative, matrixed, and international environments, bringing together diverse teams and perspectives to solve complex challenges.

What You'll Be Doing:

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

The Impact You Will Have:

• Enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction.
• Transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures.
• Driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.
• Championing the adoption of best-in-class verification methodologies across the organization.
• Standardizing and optimizing verification workflows to boost efficiency, traceability, and compliance.
• Influencing the next generation of emulation and verification solutions, positioning Synopsys as an industry leader.
• Accelerating time-to-market for high-performance silicon solutions through advanced emulation strategies.

What You'll Need:

• 10-15 years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.
• Demonstrated track record in leading IP product development initiatives with a focus on emulation.
• Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.
• Outstanding communication skills, with the ability to influence and inspire change across diverse teams.
• Adaptability and comfort working in a fast-paced, matrixed, and international environment.

Who You Are:

• A proactive and collaborative problem-solver with a passion for excellence.
• Innovative thinker who embraces change and seeks out opportunities for continuous improvement.
• Strong communicator, able to articulate complex technical concepts to diverse audiences.
• Resilient and adaptable, thriving in dynamic environments and embracing new challenges.
• Committed to mentoring others and fostering an inclusive, team-oriented culture.

The Team You'll Be a Part Of:

You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.

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Your responsibilities will include:

• Verifying and validating OBC systems through various testing activities, including functional testing, system testing, and environmental testing
• Collaborating with cross-functional teams to identify and resolve issues related to OBC systems
• Developing and maintaining test plans, test cases, and test scripts
• Analyzing test results and identifying areas for improvement
• Presenting findings and recommendations to technical teams and project organizations

To succeed in this role, you should have:

• At least 4 years of experience in software testing related to OBC
• A degree in a technical field, such as engineering physics, vehicle engineering, software engineering, or a related field
• Experience with requirement analysis and test planning
• Good knowledge of measurement systems and sensors for software testing
• Programming skills in C/C++ or Python
• Experience with communication protocols such as CAN, CANalyser, CANoe, or FlexRay
• HIL experience with systems such as dSpace or ETAS
• Experience with tools such as INCA, MDA, and MATLAB/Simulink
• Knowledge of standards such as ISO15118, ISO61851, and ISO18246
• A valid driver's license
• Excellent communication skills in Swedish and English

Preferred qualifications include:

• Experience in coordinating roles or cross-functional work
• Background in electrification or e-mobility

If you are a motivated and detail-oriented individual who enjoys working in a fast-paced environment, we encourage you to apply for this exciting opportunity.

At AVL, we offer a competitive salary and benefits package, as well as opportunities for professional growth and development. We are an equal opportunities employer and welcome applications from diverse candidates.

To apply, please submit your resume and cover letter through our website. We look forward to hearing from you!

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You will own a project that ties directly to our critical path avionics development while receiving direct mentorship from Senior Electrical Engineers and other cross-functional leads. Our team looks for engineers that value first principles engineering and extreme ownership.

Responsibilities: Design efforts include circuit design for our embedded system, system integration and verification, environmental test, qualification, and automation, debug, root cause, and drive resolution. Systems must be designed for high-reliability, radiation, aggressive temperature changes, and high-magnitude vibration.

Required qualifications: Have a degree in Electrical Engineering or equivalent, Strong technical fundamentals, Have been part of an engineering team/club, Experience with electrical design software, Altium, KiCAD, etc.

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An Avionics Specialist/Sr. Technician - High Voltage supports the entire Avionics team and other cross-functional teams. It is an essential role spanning design, verification, procurement, manufacturing, and test. You will work specifically with the Power Systems team as they design and verify all X-BAT high voltage power systems. This includes the generator, battery, and all power converters.

Responsibilities:

• Set up and execute test campaigns for custom circuits and sub-systems such as verifying logic levels, voltage rails, and basic circuit functions
• Perform benchtop PCBA testing and debugging
• Support engineers through environmental qualification that includes temperature, vibration, altitude, humidity, etc.
• Design, verify, and deploy simple PCBAs, fixtures, and harnesses
• Assist with the avionics lab design and buildout

Requirements:

• 2+ years working around high voltage, high power systems. Such as 270V and higher
• Experience performing benchtop testing with basic EE equipment (multimeter, oscilloscope, electronic load, thermal chamber, etc.)
• Experience performing PCBA and harness rework
• Proficiency reading and interpreting schematics
• Experience working on multidisciplinary hardware development projects, which can be from an internship, job, club, team, personal project, etc…
• Demonstrated history of showing ownership of project outcomes and delivering exceptional results
• Record of working hard, being a trustworthy teammate, holding yourself and others to high standards, and being kind to others

$36 - $54 an hour

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.
• Demonstrated track record in leading IP product development initiatives with a focus on emulation.
• Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.
• Outstanding communication skills, with the ability to influence and inspire change across diverse teams.
• Adaptability and comfort working in a fast-paced, matrixed, and international environment.

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What you'll do

• Empowering the creation of high-performance silicon chips and software content.

What you need

• Strong technical skills in chip design, verification, and IP integration.

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