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This role supports mission-critical applications including radar, electronic warfare (EW), and communications requiring real-time processing and high-reliability hardware design.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Design, develop, and optimize FPGA-based digital systems for real-time defense applications</li>\n<li>Implement RTL designs (VHDL, Verilog, SystemVerilog) for high-speed data processing</li>\n<li>Perform simulation, synthesis, timing analysis, and timing closure</li>\n<li>Develop and integrate DSP algorithms in hardware (e.g., FFTs, filters, modulation)</li>\n<li>Interface with high-speed ADCs/DACs, RF front ends, and embedded processors</li>\n<li>Support hardware bring-up, debugging, and validation in lab environments</li>\n<li>Collaborate with RF, systems, and software engineers to ensure system performance</li>\n<li>Document designs, requirements, and verification results</li>\n</ul>\n<p><strong>Required Qualifications</strong></p>\n<ul>\n<li>Bachelor’s degree in Electrical or Computer Engineering (or related field)</li>\n<li>Minimum of 2 years&#39; professional experience within the aerospace &amp; defense industry</li>\n<li>Minimum 2 years&#39; experience using FPGA toolchains (Xilinx Vivado, Intel Quartus)</li>\n<li>Proficiency in HDLs (VHDL, Verilog, or SystemVerilog)</li>\n<li>Strong understanding of digital design fundamentals (timing, clock domains, pipelining)</li>\n<li>Experience with simulation/verification tools (ModelSim, Questa, etc.)</li>\n<li>Ability to obtain and maintain a U.S. security clearance</li>\n</ul>\n<p><strong>ITAR Regulations</strong></p>\n<ul>\n<li>To conform to U.S. Government technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicant must be a US Citizen, Green Card holder, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.</li>\n</ul>\n<p><strong>Bonus Points</strong></p>\n<ul>\n<li>Experience with defense systems (radar, EW, communications)</li>\n<li>Knowledge of digital signal processing (DSP) implementation and fixed-point math</li>\n<li>Proficient in scripting languages (Tcl, bash, Python)</li>\n<li>Familiarity with embedded software integration on SoCs</li>\n<li>Experience with high-speed interfaces (JESD204, PCIe, Ethernet, DDR)</li>\n<li>Familiarity with SoC platforms (e.g., Xilinx Zynq, RFSoC)</li>\n<li>Understanding of RF signal chains and systems</li>\n</ul>\n<p><strong>Additional Information</strong></p>\n<p>CX2 is a next-generation defense technology company securing spectrum dominance for the United States and its allies. We build AI-enabled hardware and software platforms to detect, disrupt, and defend the electromagnetic spectrum across land, air, sea, and space. Our systems are deployed in the most contested operational environments in the world. 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You thrive in a collaborative environment and have a keen eye for detail. Your technical expertise is complemented by your ability to communicate effectively and work well within a team. You are self-motivated and enthusiastic about technology and problem-solving. With a minimum of 5 years of experience in design verification, you have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You have a solid understanding of digital and mixed-signal designs and are eager to contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.</p>\n<p>Your key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.</p>\n<p>To be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.</p>\n<p>As a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a global leader in semiconductor design and verification solutions, we enable the world&#39;s most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.</p>\n<p>You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.</p>\n<p>You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&amp;D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you&#39;ll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_44645300-ced","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/hardware-engineering-sr-engineer/44408/93159885392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL simulation","logic synthesis","timing verification tools","DFT architectures","debug tools","SystemVerilog","UVM","Verilog","C/C++","Python","Tcl","EDA tools","VC Auto-Testbench","protocol compliance checking"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:43.007Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL simulation, logic synthesis, timing verification tools, DFT architectures, debug tools, SystemVerilog, UVM, Verilog, C/C++, Python, Tcl, EDA tools, VC Auto-Testbench, protocol compliance checking"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4815342e-ce8"},"title":"Analog Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p>You Are:</p>\n<p>You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Develop and specify SERDES transceiver architectures and sub-blocks based on standards.</li>\n<li>Design, simulate, and verify high-speed analog circuits for optimal power and performance.</li>\n<li>Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.</li>\n<li>Present technical results internally and externally to customers and industry groups.</li>\n<li>Oversee physical layout to address parasitics and reliability concerns.</li>\n<li>Document features and test plans, and support post-silicon analysis and updates.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Advance industry-leading SERDES IP for next-generation SoCs.</li>\n<li>Enhance product differentiation and customer value.</li>\n<li>Streamline design processes for quality and time-to-market.</li>\n<li>Mentor junior team members and share best practices.</li>\n<li>Influence technical direction and innovation at Synopsys.</li>\n<li>Support customer success and product reliability.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.</li>\n<li>Expertise in transistor-level CMOS design and SERDES sub-circuits.</li>\n<li>Proficiency with schematic, layout, and verification tools; SPICE simulators.</li>\n<li>Experience with scripting languages (Verilog-A, TCL, Python, etc.).</li>\n<li>Strong communication and documentation skills.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Technical leader and mentor</li>\n<li>Collaborative and proactive</li>\n<li>Analytical and detail-oriented</li>\n<li>Adaptable and innovative</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. 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(Universal Verification Methodology), SVA (SystemVerilog Assertion), Perl/TCL/Python scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_05702639-4e7"},"title":"ASIC Digital IP Design/Verification, Architect","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Verification Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of HBM or PCIe/CXL and its applications. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Defining and developing ASIC RTL design and verification at both chip and block levels.</li>\n<li>Creating and executing verification plans for complex digital designs, particularly focusing on HBM or PCIe/CXL.</li>\n<li>Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.</li>\n<li>Utilizing advanced verification methodologies and tools to achieve high-quality verification results.</li>\n<li>Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.</li>\n<li>Communicating with internal and external stakeholders to align on project goals and deliverables.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing the reliability and performance of Synopsys&#39; digital verification processes.</li>\n<li>Driving innovations in HBM or PCIe/CXL technology, contributing to the development of cutting-edge semiconductor solutions.</li>\n<li>Improving time-to-market for high-performance silicon chips through efficient verification methodologies.</li>\n<li>Building and nurturing a highly skilled verification team, elevating overall project quality.</li>\n<li>Influencing strategic decisions that shape the future of Synopsys&#39; verification capabilities.</li>\n<li>Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC RTL design and verification.</li>\n<li>In-depth knowledge of HBM or PCIe protocols and their applications.</li>\n<li>Proficiency in advanced verification tools and methodologies.</li>\n<li>Strong problem-solving skills and the ability to work independently.</li>\n<li>Excellent communication skills for effective collaboration with diverse teams.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A team member who encourages innovation.</li>\n<li>A proactive problem solver who thrives in complex environments.</li>\n<li>An effective communicator with the ability to convey technical concepts to a broad audience.</li>\n<li>A team player who values collaboration and diversity.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; verification technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Health &amp; Wellness: Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>Time Away: In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Retirement Plans: Save for your future with our retirement plans that vary by region and country.</li>\n<li>Compensation: Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_05702639-4e7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/reading/asic-digital-ip-design-verification-architect/44408/91458064928","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design and verification","HBM or PCIe protocols and their applications","Advanced verification tools and methodologies","Strong problem-solving skills","Excellent communication skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:07.811Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Reading"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design and verification, HBM or PCIe protocols and their applications, Advanced verification tools and methodologies, Strong problem-solving skills, Excellent communication skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1f955980-d4b"},"title":"Analog & Mixed-Signal Layout Designer","description":"<p>We are seeking a skilled Analog &amp; Mixed-Signal Layout Designer to join our IP Design Group in Lisbon. As a key member of our team, you will be responsible for designing and developing cutting-edge semiconductor solutions. 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For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research.</p>\n<p>Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.</p>\n<p>As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.</li>\n<li>You will be responsible for micro-architecture using sophisticated verification methodologies.</li>\n<li>As a member of our verification team, you&#39;ll understand the design &amp; implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelors or Master’s Degree (or equivalent experience)</li>\n<li>3+ years of relevant verification experience</li>\n<li>Experience in architecting test bench environments for unit level verification</li>\n<li>Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies</li>\n<li>Prior Design or Verification experience of Coherent high-speed interconnects</li>\n<li>Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful</li>\n<li>Strong background developing TB&#39;s from scratch using SV and UVM methodology is desired</li>\n<li>C++ programming language experience, scripting ability and an expertise in System Verilog</li>\n<li>Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)</li>\n<li>Strong debugging and analytical skills</li>\n<li>Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.</li>\n</ul>\n<p>NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you&#39;re creative and autonomous, we want to hear from you.</p>\n<p>You will also be eligible for equity and benefits.</p>\n<p>Applications for this job will be accepted at least until March 13, 2026.</p>\n<p>This posting is for an existing vacancy.</p>\n<p>NVIDIA uses AI tools in its recruiting processes.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4d3cb52-7c4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Verification-Engineer--Coherent-High-Speed-Interconnect_JR2010025","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verification of high-speed coherent interconnect design, architecture and golden models","Micro-architecture using sophisticated verification methodologies","Testbenches, BFMs, Checkers, Monitors","System Verilog","C++ programming language","Design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)"],"x-skills-preferred":["Random stimulus along with functional coverage and assertion-based verification methodologies","Prior Design or Verification experience of Coherent high-speed interconnects","Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI"],"datePosted":"2026-03-09T20:46:52.056Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"US, CA, Santa ClaraUS, MA, WestfordUS, TX, AustinUS, OR, Hillsboro"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verification of high-speed coherent interconnect design, architecture and golden models, Micro-architecture using sophisticated verification methodologies, Testbenches, BFMs, Checkers, Monitors, System Verilog, C++ programming language, Design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), Random stimulus along with functional coverage and assertion-based verification methodologies, Prior Design or Verification experience of Coherent high-speed interconnects, Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f7fbae2c-358"},"title":"Senior Digital Verification Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong> 02/24/2026</p>\n<p><strong><strong>Category</strong> Engineering<strong>Hire Type</strong> Employee<strong>Job ID</strong> 15312<strong>Remote Eligible</strong> No<strong>Date Posted</strong> 02/24/2026</strong></p>\n<p><strong><strong>Senior Digital Verification Engineer</strong></strong></p>\n<p><strong><strong>We Are:</strong></strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong><strong>You Are:</strong></strong></p>\n<p>You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.</p>\n<p><strong><strong>What You’ll Be Doing:</strong></strong></p>\n<ul>\n<li>Developing robust functional verification environments (test benches) for high-speed PHY IPs.</li>\n<li>Creating comprehensive test plans and detailed test cases to ensure thorough coverage.</li>\n<li>Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).</li>\n<li>Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.</li>\n<li>Building architectural and micro-architectural understanding of complex digital design blocks under verification.</li>\n<li>Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.</li>\n<li>Contributing to process improvements and sharing best practices within the team.</li>\n</ul>\n<p><strong><strong>The Impact You Will Have:</strong></strong></p>\n<ul>\n<li>Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.</li>\n<li>Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.</li>\n<li>Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.</li>\n<li>Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.</li>\n<li>Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.</li>\n<li>Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.</li>\n</ul>\n<p><strong><strong>What You’ll Need:</strong></strong></p>\n<ul>\n<li>Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.</li>\n<li>Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.</li>\n<li>Proficiency in Verilog, System Verilog, UVM, and netlist simulations.</li>\n<li>Experience with industry-standard development and verification tools and methodologies.</li>\n<li>Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.</li>\n<li>Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.</li>\n<li>Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.</li>\n<li>Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.</li>\n</ul>\n<p><strong><strong>Who You Are:</strong></strong></p>\n<ul>\n<li>Detail-oriented and analytical thinker with a proactive approach to problem-solving.</li>\n<li>Effective communicator who thrives in collaborative and diverse team environments.</li>\n<li>Adaptable and eager to learn new technologies and methodologies.</li>\n<li>Resourceful and resilient in overcoming technical challenges.</li>\n<li>Committed to fostering inclusion, respect, and continuous improvement within the workplace.</li>\n</ul>\n<p><strong><strong>The Team You’ll Be A Part Of:</strong></strong></p>\n<p>You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.</p>\n<p><strong><strong>Rewards and Benefits:</strong></strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>A peek inside our office</p>\n<p>Po Popal</p>\n<p>Workplace Resources, Sr Director</p>\n<p>Back to nav</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine <strong>around the office</strong> can be like</p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f7fbae2c-358","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/asic-digital-design-sr-engineer/44408/92122114032","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","System Verilog","UVM","netlist simulations","industry-standard development and verification tools and methodologies","pre-silicon verification of complex PHY IPs, ASIC, or SoC designs"],"x-skills-preferred":["formal verification","System Verilog Assertions","code/functional coverage implementation and analysis","scripting languages such as Perl, TCL, and Shell scripting","high-speed interface protocols such as DDR and LPDDR"],"datePosted":"2026-03-09T11:04:17.847Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, System Verilog, UVM, netlist simulations, industry-standard development and verification tools and methodologies, pre-silicon verification of complex PHY IPs, ASIC, or SoC designs, formal verification, System Verilog Assertions, code/functional coverage implementation and analysis, scripting languages such as Perl, TCL, and Shell scripting, high-speed interface protocols such as DDR and LPDDR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f942bce-976"},"title":"Analog Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:\nYou are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognised for your ability to balance technical depth with practical implementation.</p>\n<p>Responsibilities:\nDesigning and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes.\nOwning the full lifecycle of ESD structures—from schematic design, simulation, and layout to silicon qualification and production release.\nLeading and executing I/O development, including I/O ring design, review, and optimisation for performance and robustness.\nDeveloping and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements.\nRunning ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity.\nApplying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality.\nCollaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.</p>\n<p>The Impact You Will Have:\nElevating the reliability and performance of Synopsys&#39; interface IPs, directly influencing the success of global semiconductor customers.\nDriving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry.\nReducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions.\nAccelerating time-to-market for customer products through efficient and high-quality design practices.\nFostering a culture of technical excellence and continuous improvement within the analog design team.\nBuilding strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.</p>\n<p>What You’ll Need:\nProven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness.\nHands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries.\nStrong background in ESD and Latch-Up qualification methodologies, including testchip development and validation.\nProficiency in ESD simulation, ESD network construction, and use of industry-standard tools.\nComprehensive understanding of PERC rules and practical experience with PERC verification tools.\nExperience working with cross-functional teams including foundry, design, and layout groups.</p>\n<p>Who You Are:\nAn analytical thinker with excellent problem-solving skills and keen attention to detail.\nA collaborative team player who values diversity, inclusion, and open communication.\nA proactive learner who stays current with industry trends and emerging technologies.\nAn effective communicator, able to translate complex technical information to diverse audiences.\nA results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work.</p>\n<p>The Team You’ll Be A Part Of:\nYou’ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys’ interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you’ll have the support and opportunities needed to thrive and grow.</p>\n<p>Rewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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The successful candidate will be responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.</li>\n<li>Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.</li>\n<li>Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_962bc801-417","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-engineer-staff/44408/91188491968","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP/SoC verification","Synopsys verification tools"],"x-skills-preferred":["SystemVerilog","UVM","Tcl","Python"],"datePosted":"2026-03-06T07:21:47.519Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP/SoC verification, Synopsys verification tools, SystemVerilog, UVM, Tcl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_44ced76b-29a"},"title":"ASIC Digital Design Engineer, Staff","description":"<p>We are seeking a highly experienced engineering professional to join our team as an ASIC Digital Design Engineer, Staff. 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This role is responsible for driving innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions. 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