Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nTeam:
\nYou'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nThis role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.
\nKey responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.
\nThe successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.
\nAs a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.
\nIf you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.
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\nYou are an accomplished engineering leader with more than a decade of hands-on experience in SoC verification, emulation, and system-level validation. You thrive at the intersection of advanced hardware-assisted verification (HAV) and simulation acceleration (SimXL), bringing a deep understanding of complex SoC architectures, memory subsystems, and high-speed interconnects.
\nArchitecting and leading Hardware-Assisted Verification and Simulation Acceleration solutions for large-scale SoCs and multi-die systems.
\nDriving end-to-end SimXL deployments, including use-case definition, performance optimization, and methodology standardization.
\nDefining and owning system-level verification and acceleration strategies spanning simulation, emulation, and prototyping.
\nBridging gaps between RTL simulation, emulation, and software bring-up to enable early and scalable system validation.
\nLeading complex customer engagements involving HAV platforms, simulation acceleration, and hybrid verification flows.
\nTranslating customer verification challenges into scalable, reusable solution architectures and acting as a technical authority in escalations.
\nDriving innovation in HAV and SimXL methodologies, including automation, reuse, and productivity frameworks leveraging AI/GenAI-assisted approaches.
\nCollaborating with R&D, Product Management, and Applications teams to influence product roadmaps and feature requirements.
\nAccelerate customer verification cycles, enabling earlier software and system bring-up for complex SoC designs.
\nDefine and scale best-in-class HAV and SimXL solutions across strategic accounts, enhancing customer outcomes.
\nDrive measurable improvements in performance, capacity, and debug productivity for verification workflows.
\nShape the future of AI-assisted verification and solution deployment within Synopsys and across the industry.
\nAct as a key technical leader in advancing the organization’s verification acceleration strategy.
\nMentor and empower senior engineers, fostering a culture of innovation and technical excellence.
\nInfluence product direction and solution roadmaps through deep technical insights and customer engagement.
\n10+ years of experience in SoC verification, emulation, or system-level validation.
\nDeep hands-on expertise in Hardware-Assisted Verification, simulation acceleration, and hybrid verification flows.
\nStrong experience with emulation platforms and accelerated simulation environments.
\nSolid understanding of SoC architectures, interconnects, memory subsystems, and software bring-up challenges.
\nProven ability to design and deploy scalable verification solutions for complex designs.
\nExperience with system-level testbenches, transactors, and acceleration frameworks.
\nExposure to GenAI or AI-assisted techniques applied to verification, debug, or solution automation.
\nBackground in high-speed interfaces, memory subsystems, or multi-die architectures.
\nTrack record of creating reusable assets, methodologies, or automation frameworks.
\nExperience influencing product direction or defining solution roadmaps.
\nInnovative thinker with a passion for driving technological advancement and automation.
\nCollaborative leader who mentors and inspires teams across geographies.
\nStrong communicator adept at translating complex technical concepts for diverse audiences.
\nCustomer-focused problem solver with a commitment to delivering impactful solutions.
\nAdaptable and resilient in fast-paced, matrixed environments.
\nDetail-oriented, analytical, and proactive in identifying and addressing challenges.
\nYou will join a dynamic, cross-functional team dedicated to advancing verification acceleration solutions for Synopsys’ strategic customers. The team comprises experts in HAV, simulation acceleration, R&D, product management, and applications engineering, all working collaboratively to define and deploy innovative methodologies.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.
\nWhat You’ll Be Doing:
\nLead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles.
\nResource & Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.
\nFloor planning & Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.
\nSynthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
\nTiming Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.
\nDesign Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.
\nBlock/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.
\nTool Flow Enhancements & Debug: Drive tool flow automation and debugging to improve productivity and design reliability.
\nCollaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development
\nRelease & Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists
\nWhat You’ll Need:
\nThe Impact You Will Have:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\n#LI-NK4
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
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\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our 401(k) and 401(k) matching program.
\nFlexible work arrangements, employee discounts, and more.
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\nWhat you'll do
\nCollaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.
\nWhat you need
\nWhy this matters
\nAdvance high-speed connectivity for enterprise and hyperscale applications worldwide.
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