Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs a Senior RTL/Synthesis Digital Design Engineer, you will be responsible for architecting and developing RTL for high-bandwidth PHY IP and test chips. You will define synthesis constraints, resolve STA and simulation issues, and collaborate with verification, controller, and lab teams.
\nKey responsibilities include:
\nThe ideal candidate will have a strong background in RTL design and synthesis, with expertise in industry tools such as VCS, Verdi, Spyglass, and Synopsys sign-off. You should also have good English communication skills and be able to work effectively in a team.
\nAt Synopsys, we value talented individuals who are passionate about technology and problem-solving. We offer a comprehensive benefits package, including health and wellness programs, time away, family support, and competitive compensation.
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\nBSEE/MS with 7+ years of related experience.
\nExpertise in Emulation and/or Prototyping flows, systems, and methodologies.
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\nUnderstanding of verification concepts and experience with functional simulators.
\nExperience with scripting languages.
\nKnowledge in Simulation flows, Assertion, DPI, and Transactors.
\nComplex problem-solving and debugging skills.
\nStrong communication skills and the ability to interact with customers and peers.
\nKnowledge in synthesis and timing analysis concepts (preferred).
\nFamiliarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).
\nExperience with Xilinx & Altera architecture and toolchains (preferred).
\nUnderstanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).
\nRewards and Benefits:
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\nAs a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.
\nKey responsibilities include:\nPlanning tests, checklists, coverage, and assertion planning.\nCreating detailed verification environments from functional specifications.\nApplying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.\nWriting test cases, checkers, and coverage that implement the verification test plan.\nDebugging simulations, including those of real signals modeled using SystemVerilog for analog.\nPerforming RTL, GLS, and co-simulations and ensuring coverage closure.\nParticipating in technical reviews and contributing actively.\nProviding customer support with the bring-up of IP in customer simulation environments.\nFollowing and improving development processes to ensure high-quality output.
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\nResponsibilities
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\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
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\nJob Description
\nWe are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.
\nWith over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.
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\nDesign Verification Engineer
\nLocation
\nSan Francisco
\nEmployment Type
\nFull time
\nLocation Type
\nHybrid
\nDepartment
\nScaling
\nCompensation
\nThe base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
\nMore details about our benefits are available to candidates during the hiring process.
\nThis role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
\nAbout the Team:
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.
\nIn this role you will:
\nYou might thrive in this role if you have:
\n_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._
\nAbout OpenAI
\nOpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
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