{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/vclp"},"x-facet":{"type":"skill","slug":"vclp","display":"Vclp","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ecffd147-5a5"},"title":"Soc Engineer (synthesis/timing)","description":"<p>Opening. Our team is looking for a SOC engineer to work on ASIC/SOC projects in Synopsys Ho Chi Minh City, District 7.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.</p>\n<ul>\n<li>Synthesis</li>\n<li>LEC</li>\n<li>LDRC</li>\n<li>GCA</li>\n<li>STA</li>\n<li>PTPX</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>2 - 4 years of related experience.</li>\n<li>Good of ASIC/SOC design, synthesis, timing closure.</li>\n<li>Familiar with Synthesis, LEC, STA flow.</li>\n<li>It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.</li>\n<li>Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.</li>\n<li>Familiar with scripting languages, such as TCL, Perl, Python.</li>\n<li>Good English/communication skills and willingness to work with customer.</li>\n<li>BS or MS with an EE or related major</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ecffd147-5a5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing/44408/92181994880","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Synthesis","LEC","STA","PTPX"],"x-skills-preferred":["low-power","high-performance design","advanced nodes under 12nm","RTL","DFT","LDRC","GCA","VCLP","IREM","TCL","Perl","Python"],"datePosted":"2026-03-04T17:10:41.176Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Synthesis, LEC, STA, PTPX, low-power, high-performance design, advanced nodes under 12nm, RTL, DFT, LDRC, GCA, VCLP, IREM, TCL, Perl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_989e07eb-cc7"},"title":"Soc Engineer (synthesis/timing)","description":"<p>Opening. Our team is looking for a SOC engineer to work on ASIC/SOC projects in Synopsys Ho Chi Minh City, District 7.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.</p>\n<ul>\n<li>Synthesis</li>\n<li>LEC</li>\n<li>LDRC</li>\n<li>GCA</li>\n<li>STA</li>\n<li>PTPX</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>6-12 years of related experience.</li>\n<li>Good of ASIC/SOC design, synthesis, timing closure.</li>\n<li>Familiar with Synthesis, LEC, STA flow.</li>\n<li>It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.</li>\n<li>Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.</li>\n<li>Familiar with scripting languages, such as TCL, Perl, Python.</li>\n<li>Good English/communication skills and willingness to work with customer.</li>\n<li>BS or MS with an EE or related major</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_989e07eb-cc7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing/44408/92181994832","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Synthesis","LEC","STA","PTPX"],"x-skills-preferred":["low-power","high-performance design","advanced nodes under 12nm","RTL","DFT","LDRC","GCA","VCLP","IREM","TCL","Perl","Python"],"datePosted":"2026-03-04T17:09:47.992Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Synthesis, LEC, STA, PTPX, low-power, high-performance design, advanced nodes under 12nm, RTL, DFT, LDRC, GCA, VCLP, IREM, TCL, Perl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cc644248-b48"},"title":"Physical Design Sr Staff Engineer - PnR","description":"<p>Opening. This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<ul>\n<li>Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.</li>\n</ul>\n<ul>\n<li>Drive flow development and optimization to improve design quality and predictability.</li>\n</ul>\n<ul>\n<li>Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).</li>\n</ul>\n<ul>\n<li>Contribute to the adoption and integration of advanced technologies and tool features in design implementation.</li>\n</ul>\n<ul>\n<li>Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.</li>\n</ul>\n<ul>\n<li>Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.</p>\n<p>Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.</p>\n<p>Enhance the predictability and simplicity of implementation processes for complex interface IPs.</p>\n<p>Accelerate the adoption of next-generation design technologies and tools across the industry.</p>\n<p>Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.</p>\n<p>Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.</p>\n<p><strong>What you’ll need</strong></p>\n<ul>\n<li><strong>Minimum 7years</strong> of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why you’ll love this role</strong></p>\n<ul>\n<li>Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.</li>\n</ul>\n<ul>\n<li>Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.</li>\n</ul>\n<ul>\n<li>Participate in professional development opportunities to enhance your skills and expertise.</li>\n</ul>\n<ul>\n<li>Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"}]}