{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/vc"},"x-facet":{"type":"skill","slug":"vc","display":"Vc","count":58},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5c3a0cd8-d2d"},"title":"Mixed-Signal AMS Co-Simulation Verification Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate engineer who thrives at the intersection of analog and digital design. With a keen analytical mindset and a collaborative spirit, you are motivated by solving complex technical challenges that drive the future of connectivity.</p>\n<p>Whether you are an ambitious new graduate eager to launch your career or an experienced engineer ready to deepen your expertise, you are excited by the opportunity to work on advanced Ethernet and PCIe SERDES IP deployed in the most cutting-edge SoCs.</p>\n<p>You value not only technical mastery but also teamwork, mentorship, and the continuous pursuit of innovation.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.</li>\n</ul>\n<ul>\n<li>Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.</li>\n</ul>\n<ul>\n<li>Perform functional verification of SERDES blocks, including TX/RX data paths, equalization algorithms, adaptation loops, CDR behavior, PLL locking, and analog/digital interactions.</li>\n</ul>\n<ul>\n<li>Debug and resolve simulation failures across analog, digital, and mixed-signal domains, ensuring root-cause analysis and timely solutions.</li>\n</ul>\n<ul>\n<li>Conduct design reliability checks such as electromigration (EM), IR analysis, and device-level stress evaluations to ensure silicon robustness.</li>\n</ul>\n<ul>\n<li>Collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.</li>\n</ul>\n<ul>\n<li>Drive quality and reliability in silicon that powers AI, automotive, cloud, and mobile applications at massive scale.</li>\n</ul>\n<ul>\n<li>Advance the state-of-the-art in AMS co-simulation methodologies, influencing future verification flows and processes.</li>\n</ul>\n<ul>\n<li>Contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.</li>\n</ul>\n<ul>\n<li>Foster cross-disciplinary collaboration and technical knowledge sharing across analog, digital, and architecture teams.</li>\n</ul>\n<ul>\n<li>Enhance Synopsys’ reputation as the premier provider of high-speed connectivity IP through engineering excellence and innovation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or master’s degree in electrical engineering or a related field (Master’s preferred for new grads).</li>\n</ul>\n<ul>\n<li>Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).</li>\n</ul>\n<ul>\n<li>Exposure to Verilog/System Verilog and AMS concepts or circuit design (coursework, labs, or hands-on experience).</li>\n</ul>\n<ul>\n<li>Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.</li>\n</ul>\n<ul>\n<li>Proficiency with System Verilog/UVM and AMS tools (HSPICE, XA, Custom Sim, VCS).</li>\n</ul>\n<ul>\n<li>Ability to debug analog-digital interactions and define robust verification strategies; experience mentoring is a plus for senior candidates.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical and detail-oriented, with strong problem-solving and debugging skills.</li>\n</ul>\n<ul>\n<li>Effective communicator who collaborates well in multidisciplinary and multicultural teams.</li>\n</ul>\n<ul>\n<li>Self-motivated and driven to deliver high-quality results in a fast-paced environment.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, with a passion for continuous improvement and innovation.</li>\n</ul>\n<ul>\n<li>Proactive in seeking feedback, sharing knowledge, and mentoring others when possible.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join the Synopsys IPG Co-Simulation (COSIM) team, a group of expert engineers at the leading edge of mixed-signal verification. The team works in close partnership with analog, digital, modeling, and architecture groups across North America, Europe, and Asia. Together, you drive engineering excellence and deliver high-impact IP that powers the world’s most advanced silicon solutions. You’ll enjoy a collaborative, supportive environment where innovation, technical rigor, and teamwork are at the core of everything we do.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Principal ASIC Digital Design Engineer, you are a trailblazer who thrives in dynamic environments and is passionate about pushing the boundaries of semiconductor technology. You bring a deep understanding of digital design methodologies, paired with a creative approach to problem-solving and a tenacious drive to deliver robust solutions.</p>\n<p>You are not only technically proficient in RTL coding and digital verification, but you also bring a practical understanding of synthesis flows, DFT, and production testing. Your scripting skills in Shell, Perl, Python, and TCL enable you to automate tasks and streamline development workflows.</p>\n<p>You will design and verify advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions. You will develop RTL code, model analog blocks, and craft complex system-level testbenches in Verilog to validate functionality and performance.</p>\n<p>You will collaborate with Application Engineers, Analog, and P&amp;R teams to resolve technical issues, provide customer support, and ensure successful product deployment. You will mentor junior engineers, foster knowledge sharing, and contribute to a culture of innovation and continuous improvement.</p>\n<p>You will drive the development of next-generation SerDes solutions, powering high-speed data transmission in cutting-edge applications. You will enable customers to achieve superior performance and reliability in their semiconductor products through innovative digital design.</p>\n<p>You will need a Bachelor&#39;s or Master&#39;s degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification. You must be familiar with Verilog and VCS. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. Join us to transform the future through technological innovation.</p>\n<p>You are a skilled ASIC Digital Design Engineer with over 5 years of design verification experience. You thrive in collaborative settings, communicate clearly, and have a strong technical foundation in simulation tools and scripting. Driven by curiosity and a passion for technology, you’re eager to make an impact on Data Center, AI/ML, and 5G solutions.</p>\n<p>Developing and validating high-speed interface IP in digital/mixed-signal environments. Planning tests, coverage, and assertions for robust verification. Building verification environments from specifications. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p>You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. 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Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.</p>\n<p>The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&amp;D teams by providing expertise and driving cross-functional collaboration.</p>\n<p>What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB (PCIe preferred) Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.</p>\n<p>Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.</p>\n<p>The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&amp;D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.</p>\n<p>Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. 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Here, everyone is part of the story. Part of a community that connects across the globe. A place where creativity thrives, new perspectives are invited, and ideas matter. A team where everyone makes play happen.</p>\n<p>We are EA IT Electronic Arts Information Technology (EAIT) group keeps our employees and business operations connected globally. We bring creative technology services to all areas, keeping everyone creative, collaborative and productive. Our team ensures better play across all of EA.</p>\n<p>The role is Hybrid in Vancouver (3 days in office).</p>\n<p>This exciting role offers the opportunity to architect and enhance software applications used to create games, at an Enterprise level. You will have the chance to work with game teams across the entire organisation, including FIFA, Madden, Battlefield and Battlefront, and central teams such as Frostbite and Origin. You have a strong focus on innovation and leverage a deep technical experience. You will contribute to the roadmap, architecture and technical and business delivery of several software applications. We require strong soft skills to collaborate with individual game teams, to gain adoption and enhance these solutions.</p>\n<p>Enterprise-level solution experience:</p>\n<ul>\n<li>Contributes across an entire project lifecycle, which includes gathering requirements from key technical leaders, creating a vision and strategy, presenting to leadership, developing the product roadmap, ensuring projects are on track and completed on time, managing communication with all stakeholders, and collaborating with the development team</li>\n<li>Participate in all aspects of the proposed service end-to-end, including design, implementation, support, vendor relations and customer interaction</li>\n<li>Manage the relationship with vendors if applicable, including sourcing, evaluation, and escalation</li>\n</ul>\n<p>Coding, language, architectural design, testing and support:</p>\n<ul>\n<li>Develop solutions as part of the game development application services portfolio that are modular, portable, testable and reliable</li>\n<li>Drive usage of coding best practices;Participates in code reviews and provides constructive feedback on design and implementation to help others improve coding skills</li>\n<li>Oversee support and administrative actions related to the installation and maintenance of production systems, while also engineering solutions that require minimal support</li>\n</ul>\n<p>Leverage the cloud where appropriate,using automation, cloud computing and configuration as code</p>\n<p><strong>Job qualifications and requirements</strong></p>\n<ul>\n<li>8 + years of experience developing Enterprise level solutions</li>\n<li>8+ years of source control management experience including advanced concepts like branching strategies and developer workflows</li>\n<li>8+ years of experience with automated build pipelines, continuous integration, and continuous deployment</li>\n<li>8+ years of experience working with standard Microsoft.NET web development tools including C#, ASP.NET MVC, HTML 5+, CSS3+, JavaScript, WCF, REST API, jQuery</li>\n<li>8+ years of experience in database development</li>\n<li>3+ years of experience with virtualization and cloud platforms (e.g. VMware, Azure, or AWS); Preferred AWS or Azure certifications</li>\n</ul>\n<p><strong>Additional requirements</strong></p>\n<ul>\n<li>Experience with different project management models (specifically Agile)</li>\n<li>Excellent verbal and written communication, and customer service skills</li>\n<li>Experience developing automation solutions using tools like Chef, Puppet, Ansible, or Terrafort</li>\n<li>Experience in container technologies like Docker and Kubernetes</li>\n<li>Experience with Artificial Intelligence and Machine Learning</li>\n</ul>\n<p><strong>Pay Transparency - North America</strong></p>\n<p><strong>COMPENSATION AND BENEFITS</strong> The ranges listed below are what EA in good faith expects to pay applicants for this role in these locations at the time of this posting. If you reside in a different location, a recruiter will advise on the applicable range and benefits. Pay offered will be determined based on a number of relevant business and candidate factors (e.g. education, qualifications, certifications, experience, skills, geographic location, or business needs).</p>\n<p><strong>PAY RANGES</strong> \\\\\\<em> British Columbia (depending on location e.g. Vancouver vs. Victoria) \\\\</em>$141,400 - $204,400 CAD</p>\n<p>Pay is just one part of the overall compensation at EA.</p>\n<p>For Canada, we offer a package of benefits including vacation (3 weeks per year to start), 10 days per year of sick time, paid top-up to EI/QPIP benefits up to 100% of base salary when you welcome a new child (12 weeks for maternity, and 4 weeks for parental/adoption leave), extended health/dental/vision coverage, life insurance, disability insurance, retirement plan to regular full-time employees. Certain roles may also be eligible for bonus and equity.</p>\n<p><strong>_About Electronic Arts_</strong> We’re proud to have an extensive portfolio of games and experiences, locations around the world, and opportunities across EA. We value adaptability, resilience, creativity, and curiosity. From leadership that brings out your potential, to creating space for learning and experimenting, we empower you to do great work and pursue opportunities for growth.</p>\n<p>We adopt a holistic approach to our benefits programs, emphasizing physical, emotional, financial, career, and community wellness to support a balanced life. Our packages are tailored to meet local needs and may include healthcare coverage, mental well-being support, retirement savings, paid time off, family leaves, complimentary games, and more. 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You will create solution architectures to incorporate custom, COTS, and packaged applications together with integrations with products such as Slack, JIRA, Perforce, and GitLab. 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We offer a holistic approach to our benefits programs, emphasizing physical, emotional, financial, career, and community wellness to support a balanced life. Our packages are tailored to meet local needs and may include healthcare coverage, mental well-being support, retirement savings, paid time off, family leaves, complimentary games, and more. We nurture environments where our teams can always bring their best to what they do.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4d14aef8-562","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Electronic Arts","sameAs":"https://jobs.ea.com","logo":"https://logos.yubhub.co/jobs.ea.com.png"},"x-apply-url":"https://jobs.ea.com/en_US/careers/JobDetail/C-Software-Engineer/213794","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Microsoft .NET (C#)","ASP.NET/MVC","WCF/Web API/REST","JavaScript frameworks","HTML+CSS3+Javascript","Microsoft SQL Server","ADO.NET","ORMs","OData","Agile","DevOps","PaaS","IaaS","AWS","Azure"],"x-skills-preferred":[],"datePosted":"2026-04-24T13:16:06.524Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bucharest"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Microsoft .NET (C#), ASP.NET/MVC, WCF/Web API/REST, JavaScript frameworks, HTML+CSS3+Javascript, Microsoft SQL Server, ADO.NET, ORMs, OData, Agile, DevOps, PaaS, IaaS, AWS, Azure"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_36515b73-0a8"},"title":"Senior Software Engineer","description":"<p>Electronic Arts creates next-level entertainment experiences that inspire players and fans around the world. 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We partner across the business to allocate and deploy our resources for the highest-impact outcomes. Within Strategic Finance, the B2B team focuses on the financial performance of our products and GTM functions, ensuring tight alignment between financial objectives and company strategy. We partner with leaders across Product, GTM, Research, Partnerships, and Operations to:</p>\n<ul>\n<li>Drive operational planning, financial forecasting, and performance management.</li>\n</ul>\n<ul>\n<li>Provide decision-quality insights on product and financial performance to inform strategic resource allocation.</li>\n</ul>\n<ul>\n<li>Build the “0→1” financial foundations required to scale and accelerate growth.</li>\n</ul>\n<p><strong>About the Role</strong></p>\n<p>We are hiring a senior leader in B2B Strategic Finance to build and scale a new pillar within our finance organization. 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We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<p>_Drive B2B finance scale and rigor_</p>\n<ul>\n<li>Build and scale core financial infrastructure across the B2B business, including forecasting methodology, variance management, and performance narratives that drive accountability and decision-making velocity.</li>\n</ul>\n<ul>\n<li>Lead consolidated planning across revenue, gross margin (including compute), and opex for annual budget, forecasts, regular business reviews, and long-range planning.</li>\n</ul>\n<ul>\n<li>Establish durable management reporting: KPI definitions, dashboards, month-end/quarter-end deliverables, and exec-ready readouts.</li>\n</ul>\n<ul>\n<li>Partner with Corporate FP&amp;A, Accounting, and Finance Systems/Data to evolve processes and controls toward public-company standards.</li>\n</ul>\n<p>_Be a strategic partner to B2B leadership_</p>\n<ul>\n<li>Lead forecasting and business reviews across usage, revenue, and gross margin, including scenario modeling tied to product &amp; engineering constraints and compute economics.</li>\n</ul>\n<ul>\n<li>Holistically manage the financial performance and unit economics of our B2B products.</li>\n</ul>\n<ul>\n<li>Partner with Compute and Engineering on margin optimization and quantifying trade-offs across product experience, cost, and scalability.</li>\n</ul>\n<p>_Stand up emerging high-stakes, strategic initiatives_</p>\n<ul>\n<li>Support high-priority strategic projects from 0 →1, partnering closely with leadership and adjacent B2B finance teams to stand up the initial financial frameworks, decision support, and performance tracking.</li>\n</ul>\n<ul>\n<li>Translate complex problems into clear executive narratives (trade-offs, risk/return, and strategic recommendations).</li>\n</ul>\n<ul>\n<li>Transition emerging initiatives to long-term owners as they scale.</li>\n</ul>\n<p><strong>You might thrive in this role if you have:</strong></p>\n<ul>\n<li>12+ years of progressive experience in Strategic Finance, Product Finance, Corporate FP&amp;A, Corporate Development, Investment Banking/PE/VC, or Management Consulting,plus meaningful operating experience in a fast-scaling technology company.</li>\n</ul>\n<ul>\n<li>Deep familiarity with B2B subscription and consumption / usage-based business models and the ability to reason fluently about unit economics and margin drivers (including compute-driven COGS).</li>\n</ul>\n<ul>\n<li>Expert modeling and analytical skills (multi-scenario P&amp;L and cash flow modeling, sensitivity analysis, and strong financial judgment).</li>\n</ul>\n<ul>\n<li>A strong ability to critically evaluate opportunities and risks in financials; attention to detail and accuracy in financial reporting, budgeting, and analysis.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to bring structure to ambiguity, lead senior stakeholders through trade-offs, and drive crisp decisions in high-uncertainty environments.</li>\n</ul>\n<ul>\n<li>Exceptional communication and executive presence,strong at building Board/exec-ready narratives from complex, cross-functional inputs.</li>\n</ul>\n<ul>\n<li>A “roll up your sleeves” mindset, high ownership, and deep curiosity about AI and how it will reshape enterprises, industries, and institutions.</li>\n</ul>\n<ul>\n<li>Experience with SQL or a willingness to learn.</li>\n</ul>\n<ul>\n<li>A passion for helping build world-class finance teams and driving business and financial outcomes.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p>We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.</p>\n<p>For additional information, please see [OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement](https://cdn.openai.com/policies/eeo-policy-statement.pdf).</p>\n<p>Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. 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Today the company runs one of the world’s largest networks that powers millions of websites and other Internet properties for customers ranging from individual bloggers to SMBs to Fortune 500 companies.</p>\n<p>You will be responsible for driving new business with fast-growing, cloud-native, VC-backed technology companies across the UK &amp; Ireland, working closely with founders and senior technical leaders. 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We’re a highly ambitious, large-scale technology company with a soul. Fundamental to our mission to help build a better Internet is protecting the free and open Internet.</p>\n<p>Project Galileo: Since 2014, we&#39;ve equipped more than 2,400 journalism and civil society organizations in 111 countries with powerful tools to defend themselves against attacks that would otherwise censor their work, technology already used by Cloudflare’s enterprise customers--at no cost. Athenian Project: In 2017, we created the Athenian Project to ensure that state and local governments have the highest level of protection and reliability for free, so that their constituents have access to election information and voter registration. Since the project, we&#39;ve provided services to more than 425 local government election websites in 33 states. 1.1.1.1: We released 1.1.1.1 to help fix the foundation of the Internet by building a faster, more secure and privacy-centric public DNS resolver. This is available publicly for everyone to use - it is the first consumer-focused service Cloudflare has ever released. Here’s the deal - we don’t store client IP addresses never, ever. We will continue to abide by our privacy commitment and ensure that no user data is sold to advertisers or used to target consumers.</p>\n<p>Sound like something you’d like to be a part of? We’d love to hear from you!</p>\n<p>This position may require access to information protected under U.S. export control laws, including the U.S. Export Administration Regulations. Please note that any offer of employment may be conditioned on your authorization to receive software or technology controlled under these U.S. export laws without sponsorship for an export license.</p>\n<p>Cloudflare is proud to be an equal opportunity employer. We are committed to providing equal employment opportunity for all people and place great value in both diversity and inclusiveness. All qualified applicants will be considered for employment without regard to their, or any other person&#39;s, perceived or actual race, color, religion, sex, gender, gender identity, gender expression, sexual orientation, national origin, ancestry, citizenship, age, physical or mental disability, medical condition, family care status, or any other basis protected by law. We are an AA/Veterans/Disabled Employer. Cloudflare provides reasonable accommodations to qualified individuals with disabilities. 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Trusted by 65,000+ companies in 160+ countries, Carta’s platform of software and services lays the groundwork so you can build, invest, and scale with confidence.</p>\n<p><strong>The Team You’ll Work With</strong></p>\n<p>Carta is looking for an Integrated Marketing Manager to join our Asia-Pacific, Middle East &amp; Africa (APAC &amp; MEA) marketing team, based in Hong Kong. Carta expanded into Asia Pacific in 2021, with Singapore as our regional hub. We are now opening our office in Hong Kong and building a local, on-the-ground team to support founders, fund managers and investors across Hong Kong and the Greater Bay Area.</p>\n<p><strong>The Problems You’ll Solve</strong></p>\n<ul>\n<li>Build Carta’s Brand from the Ground Up in Hong Kong: Establish Carta’s local marketing presence in a new market, ensuring strong brand awareness, credibility, and trust within the startup, VC, PE and private markets ecosystem. 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This is an opportunity to do career-defining work.</p>\n<p>In this role, you will be tasked with providing hands-on implementation and deployment services to our customers. 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As a Staff Backend Engineer, you will define the technical direction of a new VDC identity ecosystem and set the standard for how we build it.</p>\n<p>This role demands deep technical expertise in backend architecture and the ability to influence decisions across the team and adjacent engineering groups. You will thrive in a fast-paced, zero-to-one environment, cutting through ambiguity to drive product-market fit.</p>\n<p>In practice, that means using AI tools for architectural reasoning and design review, generating and validating test coverage, accelerating code review cycles, and helping engineers build judgment about when AI output is trustworthy and when it isn&#39;t.</p>\n<p>You&#39;ll define what &#39;good&#39; looks like here and bring the team along. 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Applications will be reviewed on a rolling basis.</p>\n<p>The annual compensation range for this role is listed below.</p>\n<p>For sales roles, the range provided is the role’s On Target Earnings (“OTE”) range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role.</p>\n<p>Annual Salary: £160,000-£160,000 GBP</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_04a285ad-ad6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://www.anthropic.com/","logo":"https://logos.yubhub.co/anthropic.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/5093547008","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"£160,000-£160,000 GBP","x-skills-required":["customer marketing","B2B customer marketing","EMEA","startups","AI","Claude","customer narratives","case studies","technical deep-dives","founder testimonials","thought leadership","video content","EMEA startup customer segmentation","tiering framework","advocacy prioritization","resource allocation","high-touch programming","scalable customer marketing initiatives","developer and founder community","regional market dynamics","key moments programming","founder dinners","customer speaking opportunities","technical workshops","startup showcase events","customer advisory programs","highest-value accounts","influential founders","strategic startup accounts","VC portfolio engagement","co-marketing opportunities","portfolio company success stories","regional programming calendar","customer advocacy activities","strategic account engagement","EMEA startup ecosystem","founder and technical leaders","powerful advocates","reference points","technical audiences","authentic founder stories","technical implementation deep-dives","developer-focused case studies"],"x-skills-preferred":[],"datePosted":"2026-04-18T15:37:10.578Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"London, UK"}},"employmentType":"FULL_TIME","occupationalCategory":"Marketing","industry":"Technology","skills":"customer marketing, B2B customer marketing, EMEA, startups, AI, Claude, customer narratives, case studies, technical deep-dives, founder testimonials, thought leadership, video content, EMEA startup customer segmentation, tiering framework, advocacy prioritization, resource allocation, high-touch programming, scalable customer marketing initiatives, developer and founder community, regional market dynamics, key moments programming, founder dinners, customer speaking opportunities, technical workshops, startup showcase events, customer advisory programs, highest-value accounts, influential founders, strategic startup accounts, VC portfolio engagement, co-marketing opportunities, portfolio company success stories, regional programming calendar, customer advocacy activities, strategic account engagement, EMEA startup ecosystem, founder and technical leaders, powerful advocates, reference points, technical audiences, authentic founder stories, technical implementation deep-dives, developer-focused case studies","baseSalary":{"@type":"MonetaryAmount","currency":"GBP","value":{"@type":"QuantitativeValue","minValue":160000,"maxValue":160000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_747bfce2-c30"},"title":"Senior Staff Propulsion Engineer (TVC) (X-BAT)","description":"<p>We&#39;re seeking a Propulsion Engineer to serve as the Responsible Engineer (RE) for the Thrust Vector Control (TVC) system on X-BAT. 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The role involves developing our web server, REST APIs, and product core by writing clean and solid code that interacts with our other services and components.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop new product features that leverage the network model to help users visualise their network, understand how it behaves, see how it has evolved, answer specific questions, and plan changes</li>\n<li>Design the data model for new product features</li>\n<li>Propose and implement REST APIs to support the Forward Networks web application and to publish to customers</li>\n<li>Constructively review product designs, technical design documents, and code changes</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>At least 5+ years of full lifecycle software development experience</li>\n<li>Expertise in Java (version 17 or above)</li>\n<li>Considerable experience with a dependency injection framework such as Guice or Spring and a talent for writing (and refactoring) code for testability</li>\n<li>Deep understanding of REST API design fundamentals and best practices</li>\n<li>Proficiency in SQL and relational database schema design</li>\n<li>Strong object-oriented design and development skills</li>\n<li>Familiarity with the principles of functional programming</li>\n<li>Good communication skills</li>\n</ul>\n<p>Nice to have:</p>\n<ul>\n<li>Experience with the Spring Web MVC framework or Spring Boot</li>\n<li>Some experience with other JVM languages such as Groovy, Kotlin, or Scala</li>\n<li>Some experience with TypeScript or modern JavaScript</li>\n</ul>\n<p>This position is a regular, full-time opportunity with Forward Networks in Bangalore, India.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c33d7101-c91","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Forward Networks","sameAs":"https://www.forwardnetworks.com/","logo":"https://logos.yubhub.co/forwardnetworks.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/forwardnetworks/jobs/6668096003","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Java","Dependency Injection Framework","REST API Design","SQL","Relational Database Schema Design","Object-Oriented Design","Functional Programming"],"x-skills-preferred":["Spring Web MVC","Groovy","Kotlin","Scala","TypeScript","Modern JavaScript"],"datePosted":"2026-04-17T12:36:07.780Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Java, Dependency Injection Framework, REST API Design, SQL, Relational Database Schema Design, Object-Oriented Design, Functional Programming, Spring Web MVC, Groovy, Kotlin, Scala, TypeScript, Modern JavaScript"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a3f857d-37c"},"title":"Customer Success Engineer","description":"<p>We are seeking a Customer Success Engineer to join our team in Japan. As a Customer Success Engineer, you will be responsible for providing world-class post-sales technical leadership to our client base.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Provide advice and guidance as the Forward Networks subject matter expert to ensure successful ongoing usage and adoption of our technologies.</li>\n<li>Take ownership of post-sales technical issues, working with cross-functional teams to document problem resolution steps and troubleshooting procedures.</li>\n<li>Walk customers through the various stages of adoption with Forward Networks Platform.</li>\n<li>Work directly with our internal Product Management, Engineering, Sales and Marketing teams.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Must be fluent in Japanese and English, both written and spoken.</li>\n<li>B.S. Computer Science or equivalent educational experience.</li>\n<li>5+ years of customer-facing experience in a post-sales engineer role for a networking company, relevant software vendor, or as a network engineer for a large enterprise, service provider or Governmental agencies.</li>\n</ul>\n<p>Experience:</p>\n<ul>\n<li>Must be fluent in Japanese and English, both written and spoken.</li>\n<li>Strong understanding of Networking and Security fundamentals.</li>\n<li>Experience in working with multiple Network vendors (e.g. A10, Arista, Cisco, F5, Fortinet, Juniper, Palo Alto Networks etc.).</li>\n<li>Strong verbal and written communications skills with a focus on needs analysis, positioning, business justification, and closing techniques; Superior presentation skills.</li>\n<li>Excellent analytical &amp; problem-solving skills, combined with the ability to provide quick resolution to problems.</li>\n<li>Demonstrable success in thinking strategically, executing tactically while providing consistent and high levels of customer satisfaction and retention in a fast-paced environment.</li>\n</ul>\n<p>Highly Desired:</p>\n<ul>\n<li>One or more of the following certificates: CCIE, JNCIE or VCDX.</li>\n<li>Experience in working for a startup company.</li>\n<li>Working knowledge of API driven workflows and scripting languages (Python, bash, jq, graphql, etc).</li>\n</ul>\n<p>Candidates will work remotely with 10-20% travel requirement for customer and internal meetings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a3f857d-37c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Forward Networks","sameAs":"https://www.forwardnetworks.com/","logo":"https://logos.yubhub.co/forwardnetworks.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/forwardnetworks/jobs/7617331003","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Japanese","English","Computer Science","Networking","Security","API driven workflows","Scripting languages"],"x-skills-preferred":["CCIE","JNCIE","VCDX","Startup experience","Python","bash","jq","graphql"],"datePosted":"2026-04-17T12:34:49.740Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Japan"}},"jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Japanese, English, Computer Science, Networking, Security, API driven workflows, Scripting languages, CCIE, JNCIE, VCDX, Startup experience, Python, bash, jq, graphql"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6e05a506-42b"},"title":"Customer Success Engineer","description":"<p>Forward Networks is transforming how the world&#39;s most complex networks are managed and secured. We&#39;re looking for a Customer Success Engineer to join our Enterprise team, providing world-class post-sales technical leadership to our client base and working onsite at our customer locations in NY.</p>\n<p>Responsibilities:\nProvide advice and guidance as the Forward Networks subject matter expert to ensure successful ongoing usage and adoption of our technologies.\nTake ownership of post-sales technical issues, working with cross-functional teams to document problem resolution steps and troubleshooting procedures.\nWalk customers through the various stages of adoption with Forward Networks Platform.\nWork directly with our internal Product Management, Engineering, Sales, and Marketing teams.\nSome travel (10%)</p>\n<p>Requirements:\nB.S. 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For candidates who receive an offer at the posted level, the starting base salary + bonus is expected to be between $165,000/yr to $190,000/yr. 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The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.</p>\n<p>Rewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>A peek inside our office</p>\n<p>Benefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. 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You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. 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integration.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead customer deployments of VCS simulation technology, working closely with field teams and R&amp;D to ensure successful adoption and integration.</li>\n<li>Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.</li>\n<li>Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.</li>\n<li>Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.</li>\n<li>Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.</li>\n<li>Interface directly with customers, product validation, and R&amp;D teams to propose solutions and suggest improvements in implementation and validation processes.</li>\n<li>Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and 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problem-solving abilities.</li>\n<li>Adaptable and open to travel, eager to learn and grow in a fast-paced environment.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&amp;D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a4490a5f-125","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/sr-staff-application-engineer-vcs-simulation/44408/93232526272","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["verification technologies","simulation","UVM","SVA","LRM","HDL languages","Verilog","VHDL","SystemVerilog","digital design fundamentals","advanced scripting skills","Perl","TCL","Make","Shell","UNIX environments","Synopsys EDA tools","SpyGlass","VC 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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Designing and implementing verification environments to ensure the correctness of Interface IP protocols.</li>\n<li>Creating and executing detailed test plans to verify complex ASIC designs.</li>\n<li>Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.</li>\n<li>Collaborating with design and architecture teams to identify and fix bugs.</li>\n<li>Performing functional coverage analysis and driving coverage closure.</li>\n<li>Mentoring and guiding junior verification engineers in best practices and methodologies.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.</li>\n<li>Enhancing the robustness and efficiency of our verification processes and methodologies.</li>\n<li>Contributing to the successful launch of Interface IP products, impacting various industries.</li>\n<li>Driving innovation and excellence within the verification team.</li>\n<li>Improving the overall performance and functionality of Synopsys&#39; IP offerings.</li>\n<li>Fostering a culture of continuous improvement and technical excellence.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.</li>\n<li>Proficiency in SystemVerilog and UVM methodologies.</li>\n<li>Strong understanding of digital design and verification concepts.</li>\n<li>Experience with simulation tools such as VCS, ModelSim, or similar.</li>\n<li>Excellent problem-solving skills and attention to detail.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Detail-oriented with a strong analytical mindset.</li>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n<li>Collaborative team player who thrives in a dynamic environment.</li>\n<li>Proactive and self-motivated, with a commitment to continuous learning.</li>\n<li>Mentor and leader, capable of guiding and developing junior engineers.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>Get an idea of what your daily routine <strong>around the office</strong> can be like</strong></p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_de112d07-e65","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-design-principal-engineer/44408/91802916768","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert","PLL , data converters and SERDES design","mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction","circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes","Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology","silicon test and debug experts to advance quality through Sim2Sil correlation","Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits","Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity ","RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:28.077Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert, PLL , data converters and SERDES design, mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction, circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes, Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology, silicon test and debug experts to advance quality through Sim2Sil correlation, Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits, Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity , RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3b0726c6-2a1"},"title":"Senior Applications Engineer – Verification","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.</p>\n<p>Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.</p>\n<p>Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.</p>\n<p>Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.</p>\n<p>Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.</p>\n<p>You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3b0726c6-2a1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/application-engineering-sr-engineer/44408/92040418272","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital design","HDLs (Verilog, VHDL)","System Verilog","dynamic simulation verification","Synopsys EDA tools (VCS, Verdi)","UNIX environments","scripting languages (Tcl)"],"x-skills-preferred":["verification methodologies","HDL/HVL technologies","dynamic simulation"],"datePosted":"2026-03-09T11:04:40.752Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"digital design, HDLs (Verilog, VHDL), System Verilog, dynamic simulation verification, Synopsys EDA tools (VCS, Verdi), UNIX environments, scripting languages (Tcl), verification methodologies, HDL/HVL technologies, dynamic simulation"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4e4a0dc-158"},"title":"DFT, Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15995</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff ASIC Digital Design Engineer</li>\n</ul>\n<ul>\n<li>Staff DFT Engineer</li>\n</ul>\n<ul>\n<li>Staff SoC Testability Engineer</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Define and implement DFT architecture for IP designs</li>\n</ul>\n<ul>\n<li>Perform SCAN insertion and ATPG simulation</li>\n</ul>\n<ul>\n<li>Analyze and improve test coverage</li>\n</ul>\n<ul>\n<li>Develop STA DFT timing constraints</li>\n</ul>\n<ul>\n<li>Prepare DFT integration guidelines for SoC</li>\n</ul>\n<ul>\n<li>Conduct quality checks and FMEDA/DFMEA analysis</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhance product reliability and quality</li>\n</ul>\n<ul>\n<li>Support functional safety standards (ISO26262, FUSA)</li>\n</ul>\n<ul>\n<li>Streamline SoC integration</li>\n</ul>\n<ul>\n<li>Reduce debug cycles and time-to-market</li>\n</ul>\n<ul>\n<li>Mentor peers</li>\n</ul>\n<ul>\n<li>Drive innovation in test methodology</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics or related field</li>\n</ul>\n<ul>\n<li>5+ years DFT design experience</li>\n</ul>\n<ul>\n<li>Expertise in Scan insertion, ATPG, JTAG</li>\n</ul>\n<ul>\n<li>Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)</li>\n</ul>\n<ul>\n<li>Scripting (Perl, TCL, Python) is a plus</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Responsible and collaborative</li>\n</ul>\n<ul>\n<li>Excellent English communication</li>\n</ul>\n<ul>\n<li>Team player and problem solver</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4e4a0dc-158","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/dft-staff-engineer-in-hcmc-hanoi/44408/92454718736","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT design experience","Scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","Scripting (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:19:13.522Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT design experience, Scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), Scripting (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_61448503-aa0"},"title":"Design Verification Engineer","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Design Verification Engineer</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$226K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team:</strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong> OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.</p>\n<p><strong>In this role you will:</strong></p>\n<ul>\n<li>Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.</li>\n</ul>\n<ul>\n<li>Define verification plans based on architecture and microarchitecture specs.</li>\n</ul>\n<ul>\n<li>Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.</li>\n</ul>\n<ul>\n<li>Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.</li>\n</ul>\n<ul>\n<li>Drive bug triage, root cause analysis, and work closely with design teams on resolution.</li>\n</ul>\n<ul>\n<li>Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.</li>\n</ul>\n<p><strong>You might thrive in this role if you have:</strong></p>\n<ul>\n<li>BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.</li>\n</ul>\n<ul>\n<li>Proven success verifying complex IP or SoC designs in industry-standard flows</li>\n</ul>\n<ul>\n<li>Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).</li>\n</ul>\n<ul>\n<li>Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.</li>\n</ul>\n<ul>\n<li>Familiarity with performance modeling, formal verification, or emulation is a plus.</li>\n</ul>\n<ul>\n<li>Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. 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This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<ul>\n<li>Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.</li>\n</ul>\n<ul>\n<li>Drive flow development and optimization to improve design quality and predictability.</li>\n</ul>\n<ul>\n<li>Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).</li>\n</ul>\n<ul>\n<li>Contribute to the adoption and integration of advanced technologies and tool features in design implementation.</li>\n</ul>\n<ul>\n<li>Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.</li>\n</ul>\n<ul>\n<li>Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.</p>\n<p>Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.</p>\n<p>Enhance the predictability and simplicity of implementation processes for complex interface IPs.</p>\n<p>Accelerate the adoption of next-generation design technologies and tools across the industry.</p>\n<p>Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.</p>\n<p>Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.</p>\n<p><strong>What you’ll need</strong></p>\n<ul>\n<li><strong>Minimum 7years</strong> of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why you’ll love this role</strong></p>\n<ul>\n<li>Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.</li>\n</ul>\n<ul>\n<li>Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.</li>\n</ul>\n<ul>\n<li>Participate in professional development opportunities to enhance your skills and expertise.</li>\n</ul>\n<ul>\n<li>Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2a30b6e4-ca4"},"title":"ASIC Verification, Principal Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<ul>\n<li>Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.</li>\n<li>Creating, executing and tracking against detailed test plans to verify complex ASIC designs.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).</li>\n<li>Proficiency in System Verilog, SVA and UVM methodologies.</li>\n<li>Strong understanding of digital design and verification concepts.</li>\n<li>Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.</li>\n<li>Experience with simulation tools such as VCS, Model Sim, or similar.</li>\n<li>Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.</li>\n<li>Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2a30b6e4-ca4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/reading/asic-verification-principal-engineer/44408/91539646624","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC digital verification","Interface IP protocols","System Verilog","SVA","UVM methodologies","Digital design and verification concepts","Simulation tools","Analytical and problem-solving skills","Communication skills"],"x-skills-preferred":["RTL design through synthesis","VCS, Model Sim, or similar"],"datePosted":"2026-02-11T16:09:03.098Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Reading, United Kingdom"}},"jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital verification, Interface IP protocols, System Verilog, SVA, UVM methodologies, Digital design and verification concepts, Simulation tools, Analytical and problem-solving skills, Communication skills, RTL design through synthesis, VCS, Model Sim, or similar"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1421653b-c51"},"title":"ASIC Digital Design, Sr Staff Engineer","description":"<p>Opening. Our team is looking for a skilled ASIC Digital Design Engineer to join our team in Ho Chi Minh City.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP.</li>\n<li>Planning tests, checklists, coverage, and assertion planning.</li>\n<li>Creating detailed verification environments from functional specifications.</li>\n<li>Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.</li>\n<li>Writing test cases, checkers, and coverage that implement the verification test plan.</li>\n<li>Debugging simulations, including those of real signals modeled using SystemVerilog for analog.</li>\n<li>Performing RTL, GLS, and co-simulations and ensuring coverage closure.</li>\n<li>Participating in technical reviews and contributing actively.</li>\n<li>Providing customer support with the bring-up of IP in customer simulation environments.</li>\n<li>Following and improving development processes to ensure high-quality output.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.</li>\n<li>8+ years of experience in design verification.</li>\n<li>Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).</li>\n<li>Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.</li>\n<li>Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1421653b-c51","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-digital-design-sr-staff-engineer-verification/44408/89830689008","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["VCS/Verdi simulation tools","formal verification tools","UPF","UVM","SVA"],"x-skills-preferred":["Perl/TCL/Python scripting"],"datePosted":"2025-12-24T12:04:34.403Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"VCS/Verdi simulation tools, formal verification tools, UPF, UVM, SVA, Perl/TCL/Python scripting"}]}