Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:\nYou are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.
\nYou are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.
\nWhat You’ll Be Doing:\nSpecify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\nDevelop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\nDesign, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\nPerform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\nCollaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\nLeverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\nContribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.
\nThe Impact You Will Have:\nEnsure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\nDrive innovation in verification methodologies, setting new standards for efficiency and coverage.\nEnhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\nStrengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\nMentor and support junior engineers, fostering a culture of learning and continuous improvement.\nContribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.
\nWhat You’ll Need:\nBSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\nExpertise in developing HVL (System Verilog)-based verification environments and testbenches.\nStrong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\nProficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\nSolid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\nFamiliarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\nDemonstrated ability to work with functional coverage-driven methodologies and quality metric goals.
\nWho You Are:\nAnalytical thinker with strong problem-solving and debugging skills.\nExcellent verbal and written communication abilities.\nTeam player who thrives in collaborative, multi-site environments.\nProactive, self-motivated, and able to take initiative on challenging projects.\nDetail-oriented, quality-focused, and driven by a desire to excel.\nAdaptable and eager to continuously learn and apply new technologies.
\nThe Team You’ll Be A Part Of:\nYou will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.
\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
\nBenefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nThis role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.
\nKey responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.
\nThe successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.
\nAs a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.
\nIf you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.
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\nYour key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.
\nTo be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nAs a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.
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\nYou will work closely with customers, Sales, R&D, and field teams to help them adopt and deploy Synopsys Verification solutions.
\nResponsibilities
\nRequirements
\nThe Team You’ll Be A Part Of
\nYou’ll join a dynamic, Theale based Customer Application Services team dedicated to delivering world-class technical support and solutions for leading semiconductor companies.
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\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nAs a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.
\nYou are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.
\nYou are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.
\nDeveloping and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.
\nAccelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.
\n2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.
\nAnalytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.
\nYou'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nKey Responsibilities:
\nImpact:
\nRequirements:
\nWho You Are:
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\nAs a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.
\nKey responsibilities include:\nPlanning tests, checklists, coverage, and assertion planning.\nCreating detailed verification environments from functional specifications.\nApplying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.\nWriting test cases, checkers, and coverage that implement the verification test plan.\nDebugging simulations, including those of real signals modeled using SystemVerilog for analog.\nPerforming RTL, GLS, and co-simulations and ensuring coverage closure.\nParticipating in technical reviews and contributing actively.\nProviding customer support with the bring-up of IP in customer simulation environments.\nFollowing and improving development processes to ensure high-quality output.
\nRequirements include:\nBS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.\n2+ years of experience in design verification.\nStrong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).\nKnowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.\nProficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
\nIdeal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written.\nA great team player, willing to support others.\nSelf-motivated and highly enthusiastic about technology and solving problems.
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\nYou are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\nBSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
\n8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.
\nGood exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.
\nKnowledge on memory defectivities soft errors and reliability.
\nFamiliarity with error correcting codes such as Hamming and Hsiao.
\nHands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.
\nFamiliarity with either Synopsys TestMAX Tool chain or competitive offerings.
\nDebugging abilities to identify and resolve issues in functional verification in UVM environment.
\nHands on experience in flow automation.
\nKnowledge of Synthesis is a must with understanding of timing constraints (SDC).
\nKnowledge of Lint, CDC, RDC is a plus.
\nKnowledge of physical implementation is not a must, but good to have.
\nAbility to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.
\nCustomer facing experience is a plus – educating/guiding customer on technical details of a solution.
\nGood to have:
\nHands-on bring-up and debug experience of silicon is a plus.
\nArchitecture/micro-architecture experience.
\nUnderstanding of GenAI and Agentic AI workflows.
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\nAs a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
\nResponsibilities
\nThe Impact You Will Have
\nWhat You’ll Need
\nWho You Are
\nThe Team You’ll Be A Part Of
\nYou will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.
\nRewards and Benefits
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\nYou should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.
\nYou should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.
\nYou should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.
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\nYou should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.
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\nYou will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.
\nThe team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.
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\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
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\nJob Description
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
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\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nYou bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity:
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\nJob Description
\nDate posted 02/24/2026
\nCategory EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
\nPo Popal
\nWorkplace Resources, Sr Director
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\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
\nBack to nav
\nGet an idea of what your daily routine around the office can be like
\n\\ Explore Noida
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\nJob Description
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.
\nA technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.
\nYou bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\n15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.
\nBe results driven
\nProven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
\nAdvanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
\nIn-depth knowledge of system-level validation for high-speed interface PHY
\nProven track record of working cross-functionally and driving issues to closure
\nKnowledge of mixed-signal design
\nExperience in working in cross-functional collaborations
\nBe an excellent communicator and a beacon for change
\nExcellent debugging, analytical, and problem-solving skills
\nWorking knowledge of scripting in languages such as Python and/or Perl
\nGood understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon
\nGood interpersonal skills, ability & desire to work as a standout colleague
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity:
\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
\n#LI-DP1
\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
\nBenefits:
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nWe are looking for a hardware verification engineer who will perform verification of complex leading-edge security systems IP components. Be a part of a world-class team, building advanced security solutions that meet the Synopsys high quality standard for best-in-class products. These products are found in some of the most advanced, high-tech devices today in areas like automotive, networking, mobile, and IoT applications.
\nResponsibilities
\nRequirements
\nWhat You’ll Be A Part Of
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\nRewards and Benefits
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\nDesign Verification Engineer
\nLocation
\nSan Francisco
\nEmployment Type
\nFull time
\nLocation Type
\nHybrid
\nDepartment
\nScaling
\nCompensation
\nThe base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.
\nMore details about our benefits are available to candidates during the hiring process.
\nThis role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.
\nAbout the Team:
\nOpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
\nAbout the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.
\nIn this role you will:
\nYou might thrive in this role if you have:
\n_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._
\nAbout OpenAI
\nOpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
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\nXML job scraping automation by YubHub
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nCollaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.
\nWhat you need
\nWhy this matters
\nAdvance high-speed connectivity for enterprise and hyperscale applications worldwide.
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nYou will join the Synopsys IP Group, a highly collaborative and innovative team focused on developing leading-edge interface IP solutions for memory technologies.
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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\nWhat you need
\nMinimum 6 years' SoC/ASIC verification experience.
\nXML job scraping automation by YubHub
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\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
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