The role is focused on Level 1+ support of Millennium's Rates, Credit, Mortgages, Commodities, and FX trading platforms, and monitoring systems.

Responsibilities

• Provide Level 1+ support for Fixed Income, Commodities, and FX Trading System users.
• Build up an understanding of various trading, trade processing, and risk reporting systems, including Front-end trading, Trade Capture, Risk and Pnl, Trade Repository, and Prime Brokerage clearing.
• Troubleshoot trade-related issues and train users on various platforms.
• Support Millennium's proprietary platform for electronic and algo trading, including testing, capturing requirements, and marketing and implementing algos with our PM teams.
• Monitor and support intra-day and EOD jobs, platform performance, enhance, and support of trade processing platform.

Qualifications

• 3-5 years front office trading support experience preferred.
• Knowledge and understanding of fixed income products (Rates, Credit, Futures, Derivatives), Commodities, and FX.
• Good team player who is able to prioritize competing demands in a fast-moving, high-pressure environment.
• Possesses a strong sense of urgency.
• Excellent written and oral communication skills.
• Detail-oriented, demonstrates thoroughness, and strong ownership of work.
• Quick thinker and problem solver, able to think on their feet and make informed decisions to resolve/mitigate issues.
• Experience with 3rd party trading systems (Bloomberg FIT/ALLQ/FXGO/CDX/IRS, Brokertec, Tradeweb, MarketAxess, Trading Technologies (TT), WebICE, CME Direct, etc.) is a plus.
• Experience with Bloomberg and/or Reuters is a plus.
• Interest in financial markets and news a plus.
• Unix shell experience a plus.

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This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.

As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.

In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.

Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Exposure to Verilog/System Verilog and AMS concepts or circuit design (coursework, labs, or hands-on experience).

Why this matters

As a Mixed-Signal AMS Co-Simulation Verification Engineer, you will play a critical role in ensuring the quality and reliability of our high-performance SERDES and mixed-signal IP, which powers AI, automotive, cloud, and mobile applications at massive scale.

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