Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You will be a part of a fast-growing analog and mixed-signal R&D team, dedicated to developing high-speed analog integrated circuits in the most advanced FinFET/GAA process nodes. You'll interact with a global, dynamic, multi-cultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

As a Staff Engineer, you will be responsible for:

Developing and/or validating analog circuits considering electrical specifications and reliability constraints. Documenting simulation results and analyzing performance. Evaluating the impact of parasitic effects related to layout implementations and working with the layout team to minimize such effects, improving performance, power, and area. Defining and planning analog design activities for high-speed SerDes products. Collaborating with a global team of engineers to integrate and verify design solutions. Continuously learning and applying the latest advancements in FinFET/GAA process nodes to enhance design efficiency.

You will contribute to the development of high-speed SerDes products that enable high-performance chip-to-chip communications. You will enhance the performance, power efficiency, and reliability of analog integrated circuits in advanced CMOS technologies. You will support the integration of more capabilities into System-on-Chip (SoC) designs, accelerating time-to-market for innovative products.

You will be a part of a dynamic, multicultural, and cross-functional design team, collaborating with experts in various fields to create innovative solutions for high-speed communications.

The ideal candidate will have a good understanding of CMOS technologies and analog circuit design principles. They will have strong analysis, problem-solving, and organizational skills. They will have experience in analog and mixed-signal block design, with a focus on high-speed SERDES. They will be proficient in documenting and analyzing simulation results. They will be familiar with IC design packages and UNIX operating systems.

You will be a collaborative team player who thrives in a global, multicultural environment. You will be an effective communicator with strong written and verbal skills in English. You will be a proactive and self-motivated individual with a passion for innovation and continuous learning. You will be an analytical thinker with the ability to tackle complex design challenges and find creative solutions. You will be a detail-oriented engineer who values precision and accuracy in their work.

You will be rewarded with a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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As a Layout Design Engineer, you will be designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces. You will collaborate with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.

Responsibilities:

• Designing and implementing complex analog and mixed-signal CMOS circuit layouts, with a focus on high-speed SerDes physical interfaces.
• Collaborating with circuit designers to translate schematics into robust, manufacturable layouts that meet performance, power, and area requirements.
• Performing floor planning, layout entry, and comprehensive verification to ensure design quality and compliance with foundry rules.
• Applying advanced techniques to mitigate signal integrity issues, ESD, and latch-up risks, including differential routing, shielding, and substrate biasing.
• Optimizing layouts for reliability, matching, and minimizing parasitic effects such as EM and IR drop.
• Supporting design porting activities to enable seamless migration of layouts across multiple foundry nodes and technology platforms.
• Documenting layout methodologies, best practices, and validation results to support knowledge sharing and continuous improvement.

Requirements:

• Bachelor or advanced degree in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level design.
• 5+ years of experience in analog and mixed-signal CMOS layout design, including complex integrated circuits.
• Expertise in deep submicron CMOS technologies and layout effects (matching, reliability, proximity, EM, IR, etc.).
• Proficiency in layout floor planning, verification, and quality validation using industry-standard EDA tools.
• Strong knowledge of signal integrity, ESD, and latch-up mitigation techniques.
• Familiarity with UNIX operating systems and scripting languages (TCL, Python) is a plus.
• Experience with Synopsys EDA tools is highly desirable.

Who You Are:

• Detail-oriented and quality-focused, with a commitment to delivering robust and reliable designs.
• Excellent communicator, able to articulate technical concepts clearly to diverse audiences.
• Collaborative team player who builds productive relationships and networks effectively.
• Self-motivated, organized, and able to manage multiple priorities in a dynamic environment.
• Strong problem-solving skills and critical judgment, with a proactive approach to overcoming challenges.
• Adaptable and eager to learn new technologies and methodologies.

The Impact You Will Have:

• Accelerate the development of cutting-edge silicon IP, enabling faster integration of advanced capabilities into SoCs.
• Enhance the performance, reliability, and manufacturability of high-speed interface solutions for next-generation applications.
• Reduce time-to-market and risk for customers by delivering high-quality, validated layout designs.
• Contribute to the innovation of analog and mixed-signal design methodologies within a global team.
• Support the creation of differentiated products that power the Era of Smart Everything, from AI to IoT and beyond.
• Foster a culture of collaboration, knowledge sharing, and technical excellence within the team and across the organization.

The Team You'll Be A Part Of:

You will join a dynamic, international team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoC solutions. Our team values innovation, collaboration, and technical excellence, working closely with circuit designers, verification engineers, and global partners to deliver industry-leading silicon IP. We foster a supportive environment where knowledge sharing and continuous learning are encouraged, and where your contributions will directly impact the success of our products and customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Provide expert support and training to customers on Totem and related Semiconductor Business Unit simulation products, ensuring high productivity and satisfaction.
• Independently coordinate and manage support for multiple customer designs through tape-out, verifying design quality and compliance with expectations.
• Apply advanced knowledge in analog circuit analysis, VLSI design, power-grid extraction, noise analysis, and ESD to solve complex SoC challenges.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) with at least 3 years of relevant experience.
• Advanced expertise in custom circuit analysis & design, physical layout, noise analysis, voltage drop effects, and ESD using CAD tools.
• Strong technical knowledge of EDA tools, especially for layout and analog circuit extraction (SPEF/DSPF).
• Proficiency in UNIX operating systems and scripting languages such as Perl, Tcl, or Python for troubleshooting and utility development.
• Excellent verbal and written communication skills in both English and Mandarin, with the ability to convey complex concepts clearly.

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What you'll do

• Providing expert support and training to customers on PrimeTime, PrimeClosure, and PrimeShield, ensuring optimal use and maximum productivity.
• Independently coordinating and supporting multiple customer designs through tape-out, verifying designs meet or exceed customer expectations.

What you need

• Bachelor’s degree in Electrical Engineering with a minimum of 12 years of experience, or a Master’s degree with at least 8 years of experience.
• In-depth understanding of timing, power, statistical and electromigration characterization, and signal integrity in advanced SoC design.

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What you'll do

• Managing the entire program engineering lifecycle—including initiation, definition, planning, execution, and closure—across multiple interconnected projects.
• Monitoring and controlling program budgets, schedules, risks, issues, and scopes to ensure successful delivery of key milestones and customer commitments.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Applied Science, or a related field (or equivalent experience).
• 5+ years of experience in project/program management within engineering, ideally in semiconductor, IP, or ASIC design environments.

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