{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/ucie"},"x-facet":{"type":"skill","slug":"ucie","display":"Ucie","count":11},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_14ac1088-f19"},"title":"ASIC Digital Design, Architect","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.</p>\n<p>What You’ll Be Doing:</p>\n<p>Defining and developing ASIC RTL design and verification at both chip and block levels.\nCreating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols.\nCollaborating with cross-functional teams to ensure seamless integration and functionality of designs.\nUtilizing advanced design and verification methodologies and tools to achieve high-quality results.\nMentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.\nCommunicating with internal and external stakeholders to align on project goals and deliverables.</p>\n<p>The Impact You Will Have:</p>\n<p>Enhancing the reliability and performance of Synopsys’ digital design processes.\nDriving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.\nImproving time-to-market for high-performance silicon chips through efficient methodologies.\nBuilding and nurturing a highly skilled development team, elevating overall project quality.\nInfluencing strategic decisions that shape the future of Synopsys’ capabilities.\nEnsuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.</p>\n<p>What You’ll Need:</p>\n<p>Extensive experience in ASIC RTL design.\nIn-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.\nProficiency in advanced digital design tools and methodologies.\nStrong problem-solving skills and the ability to work independently.\nExcellent communication skills for effective collaboration with diverse teams.</p>\n<p>Who You Are:</p>\n<p>A visionary leader with a strategic mindset.\nA mentor who fosters talent and encourages innovation.\nA proactive problem solver who thrives in complex environments.\nAn effective communicator with the ability to convey technical concepts to a broad audience.\nA team player who values collaboration and diversity.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and innovative team focused on advancing Synopsys&#39; design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_14ac1088-f19","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/asic-digital-design-architect/44408/92736415760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","DDR","PCIe","CXL","UAL","UCIe","AMBA","advanced digital design tools","methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:24:48.989Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Dublin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, DDR, PCIe, CXL, UAL, UCIe, AMBA, advanced digital design tools, methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_66c5c8aa-9e8"},"title":"Solutions Engineering, Sr Staff Engineer (DFT ,Verification, product Engineer)","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li><p>Working closely with a world-class R&amp;D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.</p>\n</li>\n<li><p>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</p>\n</li>\n<li><p>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</p>\n</li>\n<li><p>Driving the deployment and smooth execution of SLM solutions into customers’ projects.</p>\n</li>\n<li><p>Enabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.</p>\n</li>\n</ul>\n<p>The impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_66c5c8aa-9e8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/solutions-engineering-sr-staff-engineer-dft-verification-product-engineer/44408/92871142528","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design and verification","D2D and PHY protocols","UCIe and HBM","JTAG IEEE 1149.1","IEEE 1687/1500","BIST/DFT mechanisms","3D-IC/2.5D-IC solutions","IEEE 1838 and UCIe standards","PCIe & USB protocol knowledge","Debugging abilities","Flow automation","Synthesis","Lint, CDC, RDC"],"x-skills-preferred":["GenAI and Agentic AI workflows","Architecture/micro-architecture experience","Understanding of GenAI and Agentic AI workflows"],"datePosted":"2026-04-05T13:21:31.895Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, D2D and PHY protocols, UCIe and HBM, JTAG IEEE 1149.1, IEEE 1687/1500, BIST/DFT mechanisms, 3D-IC/2.5D-IC solutions, IEEE 1838 and UCIe standards, PCIe & USB protocol knowledge, Debugging abilities, Flow automation, Synthesis, Lint, CDC, RDC, GenAI and Agentic AI workflows, Architecture/micro-architecture experience, Understanding of GenAI and Agentic AI workflows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_888db686-e04"},"title":"ASIC/SoC Presales Applications Engineer","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 614 open roles</p>\n<p><strong>Innovation Starts Here</strong></p>\n<p>Find Jobs For</p>\n<p>Where?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>ASIC/SoC Presales Applications Engineer - 16648</strong></p>\n<p>Sunnyvale, California, United States</p>\n<p>Save</p>\n<p>Category: EngineeringHire Type: Employee</p>\n<p><strong>Job ID</strong> 16648<strong>Base Salary Range</strong> $184000-$276000<strong>Date posted</strong> 03/31/2026</p>\n<p><strong><strong>We Are:</strong></strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong><strong>You Are:</strong></strong></p>\n<p>You are a seasoned ASIC, SoC, or Chiplet Architect, Manager, or Design Engineer, bringing extensive expertise in IC Digital, Mixed Signal, or Analog Design. Your technical prowess is matched by your ability to engage and inspire customers, translating complex engineering concepts into clear, impactful solutions. You thrive in fast-paced, dynamic environments and are adept at navigating competitive landscapes. Your organizational skills and self-motivation ensure you deliver on ambitious goals, while your creative approach to problem-solving enables you to overcome challenges with finesse. You build trust and rapport quickly, fostering long-lasting relationships with both internal teams and external stakeholders. With a Bachelor’s (15+ years) or Master’s (11+ years) degree in a relevant field, you understand industry protocols such as SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet, bringing added value to each engagement. You are passionate about driving technology forward and contributing to customer success, ready to make a significant impact at Synopsys.</p>\n<p><strong><strong>What You’ll Be Doing:</strong></strong></p>\n<ul>\n<li>Presenting Synopsys solutions to senior managers and technical stakeholders, showcasing the value and capabilities of our IP portfolio.</li>\n</ul>\n<ul>\n<li>Engaging with customers to understand their unique requirements and challenges, proposing tailored technical solutions that meet their needs.</li>\n</ul>\n<ul>\n<li>Positioning Synopsys competitively in technical discussions, articulating differentiators and advantages in the marketplace.</li>\n</ul>\n<ul>\n<li>Liaising between technical, marketing, and sales teams to ensure seamless communication and alignment on project objectives.</li>\n</ul>\n<ul>\n<li>Driving strategy and execution for technical solution design, influencing customer architectures and product adoption.</li>\n</ul>\n<ul>\n<li>Supporting sales and business unit negotiations with expert insight into technical feasibility, solution fit, and value proposition.</li>\n</ul>\n<p><strong><strong>The Impact You Will Have:</strong></strong></p>\n<ul>\n<li>Lead customer engagements, ensuring Synopsys solutions align perfectly with client requirements and goals.</li>\n</ul>\n<ul>\n<li>Collaborate across global teams to deliver innovative, winning solutions that drive business growth.</li>\n</ul>\n<ul>\n<li>Accelerate adoption of Synopsys products and platforms within key customer accounts.</li>\n</ul>\n<ul>\n<li>Provide critical technical insight, shaping the design and success of customer chip projects.</li>\n</ul>\n<ul>\n<li>Drive customer and business success by enabling efficient, high-performance SoC and ASIC design.</li>\n</ul>\n<ul>\n<li>Ensure successful delivery of complex SoC projects across multiple regions, supporting Synopsys&#39; reputation as a market leader.</li>\n</ul>\n<p><strong><strong>What You’ll Need:</strong></strong></p>\n<ul>\n<li>Deep expertise in IC design, including Digital, Mixed Signal, or Analog domains.</li>\n</ul>\n<ul>\n<li>Experience in customer-facing roles, technical sales, or sales support within the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Exceptional communication skills, able to convey complex technical concepts to diverse audiences.</li>\n</ul>\n<ul>\n<li>Strong organizational and project management abilities, driving multiple projects to completion.</li>\n</ul>\n<ul>\n<li>Solid understanding of major semiconductor IP product lines and industry protocols (SerDes, UCIe, PCIe, DDR, USB, MIPI, Ethernet).</li>\n</ul>\n<p><strong><strong>Who You Are:</strong></strong></p>\n<p>A creative problem solver and strategic thinker, you excel at collaborating with diverse teams and stakeholders. You are driven by a passion for technology, innovation, and customer success, bringing a positive, solutions-oriented mindset to every challenge. Your adaptability and leadership enable you to thrive in high-pressure situations, while your integrity and commitment build trust across all levels of the organization.</p>\n<p><strong><strong>The Team You’ll Be A Part Of:</strong></strong></p>\n<p>You’ll join a collaborative group dedicated to delivering groundbreaking chip design solutions using Synopsys IP. The team works closely with Sales, R&amp;D, and Marketing, fostering a supportive and innovative environment where your ideas and expertise will help shape next-generation semiconductor products.</p>\n<p><strong><strong>Rewards and Benefits:</strong></strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_888db686-e04","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/asic-soc-presales-applications-engineer-16648/44408/93479957968","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$184000-$276000","x-skills-required":["IC design","Digital design","Mixed signal design","Analog design","SerDes","UCIe","PCIe","DDR","USB","MIPI","Ethernet"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:32.722Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"engineering","industry":"technology","skills":"IC design, Digital design, Mixed signal design, Analog design, SerDes, UCIe, PCIe, DDR, USB, MIPI, Ethernet","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":184000,"maxValue":276000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_aa3b68d5-66e"},"title":"Senior High-Speed IO Architect","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a Senior High-Speed IO Architect to join our team. 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Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_aa3b68d5-66e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/senior-high-speed-io-architect-15236/44408/91598898352","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$181000-$271000","x-skills-required":["high-speed mixed-signal IC design","UCIe Die-to-Die PHY","circuit design","verification","project management","communication"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:04.012Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"high-speed mixed-signal IC design, UCIe Die-to-Die PHY, circuit design, verification, project management, communication","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":181000,"maxValue":271000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6bd5b497-557"},"title":"Signal and Power integrity, Staff engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You have a strong technical background and excellent problem-solving skills. Your ability to communicate effectively and work well with diverse teams makes you an asset to any project. You are dedicated to continuous learning and development, and your passion for technology drives you to stay ahead of industry trends. You are adaptable, detail-oriented, and committed to delivering high-quality results.</p>\n<p><strong>Team</strong></p>\n<p>You will be working with a group of highly-skilled, supportive, and globally spread-out teams. Our team is dedicated to driving innovation and excellence in SIPI analysis of high speed interface IP&#39;s. We value collaboration, continuous learning, and a can-do attitude. Together, we strive to develop the most advanced technologies and deliver exceptional results for our clients.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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You will define and implement UCIe PHY for automotive applications, design and verify digital IP and ASIC solutions, and collaborate with cross-functional teams and support validation.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Define and implement UCIe PHY for automotive applications.</li>\n<li>Design and verify digital IP and ASIC solutions.</li>\n<li>Create and review FMEDA, DFMEA, and DFA work products for UCIe PHY.</li>\n<li>Apply ISO 26262 functional safety standards.</li>\n<li>Collaborate with cross-functional teams and support validation.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Experience in digital IP/ASIC design for automotive.</li>\n<li>UCIe PHY and SoC architecture knowledge.</li>\n<li>Familiarity with ISO 26262, FMEDA, DFMEA, DFA.</li>\n<li>Proficiency with EDA tools.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ad93119c-3e8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/automotive-functional-safety-staff-engineer/44408/90166587088","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["digital IP/ASIC design for automotive","UCIe PHY and SoC architecture knowledge","ISO 26262, FMEDA, DFMEA, DFA","EDA tools"],"x-skills-preferred":["collaborative","detail-oriented","passionate about automotive technology"],"datePosted":"2026-03-06T07:31:07.834Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Automotive","skills":"digital IP/ASIC design for automotive, UCIe PHY and SoC architecture knowledge, ISO 26262, FMEDA, DFMEA, DFA, EDA tools, collaborative, detail-oriented, passionate about automotive technology"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4d218e4-3b5"},"title":"Power Integrity Staff Engineer","description":"<p>We are looking for a Power Integrity Staff Engineer to join our team. As a Power Integrity Staff Engineer, you will be responsible for modeling, simulating, analyzing signal and power integrity, troubleshooting, and reviewing interfaces interconnect. This encompasses all aspects of physical include interconnect and power network delivery in a system context, including silicon, package, pcb, connectors and components on multi-signal transmission line interfaces.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.</li>\n<li>Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.</li>\n<li>Carry out experiments to validate modeling and methodologies.</li>\n<li>Develop and document signal and power integrity requirements and flows for internal and external customer use.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Possesses excellent communication skills, both verbal and written.</li>\n<li>Familiarity with both Windows and Linux operating system is required.</li>\n<li>An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.</li>\n<li>Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.</li>\n<li>Some experience in programming languages such as Python, TCL and Matlab is desired.</li>\n<li>A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. Experience with Redhawk, Totem, Ansys AEDT, Keysight ADS, etc. is a plus.</li>\n<li>Practical experience with package and pcb design 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.</li>\n<li>Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.</li>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical or Electronics Engineering, with a minimum of 6 years of relevant experience in supporting interface IP product development (preferably DDR), system integration and Signal and Power verifications flow/methodologies.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4d218e4-3b5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/power-integrity-staff-engineer/44408/92333269904","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["excellent communication skills","familiarity with Windows and Linux operating system","understanding of basic circuit and transmission line theory","knowledge on interface such as UCIE","experience in programming languages such as Python, TCL and Matlab","working knowledge of circuit simulation tools such as Synopsys HSPICE"],"x-skills-preferred":["knowledge on interface such as UCIE","experience in programming languages such as Python, TCL and Matlab","working knowledge of circuit simulation tools such as Synopsys HSPICE"],"datePosted":"2026-03-06T07:24:19.192Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"excellent communication skills, familiarity with Windows and Linux operating system, understanding of basic circuit and transmission line theory, knowledge on interface such as UCIE, experience in programming languages such as Python, TCL and Matlab, working knowledge of circuit simulation tools such as Synopsys HSPICE, knowledge on interface such as UCIE, experience in programming languages such as Python, TCL and Matlab, working knowledge of circuit simulation tools such as Synopsys HSPICE"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ed273d82-c6f"},"title":"ASIC Digital Design Architect","description":"<p>We are seeking an experienced and visionary ASIC Digital Architect to join our team. As a key member of our design team, you will be responsible for defining and developing ASIC RTL design and verification at both chip and block levels. You will create and execute design plans for complex digital designs, particularly focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols. You will collaborate with cross-functional teams to ensure seamless integration and functionality of designs. You will utilize advanced design and verification methodologies and tools to achieve high-quality results. You will mentor and guide junior engineers, promoting best practices, and fostering a culture of continuous improvement. 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This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<ul>\n<li>Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.</li>\n</ul>\n<ul>\n<li>Drive flow development and optimization to improve design quality and predictability.</li>\n</ul>\n<ul>\n<li>Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).</li>\n</ul>\n<ul>\n<li>Contribute to the adoption and integration of advanced technologies and tool features in design implementation.</li>\n</ul>\n<ul>\n<li>Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.</li>\n</ul>\n<ul>\n<li>Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.</p>\n<p>Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.</p>\n<p>Enhance the predictability and simplicity of implementation processes for complex interface IPs.</p>\n<p>Accelerate the adoption of next-generation design technologies and tools across the industry.</p>\n<p>Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.</p>\n<p>Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.</p>\n<p><strong>What you’ll need</strong></p>\n<ul>\n<li><strong>Minimum 7years</strong> of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why you’ll love this role</strong></p>\n<ul>\n<li>Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.</li>\n</ul>\n<ul>\n<li>Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.</li>\n</ul>\n<ul>\n<li>Participate in professional development opportunities to enhance your skills and expertise.</li>\n</ul>\n<ul>\n<li>Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ab43e00d-e42"},"title":"ASIC Digital Design, Senior Staff Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.</p>\n<ul>\n<li>Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Drive the development of cutting-edge HBM PHY IP, enabling industry-leading memory bandwidth for next-generation computing systems.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ab43e00d-e42","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-digital-design-senior-staff-engineer/44408/91333936928","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","SystemVerilog","Verilog","High-speed digital and mixed-signal interfaces"],"x-skills-preferred":["Automating tasks using scripting languages","Physically aware synthesis","DDR/HBM DRAM","UCIe technologies"],"datePosted":"2026-02-04T16:11:48.007Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean, Ontario, Canada"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, SystemVerilog, Verilog, High-speed digital and mixed-signal interfaces, Automating tasks using scripting languages, Physically aware synthesis, DDR/HBM DRAM, UCIe technologies"}]}