As a Staff Engineer in Analog Design, you will be part of a fast-growing team dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. You will design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.

Key Responsibilities:

• Design and develop medium complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
• Define and plan analog design activities, setting clear milestones and deliverables for project success.
• Prepare and conduct technical design reviews, identifying improvements, tracking actions, and ensuring best practices are followed.
• Evaluate and minimize the impact of layout parasitic effects by collaborating closely with layout teams, optimizing circuit performance, power, and area.
• Perform silicon correlation with simulation results, analyzing discrepancies and driving design refinements.

Impact:

• Accelerate the development of industry-leading SerDes IP products, supporting diverse markets such as mobile, automotive, cloud computing, HPC, AI, IoT, 5G, and storage, enabling high-speed chip-to-chip communications in next-generation devices.
• Enhance Synopsys' reputation as a provider of silicon-proven IP by delivering reliable, high-performance analog designs.
• Reduce risk for customers by ensuring robust correlation between simulation and silicon, leading to differentiated products in the marketplace.
• Foster innovation and continuous improvement within the analog and mixed-signal R&D team, setting benchmarks for technical excellence.

Requirements:

• M.Sc. degree in Electrical Engineering with 3+ years of experience, or Ph.D. in Electrical Engineering with 1.5+ years of experience.
• Background in CMOS analog circuit design, preferably including ADC, DAC, PLL, Rx, Tx, References, or related areas.
• Familiarity with industry-standard IC design packages and EDA tools.
• Experience working in UNIX operating systems.
• Good written and verbal communication skills in English.
• System-level knowledge of SerDes architecture is a plus.

Team:

You will join Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As an experienced analog design engineer, you will be responsible for driving the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. You will guide analog designers to ensure designs meet electrical specifications and reliability constraints. You will also define methods and procedures for project execution, including planning analog design activities and associated milestones.

You will conduct and prepare design reviews, following up on improvements, and ensuring high quality outcomes. You will evaluate and minimize parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area. You will ensure silicon correlation with simulation results, validating design accuracy and robustness.

You will mentor and train less experienced analog designers, fostering skill development within the team. You will engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

The successful candidate will have a proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc. They will have experience coordinating design activities across teams and managing medium complexity designs. They will be familiar with industry-standard IC design packages and EDA tools.

The ideal candidate will be a collaborative team player who thrives in multicultural, global environments. They will be an analytical thinker with strong problem-solving and organizational skills. They will be an effective communicator, able to lead reviews and share knowledge clearly.

The team you will be a part of is Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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