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Sr. Application Engineer - Electromagnetics

San Jose, California, United States

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Hire Type EmployeeJob ID 13351Base Salary Range $112000-$168000Date posted 11/10/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate engineering professional with a deep expertise in high-frequency electromagnetics and a drive to solve complex real-world problems. You thrive in customer-facing environments, leveraging your technical acumen and communication skills to deliver actionable solutions and build strong relationships. Your experience with advanced simulation software allows you to translate customer challenges into innovative product capabilities, and you excel at collaborating across multi-disciplinary teams. You possess a growth mindset, always eager to learn new technologies and advance your knowledge, while also contributing to a culture of excellence and continuous improvement. Your approach to problem-solving is logical and thorough, and you are adept at presenting technical concepts in a clear, engaging manner. Whether delivering training, consulting on projects, or supporting new product releases, you bring a sense of urgency, organization, and business acumen to every task. You are comfortable interacting with senior business leaders and stakeholders, and your professionalism enhances the customer experience. If you are ready to make an impact at the intersection of engineering and innovation, Synopsys is the place for you.

What You’ll Be Doing:

• Provide advanced technical support and guidance to customers using Ansys electromagnetics simulation tools, ensuring high-quality, timely solutions.
• Engage proactively with key accounts to deliver comprehensive electromagnetic solutions tailored to customer design workflows and business needs.
• Conduct intermediate and advanced training sessions, webinars, and presentations for customers and internal teams.
• Scope, plan, and deliver professional services projects, collaborating with cross-functional application engineering teams.
• Gather and analyze customer requirements, working closely with product development to enhance Ansys software capabilities.
• Test and validate new software releases on industrial problems, providing feedback and driving product improvements.
• Participate in internal initiatives to share best practices and foster knowledge exchange within and across disciplines.
• Travel up to 25% to support customer engagements, training, and project delivery.

The Impact You Will Have:

• Accelerate customer success by enabling seamless integration of Ansys solutions into their design workflows.
• Drive adoption of advanced simulation technologies, helping customers solve critical engineering challenges.
• Enhance customer satisfaction and loyalty through exceptional technical support and consultative services.
• Influence product development by translating customer feedback into innovative new features and capabilities.
• Elevate Synopsys’ reputation as a trusted partner in the engineering and semiconductor industry.
• Contribute to a culture of continuous learning and improvement, sharing expertise and best practices with peers.
• Support business growth through impactful pre-sales technical engagement and solution delivery.

What You’ll Need:

• Master’s degree in Electrical Engineering (with emphasis on high-frequency electromagnetics) or a related technical discipline.
• Minimum 3 years of experience in an engineering software environment, with hands-on use of ANSYS or similar CAE/CAD/EDA tools.
• Expertise in signal and power integrity simulation analysis, including cross-talk analysis, impedance simulations, and eye diagram analysis.
• Strong knowledge of circuit-level and timing analysis for signal integrity applications and compliance standards.
• Experience with package, PCB, and connector design processes, and familiarity with EDA tools.
• Fundamental understanding of microwave and antenna concepts, including S-parameters, wave propagation, and scattering analysis.
• Demonstrated ability to conduct training, deliver presentations, and facilitate webinars for technical audiences.

#CM-1

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As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.

Key Responsibilities:

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
• Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
• Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
• Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
• Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
• Driving tool flow automation and debugging to enhance productivity and design reliability.
• Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.

Impact:

• Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
• Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
• Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
• Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
• Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
• Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

Requirements:

• 6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Familiarity with IP integration, test chip methodology, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
• Experience coordinating complex, cross-functional projects and leading technical execution.
• Authorization to work in the USA.

Team:

You'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Lead RTL Design Engineer, you will be responsible for leading RTL design and implementation for high-performance mixed signal IPs including UCIe, DDR, and Die-to-Die interfaces. You will take technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews.

Key responsibilities include:

• Leading RTL design and implementation for high-performance mixed signal IPs
• Taking technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews
• Specifying, architecting, and implementing digital logic using Verilog/SystemVerilog
• Collaborating with circuit design, verification, physical design, and validation teams to ensure design closure and integration
• Driving logic synthesis, lint, clock domain crossing (CDC), design-for-test (DFT), and timing closure for your blocks
• Analyzing coverage, debugging functional and timing issues, supporting integration, and authoring technical documentation

In this role, you will contribute to Synopsys' reputation as a leader in advanced semiconductor design solutions. You will drive innovation in digital design and architecture, influencing key product features and capabilities. You will ensure the delivery of high-quality, reliable, and scalable IPs that meet stringent market requirements.

As a leader, you will foster a culture of continuous learning, inclusivity, and creative thinking, empowering your peers and advancing the team's collective success. You will be motivated by working on cutting-edge IPs such as UCIe, DDR, and Die-to-Die interfaces, and you will stay current with industry trends and emerging technologies, including AI/ML.

You will join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering.

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You are a dedicated engineer with a passion for analog and mixed-signal IC design, eager to push the boundaries of semiconductor technology. You thrive in environments where innovation, precision, and collaboration are key. Your technical expertise is matched by your curiosity and willingness to continuously learn, adapting to new challenges and technologies. You enjoy working hands-on, taking ownership of the design process from conception to silicon validation. With a keen eye for detail and a strong analytical mindset, you excel at optimizing performance and robustness in high-speed interfaces. You are comfortable navigating complex circuit architectures, and your experience allows you to anticipate issues and implement creative solutions. You value open communication and teamwork, working effectively with layout and lab teams in a multicultural setting. Your documentation skills ensure clarity and reproducibility throughout the design cycle. You are motivated by the opportunity to make a tangible impact on industry-leading products, and you seek growth not only in technical depth but also in architectural responsibility. Ultimately, you are a proactive contributor, ready to help Synopsys shape the next generation of high-speed analog solutions.

Design, analyze, and optimize high-speed analog and mixed-signal circuits such as voltage regulators, DACs, AFE/DFE, TX drivers, serializers, and supporting blocks. Conduct detailed circuit behavior analysis, tuning performance and proposing improvements for power, speed, and robustness. Perform timing closure for small digital blocks using NanoTime, ensuring accurate integration with analog designs. Lead technical interactions with layout teams, guiding floorplanning, matching, and parasitic-aware design to achieve block specifications. Participate actively in design reviews, layout reviews, and silicon bring-up processes to ensure quality and reliability. Support lab characterization and debug, correlating simulation results with silicon measurements for optimal validation. Document architectures, design decisions, testbenches, simulation results, and silicon learnings to maintain clarity and foster knowledge sharing.

Advance Synopsys' leadership in high-speed SerDes IP and analog interface technology. Enable the development of state-of-the-art products used across diverse industries, from data centers to automotive. Drive innovation in design methodologies, influencing future product architectures and performance standards. Enhance cross-functional collaboration, ensuring seamless integration between design, layout, and validation teams. Improve product robustness and yield through meticulous analysis, testing, and documentation. Accelerate time-to-market for cutting-edge chips by optimizing design cycles and validation processes. Contribute to a culture of continuous improvement and technical excellence within Synopsys' engineering community.

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You are a passionate analog design engineer eager to make a tangible impact in pioneering semiconductor technologies. You thrive in fast-paced environments and enjoy collaborating with diverse, talented teams. Your expertise in CMOS circuit design and deep submicron process technologies makes you a valuable contributor to high-performance chip solutions. You are detail-oriented, analytical, and consistently deliver quality results. Your curiosity drives you to explore industry standards such as JEDEC DDR interfaces, and you are comfortable navigating the complexities of ASIC design flows. You communicate clearly and effectively, bridging technical discussions between cross-functional teams. You embrace continuous learning and are always ready to tackle new challenges, leveraging your experience in analog/mixed signal circuitry and ESD concepts. You are motivated by the opportunity to influence the next generation of silicon products and are committed to excellence in every aspect of your work. Your collaborative spirit, adaptability, and drive for innovation make you a perfect fit for Synopsys' world-class engineering community.

Designing DDR I/O circuits for advanced semiconductor products, ensuring alignment with JEDEC interface standards. Implementing CMOS circuit design and layout methodologies to optimize performance and reliability. Collaborating with internal development teams to integrate analog/mixed signal circuitry into ASIC designs. Analyzing and resolving issues related to deep submicron process technologies. Executing assigned circuit design tasks with a focus on product quality and efficiency. Documenting design solutions and communicating technical details clearly to cross-functional stakeholders. Participating in design reviews and contributing to continuous improvement of design flows and practices.

Advance Synopsys' leadership in high-performance DDR interface design for cutting-edge chips. Enhance product reliability and scalability through robust analog design methodologies. Drive innovation in deep submicron process technology applications. Strengthen integration of mixed signal and analog circuitry in ASIC products. Support cross-team collaboration to accelerate product development and delivery. Contribute to Synopsys' reputation for technical excellence and quality in semiconductor solutions.

BTech/MTech in Electrical Engineering or related field (MTech+3 years / BTech+5 years experience). Strong knowledge of CMOS processes and deep submicron process technology issues. Expertise in CMOS circuit design and layout methodology; familiarity with analog/mixed signal circuitry. Understanding of basic ESD concepts (a plus). Experience with ASIC design flow and integration. Knowledge of JEDEC DDR interface requirements, DDR timing, ODT, and SDRAM functionality (preferred).

Analytical thinker with strong problem-solving skills. Effective communicator, both written and verbal, for internal team interactions. Collaborative team player, eager to learn and share knowledge. Detail-oriented and quality-focused in all aspects of design. Adaptable and resilient in dynamic project environments.

You will join a highly skilled Analog/Mixed Signal Design team in Bangalore, focused on delivering innovative DDR I/O circuit solutions for ASIC products. The team values creativity, technical rigor, and collaborative problem-solving, working closely with cross-functional groups to drive product excellence and meet industry standards.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking a Principal Physical Design Engineer to lead the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII. The ideal candidate will have intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.

The successful candidate will be responsible for driving timing and physical sign-off processes to ensure optimal performance and reliability, collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges, and guiding a team of engineers through project execution, mentoring and developing talent within the group.

Key responsibilities include:

• Leading the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII
• Driving timing and physical sign-off processes to ensure optimal performance and reliability
• Collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges
• Guiding a team of engineers through project execution, mentoring and developing talent within the group

The ideal candidate will have 12+ years of digital or physical design experience with recent project tape-outs as a technical driver or project lead, intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.

In addition to technical expertise, the successful candidate will be a collaborative and communicative leader, able to work effectively across diverse teams, autonomous and decisive, comfortable managing multiple priorities and interruptions, and methodology-driven, with a passion for continuous improvement and innovation.

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You possess a solid foundation in analog and mixed-signal circuit concepts, with hands-on experience using CAD tools for schematic entry and layout design. You approach challenges with a problem-solving mindset, leveraging your scripting abilities to automate workflows and enhance productivity. Your communication skills enable you to clearly document processes and share best practices, fostering a culture of knowledge exchange. You’re equally comfortable analyzing complex timing data and collaborating with senior engineers to improve design flows.

Above all, you are motivated to make a tangible impact in the semiconductor industry. You seek opportunities to contribute to innovative projects, learn from experts, and grow your career in a supportive, technology-driven environment. If you are excited by the prospect of working on DDR and HBM memory IPs, and you enjoy taking initiative, you’ll find yourself at home in our team.

\* Simulating and analyzing the performance of analog and mixed-signal circuits for DDR and HBM memory PHY IP.

\* Characterizing circuit timing and validating timing .lib data against design specifications to ensure accuracy and reliability.

\* Collaborating with senior engineers across multiple disciplines to identify design flow bottlenecks and develop automation solutions.

\* Documenting workflows, design guidelines, and best practices to promote effective team collaboration and knowledge sharing.

\* Applying scripting languages (Python, TCL) to automate tasks and streamline design processes.

The Impact You Will Have:

\* Enhancing the performance and reliability of industry-leading DDR and HBM memory PHY IP products.

\* Driving productivity improvements through workflow automation and innovative design solutions.

\* Facilitating knowledge sharing and documentation to strengthen team collaboration and project success.

\* Ensuring design compliance and accuracy through rigorous timing analysis and validation.

\* Supporting the evolution of Synopsys’ analog/mixed-signal design capabilities and methodologies.

What You’ll Need:

\* BSc or MSc in Electrical Engineering, with relevant experience in analog/mixed-signal design.

\* Hands-on experience with schematic entry and layout design CAD tools.

\* Knowledge of timing liberty files and mixed-signal timing analysis.

\* Proficiency in scripting languages such as Python and TCL, with an ability to automate and optimize workflows.

\* Familiarity with AI prompt engineering and agentic AI concepts, integrating modern approaches into design processes.

Who You Are:

\* Strong communicator, able to document and share technical information effectively.

\* Collaborative team player, eager to learn from and contribute to a diverse group of engineers.

\* Detail-oriented and organized, with excellent time management skills.

\* Proactive problem solver, comfortable tackling complex challenges in fast-paced environments.

\* Innovative thinker, continually seeking ways to improve processes and drive technological advancement.

The Team You’ll Be A Part Of:

You will join a dynamic R&D team focused on analog and mixed-signal design for DDR and HBM memory PHY IP products. Our team brings together engineers from various backgrounds, fostering an environment of collaboration, innovation, and continuous learning. We are committed to developing high-performance products that set industry standards, and we value the contributions and growth of each team member.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Driving increased adoption and usage of Synopsys PrimeTime and ECO in both pre-sale and post-sale engagements with customers.
• Conducting in-depth competitive benchmarks and product evaluations to demonstrate PrimeTime's technical and business advantages.
• Providing expert-level training, onboarding, and technical support to empower customers through successful chip tapeouts.
• Collaborating with R&D, marketing, and sales teams to define requirements and influence enhancements to PrimeTime's features.
• Engaging directly with customers to gather actionable feedback and advocate for their needs within Synopsys.
• Articulating complex technical solutions and methodologies to diverse audiences, from design engineers to senior management.
• Troubleshooting critical issues related to timing closure, signal integrity, and process variations.

As a Sr Staff Engineer, you will have a significant impact on customer satisfaction, product adoption, and the strengthening of Synopsys's market presence. You will also contribute to the company's reputation as a global leader and innovator in electronic design automation.

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Your expertise in C/C++ and scripting languages like Tcl or Python allows you to seamlessly develop and optimize robust software solutions. You have a deep understanding of front-end design flows, timing constraints, and the intricate interactions between synthesis, place & route, and analysis tools.

As a Staff Engineer, you will be responsible for designing, developing, and enhancing logic synthesis features and automation flows for advanced EDA tools. You will own and maintain synthesis capabilities with direct impact on timing, area, power, and Quality of Results (QoR) optimization.

You will collaborate with architecture, verification, QA, and product management teams to deliver integrated, production-quality EDA solutions. You will participate actively in technical design discussions, code reviews, and roadmap planning to shape the future of Synopsys' tools.

You will ensure high engineering quality through unit testing, regression support, and adherence to best development practices. You will contribute to internal documentation, knowledge sharing, and mentoring junior engineers to foster growth and innovation within the team.

You will drive the evolution of Synopsys' industry-leading EDA solutions in IP packaging and subsystem assembly. You will enhance the efficiency and scalability of design flows for leading semiconductor and system companies worldwide.

You will empower customers to achieve optimal timing, area, and power results, accelerating their product development cycles. You will resolve critical technical challenges, enabling seamless integration of synthesis and automation in complex design environments.

You will contribute to the creation of robust, production-quality tools that set new standards in the EDA industry. You will facilitate knowledge transfer and technical growth within the R&D organization through mentorship and documentation.

You will support customer success by providing innovative solutions and responsive issue resolution. You will shape the roadmap and future direction of Synopsys' automation frameworks and design technologies.

You are a strong sense of ownership, accountability, and technical leadership. You have clear and effective written and verbal communication skills. You are able to work independently on complex problems while collaborating across teams.

You are comfortable operating in a fast-paced, multi-project R&D environment. You are adaptable, proactive, and eager to learn and share knowledge. You are a collaborative team player with a customer-centric mindset.

You are detail-oriented with a focus on delivering high-quality, scalable solutions.

You will join Synopsys' dynamic R&D organization in Bengaluru, working with a diverse team of engineers focused on developing industry-leading EDA tools and automation frameworks.

The team collaborates globally, engaging with architecture, verification, QA, and product management experts to deliver integrated, high-impact solutions for semiconductor and system companies.

Together, you will drive innovation in IP packaging and subsystem assembly, shaping the future of chip design and verification.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You are a passionate and detail-oriented engineering professional eager to make a tangible impact in the world of semiconductor design and software development. With a strong foundation in electrical engineering and hands-on experience in EDA solutions, you thrive in collaborative environments and are comfortable navigating the complexities of modern chip design.

Responsibilities: Designing, implementing, maintaining, testing, and documenting software modules and sub-systems for EDA products. Collaborating with expert professionals to accomplish development objectives and deliver high-quality software solutions. Learning and employing industry best practices to ensure robust and reliable code. Conducting basic bug verification, release testing, and beta support for assigned products, ensuring product stability. Researching and resolving problems discovered by QA or product support, developing innovative solutions to technical issues. Working under the close supervision of a development manager, receiving guidance and mentorship to foster professional growth. Participating in team meetings and contributing to knowledge sharing and process improvement initiatives.

The Impact You Will Have: Enhancing the performance and reliability of Synopsys' EDA software, directly influencing semiconductor design outcomes. Driving innovation in chip design and verification, enabling customers to achieve faster time-to-market for their products. Supporting the creation of high-performance silicon chips and software content for diverse applications, from automotive to AI. Contributing to industry-leading solutions for signal integrity analysis, IC signoff, and electronic migration challenges. Improving customer satisfaction by resolving technical issues quickly and efficiently. Advancing your own skills and knowledge while helping shape the future of technology at Synopsys.

What You’ll Need: BS in Electrical Engineering or a related field, with at least 5 years of relevant experience. Experience working with EDA solutions, EDA companies, semiconductor design companies, or semiconductor foundries. Proficiency with tools such as Ansys Totem, IC layout editors, and spice simulation tools. Knowledge of Ansys or other commercial CAE, CAD, EDA software platforms. Familiarity with circuit-level and timing analysis, especially in signal integrity applications. Understanding of Electronic Migration, Electro Static Discharge, and other IC signoff criteria.

Who You Are: Logical thinker with strong problem-solving abilities. Excellent interpersonal and communication skills, able to work effectively in diverse teams. Organized and detail-oriented, with a sense of urgency and strong follow-up skills. Adaptable and eager to learn new technologies and methodologies. Collaborative team player, committed to knowledge sharing and continuous improvement.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits at Synopsys: Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries.

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Turn launches into cultural moments and reviews into competitive advantages.

Execute the full product PR lifecycle regionally: adapt global messaging, coordinate embargoes across time zones, manage reviewer outreach, and drive post-launch amplification in UK, Nordics, and Benelux across all of Elgato's product categories.

Build and maintain tiered regional media lists across tech, creator-focused, lifestyle, and business publications: UK, Nordics and Benelux.

Develop region-specific reviewer briefing kits that translate specs into creator outcomes and drive the execution of Elgato products strategy in PR across European markets.

Manage seeding strategy and review unit logistics across all covered markets, ensuring key outlets receive early access ahead of embargoes.

Track regional review sentiment, message pull-through, and share of voice. Feed insights back to PR Lead and product/marketing teams.

Strategic PR & Thought Leadership

Shape the regional narrative. Bring global stories to life locally.

Adapt global story angles for regional relevance, identifying local hooks around creator economy growth, gaming culture, and professional AV convergence in European markets.

Identify regional placement opportunities for thought leadership content (executive bylines, op-eds) in European tech and business publications.

Contribute to quarterly PR plans with regional objectives, target outlets, story angles, and KPIs aligned to market-specific business goals.

Monitor competitive communications across European markets weekly. Flag opportunities for Elgato to lead regional industry conversations.

B2B, Pro AV & Trade PR

Extend Elgato’s reach into European professional markets while keeping the brand authentic.

Adapt B2B messaging for European enterprise buyers, IT decision-makers, and AV integrators, emphasizing reliability, scalability, deployment simplicity, and total cost of ownership.

Write for European Pro AV and broadcast trade press in the language integrators and engineers speak.

Localize vertical positioning for corporate communications, education, houses of worship, and broadcast/production segments across European markets.

Support case study development by sourcing European customer stories and coordinating approvals.

Support EMEA B2B team with trade media outreach, European distributor announcements, and regional trade show PR.

Event & Speaker PR

Make Elgato unmissable at every European event that matters.

Develop event PR timelines for European shows: pre-event outreach, on-site media appointments, demo coordination, and post-event follow-up.

Identify and secure regional speaking opportunities at European events and relevant podcasts/webinars.

Prepare speaker briefing docs, talking points, and executive bios tailored to European audience context.

Compile post-event reports with regional coverage analysis, key conversations, and actionable learnings.

Crisis & Issues Management

Protect the brand. Move fast, stay calm, be transparent.

Execute regional crisis response following global playbooks, adapting messaging for European market nuances and media expectations.

Draft regional holding statements and Q&A documents that can be activated within hours, coordinating with PR Lead on messaging alignment.

Provide real-time regional media monitoring during active situations, flagging escalation risks in European press.

Coordinate with Corsair corporate communications when issues have European or parent-company implications.

European PR Coordination

Align the European PR network.

Coordinate with European PR team to ensure consistent messaging and launch timing across European markets.

Adapt global messaging frameworks and launch playbooks for European market nuances (language, cultural context, retail landscape).

Collaborate with European PR team on PR best practices to elevate media coverage quality and consistency.

Build and maintain media database across all covered markets.

AI-Powered PR (Cross-Cutting)

Use AI to elevate every aspect of the work.

Contribute to Elgato’s AI search visibility by systematically building regional earned media citations that feed into AI-generated search answers.

Leverage AI tools (e.g., ChatGPT, Claude, Gemini) to accelerate regional press release adaptation, pitch development, and briefing document creation.

Use AI-powered media monitoring to surface regional coverage trends, competitive signals, and emerging story angles across multiple European markets and languages.

Apply AI to media list research, journalist profiling, and outlet analysis to improve targeting precision across UK, Nordics, and Benelux.

Build AI-assisted workflows for regional coverage reporting and earned media value tracking.

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You will drive customer scenario reproduction, deep-dive debugging, and root-cause analysis of complex, cross-component issues. You will proactively identify product weak areas, corner cases, and scalability/performance risks and ensure early detection. You will work closely with R&D, Product Engineering, and Field teams to clarify requirements, influence design decisions, validate fixes, and ensure smooth integration.

You will lead functional, regression, stress, accuracy, and sign-off-oriented testing for STA features and advanced flows. You will architect and enhance automation frameworks using Perl, Tcl, and Python to improve productivity, robustness, and validation coverage. You will analyze large-scale validation and regression data to identify trends, systemic gaps, and improvement opportunities.

You will effectively leverage AI-assisted engineering tools (e.g., VS Code / Cursor-based workflows with multiple LLMs) for faster testcase and automation script development, debug acceleration and hypothesis generation, log analysis, flow understanding, and code reviews. You will apply sound technical judgment to validate, review, and refine AI-assisted outputs, ensuring correctness, accuracy, and compliance with quality standards.

You will prepare and present clear, executive-ready validation status, quality metrics, risks, and recommendations. You will participate in feature readiness reviews, postmortems, and continuous improvement initiatives. You will drive best practices in validation methodology, tooling, and knowledge sharing across the team.

As a STA PrimeTime Test & Validation Sr Specialist, you will own and drive quality sign-off for critical PrimeTime STA features. You will significantly reduce customer-reported issues through proactive, risk-based validation. You will improve tool accuracy, robustness, scalability, and real-world customer readiness. You will strengthen cross-team alignment by serving as a trusted technical Subject Matter Expert (SME).

You will elevate overall team capability through mentorship, technical leadership, and adoption of modern productivity tools. You will influence product roadmap and feature decisions through validation-driven insights.

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We are seeking an expert analog design engineer with a passion for high-speed integrated circuits and a drive to push the boundaries of SERDES technology. As a Sr Staff Engineer, you will lead the design and development of high-performance analog and mixed-signal solutions in advanced process nodes.

Key Responsibilities:

• Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.
• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.
• Collaborating with cross-functional teams, including analog, digital, and layout engineers,to optimize design and verification strategies for superior quality and project efficiency.
• Presenting and critically reviewing simulation data within project teams and at external industry panels or customer meetings.
• Overseeing physical layout to minimize parasitics, device stress, and process variations, ensuring robust manufacturability and reliability.
• Documenting design features, creating comprehensive test plans, and ensuring traceability throughout the development lifecycle.
• Consulting on electrical characterization of SERDES IP, analyzing customer silicon data, and proposing enhancements or post-silicon updates as needed.

Impact:

• Driving the next generation of high-speed data communication through pioneering SERDES architectures.
• Enabling Synopsys customers to achieve industry-leading performance, power efficiency, and reliability in their products.
• Fostering a culture of technical excellence and innovation within a diverse, high-caliber design team.
• Accelerating project timelines by streamlining design and verification methodologies.
• Enhancing the overall quality and competitiveness of Synopsys IP offerings through expert problem-solving and continuous improvement.
• Mentoring and developing junior engineers, strengthening the team's collective expertise and future leadership pipeline.

Requirements:

• Ph.D. with 6+ years, or M.Sc. with 8+ years of practical analog IC design experience, preferably in Electrical Engineering, Computer Engineering, or a related field.
• Deep expertise in transistor-level circuit design and sound CMOS fundamentals.
• Hands-on design experience with one or more SERDES sub-circuits (e.g., receive equalizers, samplers, drivers, serializers/deserializers, voltage-controlled oscillators, PLLs, bandgap references, ADCs, DACs).
• Proficiency with schematic entry, physical layout, and design verification tools; familiarity with SPICE simulators and simulation methodologies.
• Experience with analog/digital co-design for performance optimization, including calibration, adaptation, and timing handoff.
• Knowledge of reliability and layout effects (EM, IR, aging, matching, proximity, ESD, etc.).
• Proficiency in Verilog-A for analog behavioral modeling, and experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.
• Excellent communication, presentation, and documentation skills.

Team:

• You will join a dynamic, growing analog and mixed-signal design team focused on developing cutting-edge Multi-Gbps SERDES IP.
• The team is composed of passionate engineers from diverse backgrounds, collaborating closely with digital designers, layout specialists, and software/CAD experts.
• Our culture emphasizes technical excellence, innovation, and continuous learning.
• With access to best-in-class design tools and in-house support, this team thrives on solving industry-defining challenges and delivering world-class IP to Synopsys' global customers.

Rewards and Benefits:

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Our total rewards include both monetary and non-monetary offerings.
• Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.

Key Responsibilities:

• Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes
• Driving timing closure efforts, especially above ~2GHz
• Resolving complex challenges related to mixed signal and macro IP integration
• Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements
• Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams
• Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects
• Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation

Requirements:

• Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications
• Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)
• Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration
• Strong analytical and problem-solving skills, with a track record of resolving complex technical issues
• Ability to independently lead project tasks, mentor junior team members, and work collaboratively

Benefits:

• Comprehensive medical and healthcare plans
• Time away from work for vacation, sick leave, and family care
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries

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We currently have 700 open roles

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Application Engineering, Sr Enginer

Bengaluru, Karnataka, India

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Hire Type EmployeeJob ID 17054Date posted 04/20/2026

A peek inside our office

Po Popal

Workplace Resources, Sr Director

Alternate Job Titles:

• Applications Engineer – Static Timing Analysis
• PrimeTime Specialist
• STA Solutions Engineer
• Silicon Verification Engineer
• Customer Success Engineer – EDA Tools

We Are:

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips,faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance,eliminating months off their project schedules.

You Are:

You are a seasoned engineer with a keen interest in cutting-edge semiconductor technology and a passion for delivering customer-centric solutions. With a strong background in static timing analysis, you understand the intricacies of chip design and the critical role of timing verification in successful tapeouts. You thrive on solving complex technical challenges, whether through competitive benchmarking, customer training, or advanced collaboration initiatives. Your experience with Synopsys PrimeTime sets you apart, and you’re adept at explaining technical concepts to both engineers and management audiences.

You possess exceptional communication skills, enabling you to build relationships and foster trust with customers and internal teams alike. You are comfortable leading technical discussions, delivering workshops, and supporting users through the entire lifecycle of their projects. Your analytical mindset helps you dissect timing-related issues, process variations, and signal integrity challenges, ensuring that your customers achieve optimal results.

As a collaborative team player, you value diverse perspectives and enjoy working across functions,including R&D, marketing, and sales,to drive product enhancements and customer satisfaction. You are proactive, resourceful, and adaptable, always ready to learn and grow in a fast-evolving industry. Your dedication to excellence and innovation makes you a valuable asset to Synopsys and its customers.

What You’ll Be Doing:

• Driving increased adoption of Synopsys PrimeTime by executing competitive benchmarks and product evaluations for customers.
• Articulating product advantages and technical superiority to customer design teams and management in both pre-sale and post-sale engagements.
• Delivering customer training sessions, workshops, and hands-on support to enhance user proficiency and satisfaction.
• Providing tape-out support, troubleshooting timing issues, and guiding customers through complex design challenges.
• Collaborating with R&D, marketing, and sales teams to relay customer feedback and contribute to product enhancements.
• Engaging in advanced initiatives that foster innovation and strengthen customer relationships.
• Developing technical documentation and best practices to streamline customer adoption and usage.

The Impact You Will Have:

• Accelerating customer project schedules by enabling efficient and accurate timing analysis using PrimeTime.
• Enhancing product usage and satisfaction, driving customer loyalty and long-term partnerships.
• Contributing to the continuous improvement of Synopsys STA tools by providing actionable insights from real-world customer engagements.
• Supporting industry-leading chip design teams in achieving successful tapeouts and meeting performance targets.
• Empowering customers to overcome complex timing, process variation, and signal integrity challenges.
• Strengthening Synopsys’ reputation as the provider of choice for advanced silicon design and verification solutions.

What You’ll Need:

• Hands-on experience with Synopsys PrimeTime static timing analysis tool.
• Deep understanding of timing corners, modes, process variations, and signal integrity issues.
• Familiarity with synthesis, physical design, extraction, and ECO methodologies.
• Strong proficiency in TCL scripting for tool customization and automation.
• Excellent verbal and written communication skills, with prior customer-facing experience preferred.
• BSEE or equivalent with 3–5 years of relevant experience, or MSEE/equivalent with 2–4 years.

Who You Are:

• Clear, confident communicator able to engage technical and non-technical audiences.
• Analytical problem-solver with a detail-oriented approach to complex technical challenges.
• Collaborative team player who thrives in cross-functional environments.
• Adaptable and resourceful, comfortable with evolving technologies and project priorities.
• Customer-focused, demonstrating empathy and proactive support.
• Self-motivated, eager to learn and contribute to innovation.

The Team You’ll Be A Part Of:

You will join the applications engineering team supporting the industry-leading Static Timing Analysis tool, PrimeTime. The team’s mission is to drive customer success by delivering expert guidance and technical support, ensuring seamless adoption and optimal usage of Synopsys STA solutions. Working closely with customers and internal stakeholders, the team fosters a culture of innovation, collaboration, and continuous improvement, shaping the next generation of chip design and verification technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.

What You’ll Be Doing:

• Working closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM and Test solutions into customers’ projects.
• Enabling customers to realise the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys’ Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
• Driving the adoption of Synopsys’ SLM and DFT solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You’ll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
• 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.
• Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.
• Knowledge on memory defectivities soft errors and reliability.
• Familiarity with error correcting codes such as Hamming and Hsiao.
• Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.

• Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.
• Debugging abilities to identify and resolve issues in functional verification in UVM environment.
• Hands on experience in flow automation.
• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).
• Knowledge of Lint, CDC, RDC is a plus.
• Knowledge of physical implementation is not a must, but good to have.
• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.
• Customer facing experience is a plus – educating/guiding customer on technical details of a solution.
• Good to have:
• Hands-on bring-up and debug experience of silicon is a plus.
• Architecture/micro-architecture experience.
• Understanding of GenAI and Agentic AI workflows.

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As a Staff Engineer in Analog Design, you will be part of a team focused on developing high-speed SerDes physical interfaces and supporting analog blocks for advanced SoCs. You will work alongside passionate engineers who value technical excellence, innovation, and teamwork - driving the integration of new capabilities for the Era of Smart Everything.

Designing and validating analog and mixed-signal circuits, with a focus on high-speed SerDes interfaces (including drivers, receivers, clocking, PLL, DLL, and CDR). Conducting schematic entry, simulation, and final validation of analog blocks, from basic reference components to complex analog front-ends. Collaborating with layout engineers to review and optimize layout designs, minimizing the impact of parasitics on circuit performance. Developing and validating custom digital circuits for high-speed applications, ensuring timing closure and constraint checks using industry standard tools such as Primetime and Nanotime. Utilizing IC design tools and SPICE simulators for simulation, verification, and performance analysis of analog circuits. Engaging with international teams to share knowledge, solve problems, and drive innovation in analog design methodologies.

Key responsibilities include: Designing and validating analog and mixed-signal circuits Conducting schematic entry, simulation, and final validation of analog blocks Collaborating with layout engineers to review and optimize layout designs Developing and validating custom digital circuits Utilizing IC design tools and SPICE simulators Engaging with international teams

The ideal candidate will have: MSc in Electrical or Computer Engineering (or equivalent) with a solid background in transistor-level circuit design 5+ years of hands-on experience in analog circuit design, especially in high-speed mixed-signal environments Strong knowledge of deep submicron CMOS technologies and their application in modern ICs Experience with SPICE simulators, simulation methods, and verification tools for analog circuit analysis Familiarity with industry standard IC design tools and digital circuit validation, including STA timing closure (Primetime, Nanotime, or equivalent) Preferred: Knowledge of Synopsys EDA tools and familiarity with Unix and scripting languages (TCL, Python)

As a Staff Engineer, you will be responsible for delivering high-quality designs, collaborating with cross-functional teams, and driving innovation in analog design methodologies. You will also be expected to mentor junior engineers and contribute to the development of new design techniques and tools.

If you are a motivated and experienced analog design engineer looking to take your career to the next level, we encourage you to apply for this exciting opportunity.

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You will be responsible for owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/parallel analysis flows. You will define long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership.

Key responsibilities include:

• Owning and evolving major architectural components of PrimeTime
• Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis
• Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems
• Leading the design and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear behaviours
• Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off
• Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges
• Diagnosing systemic issues involving SDC interpretation, timing convergence, path pessimism/optimism, and tool correlations across flows
• Mentoring and influencing engineers through technical reviews, discussions, and leadership,raising the technical bar across the organization

As a Sr Staff Engineer, you will have a strong sense of ownership and accountability, and be able to drive technical excellence and innovation. You will be a collaborative influencer, able to mentor and inspire technical teams, and have excellent communication skills, capable of articulating complex technical concepts to diverse audiences.

You will join a team that is passionate about delivering innovative solutions that define industry standards for timing sign-off. Together, you will tackle complex architectural challenges, drive technical excellence, and shape the future of silicon design by enabling customers to achieve reliable and high-performance tapeouts.

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Key responsibilities include:

• Driving customer success on RTL-to-GDSII implementation flows with focus on PPA (performance, power, area)
• Owning/leading technical execution on key topics: physical synthesis, timing closure, CTS, routing
• Troubleshooting complex design/tool issues, reproducing, isolating, and driving resolution with R&D
• Building/standardizing methodologies; automating workflows using Tcl and Python (or Perl/Tcl where applicable)
• Delivering technical trainings, best practices, application notes, and customer-facing presentations
• Collaborating cross-functionally with R&D, Product, and worldwide AE teams to influence features and improve product quality

Requirements include:

• BS/MS in Electrical Engineering, Computer Engineering, or related field, with 5+ years relevant experience
• Strong hands-on knowledge of RTL-to-GDSII and backend implementation
• Experience with Fusion Compiler, IC Compiler II (ICC2) or similar P&R tools
• Solid understanding of timing analysis/closure, CTS, routing, and advanced nodes
• Scripting skills in Tcl and Python for automation and productivity
• Strong communication skills in English; comfortable working with global customers/teams

You'll be successful if you're analytical, structured, and calm under pressure when debugging complex issues, proactive in driving alignment across customers, AE peers, and R&D, comfortable juggling multiple priorities while maintaining high execution quality, and curious and continuously learning new flows, nodes, and AI-enabled productivity approaches.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.

Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.

• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.

• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.

• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.

• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.

• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.

• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.

• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.

• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.

• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of: You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

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Job Description

As an Analog Mixed-Signal Engineer at Synopsys, you will be responsible for designing and developing high-performance memory interface solutions that power next-generation technologies. You will work closely with cross-functional teams to meet complex design specifications and project goals.

Responsibilities

• Design and develop DDR/HBM Memory Interface I/O circuits, including GPIO and special I/Os, ensuring robust performance and reliability.
• Collaborate closely with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project milestones.
• Execute circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Apply deep knowledge of CMOS processes and analog/mixed-signal circuitry to innovate and refine design methodologies.
• Review and optimize circuit layouts, ensuring compliance with ESD and JEDEC standards for DDR interfaces.
• Participate in design reviews, provide technical input, and contribute to the continuous improvement of design flows and best practices.
• Document design processes, test plans, and results, supporting knowledge sharing and future project success.

Impact

• Drive the development of high-performance memory interface solutions that power next-generation technologies.
• Enhance the robustness and reliability of Synopsys' analog and mixed-signal IP portfolio.
• Ensure products meet or exceed industry standards, supporting customer success and market leadership.
• Influence cross-functional teams by sharing insights and best practices in circuit design and layout.
• Contribute to the delivery of cutting-edge silicon solutions for global semiconductor leaders.
• Support continuous innovation, helping Synopsys stay ahead in a competitive, fast-moving industry.

Requirements

• BTech/MTech in Electronics or Electrical Engineering.
• 1–3 years of experience in analog/mixed-signal circuit design, with expertise in CMOS processes and deep submicron technologies.
• Proficiency in CMOS circuit design and layout methodologies; experience with ESD concepts is a plus.
• Familiarity with ASIC design flows and JEDEC DDR interface requirements, including DDR Timing, ODT, and SDRAM functionality.
• Ability to work with cross-disciplinary teams to meet complex design specifications and project goals.

Team

You will join a world-class engineering team focused on analog and mixed-signal IP development for cutting-edge memory interfaces. Our team thrives on innovation, collaboration, and technical excellence, working closely with global experts to deliver industry-leading solutions for top-tier semiconductor clients. We foster an inclusive and supportive culture where every member's contributions are valued and professional growth is encouraged.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your primary focus will be on developing core algorithms for global placement, detailed placement, global routing, detailed routing, and timing optimization. You will also improve product usability, robustness, and user experience, ensuring high-quality engineering workflows.

To succeed in this role, you will need to have a strong background in data structures and algorithms, experience in EDA tool development, and proficiency in C/C++ programming. You will also need to be able to collaborate closely with cross-functional teams to ensure seamless integration of new capabilities across Fusion Compiler.

As a Staff Engineer, you will have the opportunity to drive the development of cutting-edge software tools that power the future of technology. You will enhance the performance and capabilities of Synopsys' chip design and software security solutions, contributing to the success of self-driving cars, 3DIC, AI, machine learning, the cloud, 5G, and IoT technologies.

In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Your responsibilities will include:

Implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below). Performing timing closure for designs operating above ~4GHz, ensuring robust performance and reliability. Collaborating daily with local and US counterparts to align on technical challenges and project milestones. Integrating mixed-signal macro IPs and optimizing their placement within complex chip architectures. Designing and building efficient clock trees with exceptionally tight skew balancing to meet stringent requirements. Driving continuous improvement in implementation methodologies and sharing best practices across the team. Participating in design reviews, providing critical feedback and innovative solutions to enhance project outcomes.

As a senior engineer, you will have a strong technical foundation in ASIC physical design and hands-on experience with DDR IP implementation and timing closure, especially at advanced nodes (10nm, 7nm, 6nm and below). You will also have proficiency in EDA tools for synthesis, place-and-route, and timing analysis.

If you are a detail-oriented and analytical individual with a drive for technical excellence, effective communication skills, and a collaborative mindset, we encourage you to apply for this exciting opportunity.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

The ideal candidate will have a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you will thrive in fast-paced, innovative environments and be eager to tackle new technical challenges.

Your expertise will span the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You will have experience in both block-level and full-chip floor-planning, and you’ll be adept at navigating timing constraints and closing timing on aggressive schedules.

You will utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions. You will develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.

As a Senior Staff SOC Engineer, you will contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed. You will accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.

The ideal candidate will have a Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field, and 8+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).

If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

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We currently have 700 open roles.

Innovation Starts Here

STA PrimeTime Test & Validation Sr Specialist

Technical Leadership & Validation Ownership

• Lead and own validation of complex PrimeTime STA features and flows, from requirement analysis through quality sign-off.
• Define and drive validation strategy, depth, and coverage for assigned functional areas.
• Act as technical lead for L1/L2 engineers, providing guidance on STA concepts, debugging approaches, testcase design, and best practices.
• Review and approve validation plans, testcases, regression results, and quality sign-off metrics.

Product Quality, Debug, and Cross-Team Collaboration

• Drive customer scenario reproduction, deep-dive debugging, and root-cause analysis of complex, cross-component issues.
• Proactively identify product weak areas, corner cases, and scalability/performance risks and ensure early detection.
• Work closely with R&D, Product Engineering, and Field teams to clarify requirements, influence design decisions, validate fixes, and ensure smooth integration.
• Lead functional, regression, stress, accuracy, and sign-off-oriented testing for STA features and advanced flows.

Automation, Data Analysis & AI-Assisted Productivity

• Architect and enhance automation frameworks using Perl, Tcl, and Python to improve productivity, robustness, and validation coverage.
• Analyze large-scale validation and regression data to identify trends, systemic gaps, and improvement opportunities.
• Effectively leverage AI-assisted engineering tools (e.g., VS Code / Cursor-based workflows with multiple LLMs) for:
• Faster testcase and automation script development
• Debug acceleration and hypothesis generation
• Log analysis, flow understanding, and code reviews
• Improving documentation quality and consistency
• Apply sound technical judgment to validate, review, and refine AI-assisted outputs, ensuring correctness, accuracy, and compliance with quality standards.

Communication & Continuous Improvement

• Prepare and present clear, executive-ready validation status, quality metrics, risks, and recommendations.
• Participate in feature readiness reviews, postmortems, and continuous improvement initiatives.
• Drive best practices in validation methodology, tooling, and knowledge sharing across the team.

The Impact You Will Have

• Own and drive quality sign-off for critical PrimeTime STA features.
• Significantly reduce customer-reported issues through proactive, risk-based validation.
• Improve tool accuracy, robustness, scalability, and real-world customer readiness.
• Strengthen cross-team alignment by serving as a trusted technical Subject Matter Expert (SME).
• Elevate overall team capability through mentorship, technical leadership, and adoption of modern productivity tools.
• Influence product roadmap and feature decisions through validation-driven insights.

What You’ll Need

• Strong, hands-on understanding of Static Timing Analysis fundamentals.
• BSEE with 5+ years of relevant experience OR MSEE with 4+ years of relevant experience.
• Deep hands-on experience with:
• Synopsys PrimeTime or equivalent STA tools
• Advanced timing concepts, SDC constraints, and real-world sign-off scenarios
• OCV/AOCV/POCV, derates, PBA, ECO, and what-if analysis flows
• Hierarchical, distributed, and large-scale STA flows
• Proven ability to debug complex, ambiguous, cross-component issues.
• Strong proficiency in Perl, Tcl, and Python for automation and framework development.
• Experience using AI-assisted development tools responsibly to enhance engineering productivity and validation quality.
• Track record of technical ownership, leadership, and sound decision-making.
• High standards for quality, rigor, documentation, and sign-off discipline.

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As a seasoned engineering professional with a passion for advancing electronic design automation (EDA) and CAD automation, you will thrive on solving complex technical challenges and enjoy collaborating with diverse teams to deliver robust, scalable solutions. Your expertise is rooted in front-end synthesis, timing constraints, and digital design flows, and you have a keen eye for detail and quality.

You will design, develop, and enhance logic synthesis features and automation flows for industry-leading EDA solutions. You will own and maintain synthesis capabilities to optimize timing, area, power, and Quality of Results (QoR). You will develop and debug solutions across end-to-end EDA flows, understanding interactions between synthesis, place & route, STA, and power analysis tools.

You will analyze and resolve complex customer and internal issues related to timing constraints (SDC), synthesis behavior, and flow integration. You will collaborate with architecture, verification, QA, and product management teams to deliver integrated, production-quality EDA solutions. You will participate actively in technical design discussions, code reviews, and roadmap planning to shape future product directions.

You will ensure high engineering quality through unit testing, regression support, and adherence to best development practices. You will contribute to internal documentation, knowledge sharing, and mentoring junior engineers to foster team growth.

The impact you will have includes enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs. You will drive innovation in EDA automation, shaping the future of semiconductor design flows. You will improve product reliability, scalability, and integration across Synopsys' IP packaging and subsystem assembly solutions.

To be successful in this role, you will need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. You will require 6–8 years of experience in EDA tools, CAD automation, or system-level software development. You will need strong proficiency in C/C++ for large-scale software development.

You will demonstrate a strong sense of ownership, accountability, and technical leadership. You will have clear and effective written and verbal communication skills to engage with technical and non-technical audiences. You will be able to work independently on complex problems while collaborating across teams.

You will join a highly collaborative R&D team at Synopsys dedicated to advancing EDA tool development and automation. The team focuses on integrated design flows for IP packaging and subsystem assembly. You will work alongside talented engineers, architects, and product managers, contributing to innovative solutions that set industry standards and drive customer success.

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You Are: A highly skilled engineer with strong expertise in ASIC prototyping, emulation, and debug, especially using HAPS and Zebu platforms. You’re a problem-solver with excellent communication abilities, able to support customers and collaborate with cross-functional teams. You enjoy integrating hardware and software, thrive on technical challenges, and are eager to deliver innovative solutions that help customers succeed.

Responsibilities:

• Building and supporting integrated solutions using HAPS and Zebu systems.
• Debugging complex issues involving clocking, timing, and tool flows.
• Developing user models/interfaces for seamless system integration.
• Providing technical support and guidance to customers.
• Documenting methodologies and troubleshooting steps.
• Collaborating with internal and customer teams to optimize solutions.

The Impact You Will Have:

• Accelerating customers’ ASIC development with robust emulation and prototyping solutions.
• Improving system integration and verification efficiency.
• Enhancing customer satisfaction with timely, expert support.
• Contributing technical insights for product improvement.
• Strengthening Synopsys’ reputation for innovation and service.
• Building strong, trust-based relationships with clients.

Requirements:

• Experience with ZeBu and HAPS prototyping systems.
• Expertise in clocking, timing, and integration flows.
• Proficiency in user model/interface development.
• Strong debugging and problem-solving skills.
• Excellent customer communication abilities.

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are looking for a passionate and driven STA Expert with a strong technical leadership and execution skills in Static Timing Analysis and design timing & power closure flows and methodologies. You will independently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

Key Responsibilities:

• Independently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute static timing analysis (STA), power analysis, synthesis and timing/power closure to meet stringent performance and power targets.
• Develop and validate timing constraints at block-level or Full SoC level.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.

Requirements:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 12+ years of relevant experience in static timing analysis, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience of constraints development, validation, static timing analysis (STA), power analysis, Timing and power ECO generation.
• Proficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, Tweaker.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.

As a Principal Engineer at Synopsys, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

Rewards and Benefits:

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Design on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability.

Execute digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.

Drive post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.

Perform physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff.

Collaborate with architects and circuit design engineering teams to create and refine new flows and methodologies.

Ensure pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.

Accelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.

Optimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.

Enhancing product reliability and differentiation in the market, reducing risk for customers and partners.

Driving innovation in physical design, verification, STA, and signoff methodologies and tools.

Contributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.

Collaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.

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We are seeking a passionate and experienced Field Application Engineer to join our team. As a Field Application Engineer, you will serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling. You will provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy.

Responsibilities:

Serve as the primary technical interface for strategic customers leveraging PrimeLib for advanced library characterization and modeling. Provide expert guidance on integrating PrimeLib into diverse EDA flows, ensuring optimal performance and accuracy. Lead product demonstrations, evaluations, and proof-of-concept projects that showcase PrimeLib's capabilities in real-world scenarios. Assist customers in optimizing PrimeLib usage for various different technologies nodes including cutting-edge process nodes such as 3nm and 2nm technologies. Troubleshoot and resolve complex technical challenges related to timing, power, and signal integrity modeling. Collaborate with R&D and product teams to influence the PrimeLib roadmap, advocating for customer needs and emerging technology trends. Develop and deliver technical training, best practices, and documentation to empower both customers and internal teams. Represent Synopsys and PrimeLib at industry conferences, technical forums, and customer workshops.

The Impact You Will Have:

Accelerate customer adoption and success with PrimeLib, directly influencing the design of next-generation semiconductor products. Drive technical excellence and innovation by bridging customer requirements and R&D advancements. Enhance Synopsys' reputation as a trusted technology partner and thought leader in library characterization and EDA solutions. Shape the evolution of PrimeLib by capturing and relaying key customer insights to product development teams. Facilitate knowledge sharing and best practices that elevate the capabilities of customers and colleagues alike. Promote the adoption of advanced semiconductor process technologies through expert technical support and guidance. Build lasting relationships with Tier-1 semiconductor companies and industry leaders.

What You’ll Need:

BS/MS in Electrical Engineering, Computer Engineering, or a related field (PhD preferred). 8+ years of experience in semiconductor design, library characterization, or EDA application engineering. Strong background in timing, power, variation, and signal integrity analysis for standard cell libraries. Hands-on expertise with characterization tools such as PrimeLib, Liberate, or SiliconSmart, and SPICE simulators. Advanced scripting skills (Python, Perl, TCL) for automation and flow customization. Familiarity with advanced process technologies, variation modeling, and Liberty format (including LVF/CCS/CCSN/CCSP models). Excellent verbal and written communication skills, with a proven ability to present complex technical concepts to varied audiences.

Who You Are:

A collaborative team player who excels in cross-functional environments and values diverse perspectives. Detail-oriented, analytical, and resourceful problem-solver with a passion for tackling technical challenges. Strong communicator who can build trust and rapport with customers, partners, and internal stakeholders. Adaptable and eager to learn, with a growth mindset and commitment to continuous improvement. Customer-focused and proactive, always striving to deliver exceptional service and solutions. Comfortable with ambiguity and able to thrive in fast-paced, dynamic settings.

The Team You’ll Be A Part Of:

You will join a dynamic, high-impact Customer Application Services team focused on enabling customer success with Synopsys’ PrimeLib product. Our team works closely with R&D, product management, and global customers to deliver technical excellence, foster innovation, and drive the adoption of industry-leading library characterization solutions. We value open communication, knowledge sharing, and a collaborative spirit that empowers each member to make meaningful contributions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you're adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams,architecture, verification, physical implementation, and firmware,to deliver industry-leading SERDES PHY IP solutions.

Your leadership style is empowering, fostering growth and development within your team, and you're committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and powers target while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you're excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you.

What You'll Be Doing:

• Leading a diverse team of design engineering the development of next-generation SERDES PHY IP solutions.

• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

• Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.

• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.

• Mentoring and developing team members, fostering technical growth, and a culture of innovation.

• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

The Impact You Will Have:

• Delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency.

• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.

• Driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.

• Enhancing product quality and reliability through rigorous design and verification processes/Flows.

• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

What You'll Need:

• Bachelor's degree or higher in Electrical Engineering, with 8+ years of complex technical development experience.

• Minimum 2 years' experience in people management and employee development.

• Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation.

• Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA), CDC/RDC, DFT, and power optimization.

• Excellent communication skills and the ability to work independently and collaboratively.

• Understanding the PCIe and Ethernet standard is a plus.

Who You Are:

• Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure.

• Strong problem-solver with a strategic, analytical mindset.

• Inspirational leader who motivates and develops technical talent.

• Collaborative team player who excels in cross-functional environments.

• Effective communicator who can translate complex technical concepts to diverse audiences.

The Team You'll Be A Part Of:

You'll join the Synopsys SERDES PHY IP team,a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world's most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys' leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we drive the innovations that shape the way the world lives, works, and connects. Our technology is foundational to the Era of Pervasive Intelligence,from autonomous systems and high-performance computing to artificial intelligence and advanced connectivity.

As a global leader in electronic design automation, semiconductor IP, and system design solutions, we enable customers to deliver complex, high-performance silicon and software products with confidence.

Technical & Program Leadership

• Lead and oversee end-to-end SoC physical design execution, from specification through post-silicon bring-up, using Synopsys EDA tools and IP.
• Provide technical direction and architectural guidance on Place & Route, timing closure, power integrity (IREM), extraction, and physical verification.
• Act as a senior escalation point for complex technical challenges, driving resolution through sound engineering judgment.
• Ensure consistent delivery excellence across turnkey projects and customer advisory engagements.
• Influence and evolve design methodologies and best practices within the broader SoC organization.

People Management & Team Development

• Build, lead, and develop a high-performing SoC design team in Vietnam, including hiring, onboarding, coaching, and performance management.
• Establish clear goals, expectations, and development plans aligned with Synopsys’ engineering and leadership frameworks.
• Mentor senior engineers and cultivate future technical and people leaders to support long-term capability growth.
• Foster a culture of technical rigor, accountability, inclusion, and continuous improvement.

Stakeholder & Business Partnership

• Partner closely with Business Units, R&D, and Sales to align engineering execution with product strategy and customer needs.
• Serve as a trusted technical advisor to customers, customer design teams, and internal stakeholders.
• Contribute to workforce planning, delivery commitments, and risk management within the Vietnam organization.
• Play a key role in scaling and strengthening Synopsys’ SoC engineering capability in Vietnam as part of the global organization.

The Impact You Will Have

• Enable scalable, high-quality delivery of advanced SoC designs.
• Elevate technical capability and execution maturity within Synopsys Vietnam.
• Drive innovation in physical design methodology and engineering best practices.
• Improve customer satisfaction through strong technical leadership and trusted advisory support.
• Develop and retain critical engineering talent in a highly competitive semiconductor market.
• Strengthen Synopsys’ reputation as a long-term technology and talent leader in Vietnam.

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As a Sr Staff Engineer in ASIC Physical Design, you will contribute to the development of advanced semiconductor solutions, collaborating with cross-functional teams to design, verify, and manufacture complex SoCs and test chips. Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.

Key Responsibilities:

• Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.
• Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.
• Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.
• Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).
• Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.
• Driving tool flow automation and debugging to enhance productivity and design reliability.
• Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.

Impact:

• Enable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.
• Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.
• Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.
• Bolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.
• Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.
• Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.

Requirements:

• 9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.
• Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.
• Familiarity with IP integration, test chip methodology, and advanced verification flows.
• Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.
• Experience coordinating complex, cross-functional projects and leading technical execution.
• Authorization to work in the USA.

Team:

You'll join the Test Chip PHY development team within Synopsys's Silicon IP business. This group is dedicated to integrating and validating Synopsys's broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

Key Responsibilities:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence
• Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency

Key Requirements:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs
• Exposure to high-frequency design and low-power design methodologies

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Key Responsibilities:

• Design and implement physical design flows for SLM IPs and subsystems, including state-of-the-art SLM Controllers and on-chip Monitors.
• Execute RTL2GDS flows on advanced process nodes (16nm to 3nm and beyond), ensuring robust performance and reliability.
• Perform static timing analysis, synthesis, and layout closure using industry-leading EDA tools, preferably Synopsys PrimeTime, ICC2, Design Compiler, or Fusion Compiler.
• Collaborate with cross-functional teams to integrate soft and mixed-signal IPs, optimize design margins, and address high-frequency, multi-voltage, and low-power requirements.
• Develop and enhance automation scripts (TCL/PERL) to streamline design processes and improve execution efficiency.
• Participate in project planning, execution, and mentoring, supporting both internal teams and external customers with technical expertise and guidance.
• Contribute to the signoff and verification of designs, ensuring compliance with quality and reliability standards.

Impact:

• Accelerate the integration and deployment of next-generation SLM products, enabling customers to bring differentiated solutions to market faster and with reduced risk.
• Optimize semiconductor lifecycle management through innovative hardware IP, test, and analytics, enhancing performance, power, area, and yield.
• Drive advancements in chip design and verification methodologies, supporting the evolution of process nodes and IP integration.
• Enhance reliability and scalability of technology products, contributing to breakthroughs in AI, IoT, automotive, and cloud sectors.
• Empower global teams and customers with robust solutions, technical guidance, and effective collaboration.
• Support Synopsys' leadership in the Era of Smart Everything, powering the technologies that shape our connected world.

Requirements:

• Strong experience in standard ASIC RTL2GDS physical implementation and signoff flows.
• Hands-on expertise in synthesis, pre-layout STA, post-layout STA, and CTS tools.
• BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience.
• Automation-focused mindset with proven experience in scripting (TCL/PERL) and custom flow development.
• Exposure to soft and mixed-signal IPs, high-frequency/multi-voltage designs, and low-power methodologies.
• Proficiency with EDA tools from any vendor, preferably Synopsys tools (PrimeTime, ICC2, Design Compiler, Fusion Compiler).
• Solid understanding of OCV, POCV, derates, crosstalk, and design margins.
• Experience in layout of digital blocks, timing constraints, STA, and timing closure.
• Experience with PVT-sensors and/or DFT/DFx technologies is a strong plus.

Who You Are:

• Collaborative and inclusive team player who values diversity and supports others.
• Excellent communicator, able to convey complex technical concepts clearly and effectively.
• Mentor and leader, providing guidance and support to peers and junior engineers.
• Adaptable and innovative, eager to learn and embrace new technologies and methodologies.
• Self-motivated with strong project execution and planning skills.
• Customer-focused, dedicated to delivering high-quality solutions and support.

The Team You’ll Be A Part Of:

You’ll join the rapidly expanding Hardware-Analytics and Test (HAT) business unit as a member of the SLM Hardware Group (SHG). The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities:

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

The Impact You Will Have:

Enable Synopsys to deliver industry-leading, high-performance IP cores that power next-generation technologies.

Contribute to the successful execution of complex, global projects that set new standards in chip design and verification.

Accelerate time-to-market for customers in commercial, enterprise, and automotive sectors by delivering robust, reliable IP solutions.

Elevate the technical capabilities of your team through mentorship and leadership, cultivating a culture of continuous learning and innovation.

Drive improvements in design quality, efficiency, and scalability through process optimization and automation.

Directly influence product architecture and feature enhancements, ensuring alignment with customer needs and emerging industry trends.

What You’ll Need:

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who You Are:

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a seasoned engineering leader with a passion for innovation and a deep understanding of physical design methodologies for cutting-edge semiconductor technologies. With a proven track record of successful project tape-outs, you thrive in collaborative, multidisciplinary environments, and you enjoy mentoring and guiding teams to achieve ambitious technical goals.

Your experience spans advanced FinFET nodes and the latest SERDES standards, and you possess a nuanced appreciation for both digital and mixed-signal architectures. You are methodology-driven, adept at software and scripting, and you have a strong grasp of CAD automation. Communication is your forte, whether you’re interfacing with peer groups, customers, or cross-functional teams.

Leading the physical implementation of advanced high-speed interface IPs and test-chips, from RTL to GDSII. Driving project execution for SERDES developments (56G/112G/224G PAM4/6) across multiple process nodes, including the latest FinFET technologies. Collaborating closely with front-end, analog, CAD, and product teams to ensure seamless integration and sign-off. Managing and mentoring a small team of engineers, fostering a culture of excellence, innovation, and continuous improvement. Developing and refining timing constraints and design architectures to ensure on-time delivery and optimal power/area targets. Applying advanced low-power design techniques and addressing the challenges of analog/digital interfaces in complex mixed-signal IPs. Contributing to methodology enhancements, CAD automation, and process improvement initiatives. Elevate Synopsys’ leadership in high-speed SERDES IP and mixed-signal solutions for next-generation silicon. Accelerate time-to-market for advanced interface IPs by ensuring robust and efficient physical implementation flows. Drive innovation in low-power and high-performance design, influencing industry standards and best practices. Mentor and empower engineering talent, building a high-performing team that delivers exceptional results. Strengthen cross-functional collaboration, optimizing integration and sign-off processes across technology domains. Enhance customer satisfaction through technical excellence, timely delivery, and superior product quality.

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You Are: You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 2+yrs experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies.

What You'll Be Doing: Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

The Impact You Will Have: Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys' leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

What You'll Need: B.Tech/M.Tech degree in Electronics or Electrical Engineering. 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies. Proficiency in analog/mixed signal design methodologies and layout flows. Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus. Basic understanding of ESD concepts and ASIC design flow. Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency. Strong written and verbal communication skills for effective team interactions.

Who You Are: Analytical thinker with strong problem-solving skills. Collaborative and adaptable, thriving in dynamic team settings. Detail-oriented and quality-driven, with a commitment to excellence. Proactive, self-motivated, and eager to learn new technologies. Effective communicator, capable of conveying technical concepts clearly. Resilient and resourceful, able to navigate complex challenges.

The Team You'll Be A Part Of: You will join a highly skilled engineering team specializing in DR I/O circuit design for memory interfaces. The team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking a creative and talented engineer to fill a FPGA Validation role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities.

The FPGA Design and Verification IP Prototyping team is responsible to build FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and test them to verify their compliance with leading edge industry standards. We play a vital role on supporting Synopsys IP business by validating key features, and mitigating ASIC potential faults early on, in a prototype.

Responsibilities:

• Design, implement, and verify FPGA-based systems for a variety of applications
• Validate FPGA-based IP prototype 'Device Under Test' against real-world devices, Test Equipment and other hardware systems
• Create and maintain comprehensive technical documentation
• Elaborate and execute test plans and test routines
• Detect, troubleshoot, debug, and investigate potential ASIC issues up front
• Establish and maintain relationships with cross-functional teams, internal and external customers

Key Qualifications:

• Bachelor's or master's degree in electrical engineering
• 5+ years of experience in FPGA design and development
• Design and simulate integrated circuitry using Verilog, System Verilog
• Expertise with industry-standard scripting languages such Tcl, Python, Perl and Bash
• Expertise with industry-standard interfaces and protocols such as AMBA AXI or APB.
• Experience with FPGA development tools such as XILINX Vivado. Familiarity with Synopsys Synplify or Protocompiler is a plus
• Experience in digital design methods such as floor planning, timing constraints definition, and static timing analysis
• Excellent verbal and written communication skills in English

Preferred Experience:

• Expertise with HAPS-100,HAPS-80 Boards and Protocompiler Flows
• Familiarity with peripheral interfaces like SD/eMMC and (LP)DDR
• Familiarity with simulation tools such as VCS
• Familiarity with laboratory equipment such as Oscilloscopes, Protocol-Analyzers

Travelling:

As a worldwide organization there is sometimes short term travel maybe required.

The Team You’ll Be a Part Of:

You will be joining the FPGA Design and Verification IP Prototyping team, a group of innovative engineers dedicated to building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs. The team plays a pivotal role in supporting Synopsys' IP business by validating key features, mitigating ASIC potential faults early, and ensuring compliance with industry standards. Collaboration and continuous learning are at the heart of the team, offering a stimulating, challenging, and rewarding environment with positive career development opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Key Responsibilities:

• Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability.
• Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals.
• Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies.
• Contributing to the ASIC design flow, from concept to implementation, including verification and documentation.
• Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process.
• Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Requirements:

• B.Tech/M.Tech degree in Electronics or Electrical Engineering.
• 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies.
• Proficiency in analog/mixed signal design methodologies and layout flows.
• Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus.
• Basic understanding of ESD concepts and ASIC design flow.
• Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency.
• Strong written and verbal communication skills for effective team interactions.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: Year Required Skills: CMOS circuit design, analog/mixed signal design methodologies, layout flows, JEDEC DDR interface requirements, DDR Timing, ODT, SDRAM functionality, ESD concepts, ASIC design flow Preferred Skills: Not stated

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We are looking for a passionate and highly skilled engineer who thrives in a collaborative, fast-paced environment. With a deep understanding of analog design principles, you have honed your expertise in static timing analysis (STA) and timing characterization over 4-8 years in the semiconductor industry. You are driven by curiosity and a desire to solve complex challenges, always seeking innovative solutions to enhance performance and reliability.

As a STA and Timing Characterization Specialist, you will be responsible for driving DDR, HBM, and UCIE timing generation and validation in partnership with circuit design and layout teams. You will perform static timing analysis (STA) and timing characterization, ensuring robust timing constraints and accurate correlation with design requirements. You will also debug and resolve timing violations at both circuit and system levels, applying deep transistor-level simulation expertise.

You will utilize SiliconSmart, NanoTime, and advanced scripting to automate timing analysis workflows and improve efficiency. You will collaborate closely with internal development teams to communicate findings, propose solutions, and implement best practices. You will provide technical leadership, mentoring junior engineers, and championing quality and accountability throughout project lifecycles.

As a member of our team, you will be empowered to drive innovation and technical excellence, contributing to Synopsys' global leadership in chip design and integration.

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Experience Designer II, UI Motion at EA SPORTS FC Companion App

EA SPORTS is one of the most iconic brands in entertainment – connecting hundreds of millions around the world to the sports they love through a portfolio of industry-leading video games. With more opportunity than ever to create new, authentic experiences that bring joy, inclusivity, and immersion to a global community of fans, we invite you to join us and pioneer the future of football with EA SPORTS!

Role:

We at EA Sports have reached the next level of cohesion and craft by evolving into a modern Experience Design practice that brings UX and UI together, understanding that neither exists in a vacuum. The team is passionate and committed to developing an immersive player experience within FC.

You will use your creativity, passion and knowledge of motion and interactive design, branding, and modern UI/UX practices to create leading-edge interactive motion and visual experiences for highly engaged Football Club fans, helping translate the core FC experience into an elegant and intuitive mobile experience that seamlessly integrates into the broader FC ecosystem. You will craft motion flows, interaction moments, and broader visual motion experiences that enhance usability, feedback, and emotional engagement, creating delightful player experiences across the FC ecosystem.

You will work closely with Production and your partners across the Experience Design Team, Engineering, Game Design, Research, Art Direction and Creative Direction to create experiences that surprise, delight and inspire millions of players around the world to play.

We value designers who care deeply about craft and take pride in building polished, high-quality interactive experiences that ship to real players.

This is an opportunity to do career-defining work and be a part of EA's most successful franchise – EA SPORTS FC.

Responsibilities:

• Collaborate with other Experience Designers and report to your Experience Design Manager to craft high-quality interactive motion flows and interaction moments that enhance player engagement and emotion, contributing to FC's high standards for visual excellence.

• Partner with the UI/UX team, Game Designers, Producers, Art Directors, and Software Engineering teams to balance user needs, team goals, and project timelines while upholding high standards of motion and design quality.

• Work fluidly across 2D & 3D motion contexts, creating motion mockups and interaction explorations that support our product and feature vision, guiding development from concept to design reviews and implementation, and collaborating with engineers to bring motion to life in real-time.

• Leverage and expand our UI Design System to build cohesive user experiences, introducing motion patterns and interaction behaviors where valuable.

Requirements:

• A strong portfolio showcasing motion design work with a focus on user-centered, visually engaging animations and interactions, demonstrating how motion enhances usability, feedback, and emotional engagement in real interactive experiences.

• 5+ years of experience creating high-quality UI motion design in collaboration with cross-disciplinary teams.

• Expertise with both 2D and 3D motion design tools (such as After Effects, Maya, Cinema4D), with experience working within design systems and interface design tools like Figma to support interactive motion design.

• Exceptional visual design skills in layout, composition, typography, and color theory, with an understanding of motion, timing and accessibility principles.

• Experience presenting and justifying interaction design decisions to diverse audiences, incorporating feedback to refine designs.

• You are comfortable working with varying levels of the organization and collaborating with team leaders across the franchise.

• Understanding of design considerations within mobile environments, including responsiveness, touch interaction, and continuity across visual and interactive states.

Nice to Have:

• Experience implementing motion using industry-standard engines or tools (such as React Native, Rive, Unity, Unreal, or similar) within game, mobile or other digital interactive product environments.

• Understanding of technical constraints, performance considerations, and optimization when designing motion for production environments.

• Experience contributing to motion systems, UI patterns, or interaction guidelines within a product design system.

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Key responsibilities include:

• Effectively communicating upstream and downstream to all levels of the organization to assure common understanding and direction.
• Reviewing and analyzing daily reports to identify safety, quality, delivery gaps, and developing potential countermeasures and/or root cause analysis opportunities striving for continuous improvement.
• Utilizing data analysis and PDCA to lead, support, develop, and justify solutions with related groups/departments for your area of responsibility to solve complex problems.
• Monitoring and managing equipment and processes to ensure optimal manufacturing performance and function while minimizing operating expense.
• Developing capability of self, colleagues, and team through training, mentoring, and sharing of experiences in area of technical expertise and understanding.
• Establishing priorities and making decisions based on data analytics to most effectively accomplish business objectives.
• Managing project implementation, schedule, budget, and resource allocations to ensure successful completion and target achievement.
• Testing, evaluating, and implementing new and innovative technologies to improve overall equipment and process efficiency.
• Developing and managing investment and expense budgets to achieve overall cost targets.

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The ideal candidate will have a strong background in vehicle and system-level validation, with proven experience in instrumentation, data acquisition, global certification, and homologation testing. You will also bring a structured and proactive approach to team leadership, cross-functional coordination, and continuous improvement.

Key Responsibilities:

Team Leadership & Coordination

Manage and mentor a team of V&V Test Engineers, ensuring effective allocation of work, development of team capability, and delivery against program milestones. Act as the central point of coordination for all validation and test activities across commodities and vehicle systems.

DVP Ownership & Test Timing

Define, manage, and maintain the overall Design Verification Plan (DVP), ensuring alignment with program requirements and gateways, cross-disciplinary: Electrical/electronics, controls, software, NVH, structural, durability, dynamics, thermal, fluids, environmental Oversee test scheduling and timing plans, ensuring tests are booked, resources prepared, and vehicles/components delivered on time and to the correct specification. Monitor progress of all test activities, proactively addressing risks, delays, and dependencies.

Verification & Validation Delivery

Oversee the planning, preparation, and execution of system and vehicle-level tests, including global certification and homologation campaigns. Ensure accurate data acquisition and instrumentation setups, data quality, and test coverage against requirements. Review test data, reports, and feedback from engineers to ensure accuracy, consistency, and relevance.

Process Development & Improvement

Drive continuous improvement in V&V processes, methods, and tools, ensuring best practices in requirements-based testing, data handling, and reporting. Standardise templates, workflows, and reporting to improve efficiency and traceability. Champion lessons learned from test campaigns and embed them into future processes.

Communication & Reporting

Provide regular updates to senior management and program leadership on DVP status, test progress, risks, and results. Ensure fast feedback loops, with preliminary findings communicated quickly to design and project teams before full report completion. Act as a key liaison with internal engineering teams, Tier 1 suppliers, and external test facilities.

Global Testing Support

Coordinate international test trips, ensuring correct planning, logistics, and resourcing for engineers and vehicles. Provide senior technical support during test campaigns, including certification and homologation events.

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Responsibilities:

• Lead, coach, and develop a team of CAD designers and engineering design personnel.
• Oversee creation, quality, release, and maintenance of 3D CAD models, assemblies, and 2D engineering drawings.
• Support vehicle and subsystem development from concept, feasibility, packaging, and prototype through validation and production release.
• Ensure CAD deliverables meet engineering standards, release requirements, timing milestones, and program objectives.
• Partner closely with design release engineers, manufacturing, studio, quality, purchasing, suppliers, prototype, and program teams.
• Review model integrity, interface control, package feasibility, tolerance conditions, and manufacturability.
• Drive consistent use of CAD best practices, modeling standards, drawing standards, naming conventions, and data management processes.
• Support digital mockup reviews, issue resolution, packaging studies, and design change implementation.
• Manage team workload, priorities, staffing support, and escalation of technical or timing risks.
• Lead problem-solving activities related to design quality, package conflicts, release issues, and engineering change execution.
• Promote continuous improvement in CAD productivity, digital quality, and development efficiency.
• Mentor team members in technical design methods, GD&T, release discipline, and product development processes.

Qualifications:

• Bachelor's degree in Mechanical Engineering, Automotive Engineering, Manufacturing Engineering, or a related technical discipline.
• 7 or more years of experience in CAD design, engineering design, or product development.
• 2 or more years of leadership experience in a supervisory, lead, or team-coordination capacity.
• Strong experience in automotive or complex mechanical product development.
• Advanced proficiency in 3D CAD modeling, assembly design, engineering drawing development, and release processes.
• Strong working knowledge of GD&T and engineering drawing interpretation.
• Experience supporting cross-functional design reviews, packaging studies, and manufacturability assessments.
• Strong understanding of mechanical systems, component interfaces, materials, and production processes.
• Excellent communication, organizational, problem-solving, and collaboration skills.

Experience with many of the following technical tools and systems is also beneficial:

• CATIA V5
• CATIA 3DEXPERIENCE
• 3D solid modeling
• surface modeling
• large assembly management
• parametric design
• 2D detailing and drawing release
• Teamcenter
• product lifecycle management systems
• engineering release systems
• revision control
• configuration management
• Teamcenter Visualization
• VisMockup
• digital mockup tools
• interference detection
• package analysis
• interface management
• tolerance stack-up tools
• DFMEA support tools
• CAE coordination processes
• design-for-manufacturing reviews
• Microsoft Excel
• Microsoft PowerPoint
• Microsoft Word
• issue tracking systems
• project timing tools
• collaboration platforms

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Your focus will span end-to-end semiconductor workflows, from chip design and verification through tooling and manufacturing-adjacent systems. You will help expand OpenAI's footprint across the stack, shaping how frontier models are applied throughout the semiconductor lifecycle.

You will measure success through production adoption, cycle-time reduction, engineer productivity gains, and evaluation-driven feedback loops that inform product, model, and platform strategy. You'll work closely with Product, Research, GTM, and Partnerships to turn early wins into a durable semiconductor vertical offering.

This role operates in environments where correctness, scale, and trust matter , regressions cost weeks, failures block tape-out, and credibility is earned through technical rigor.

This role is based in San Francisco. We use a hybrid work model of 3 days in the office per week. We offer relocation assistance. Travel up to 50% is required.

In this role you will:

• Design and ship production AI systems around models, owning integrations with RTL repositories, verification environments, simulators, and internal tooling.

• Lead discovery and scoping from pre-engagement through production rollout, translating ambiguous engineering pain points into hypothesis-driven use cases with measurable outcomes.

• Deliver AI-powered verification workflows such as change-aware test selection, directed test generation, and intelligent regression triage, taking them from prototype to daily production use.

• Build systems that operate over large, evolving codebases and artifacts (RTL, tests, logs, waveforms, traces), where performance, latency, and failure handling shape architecture.

• Define and run evaluation loops that measure model and system quality against workflow-specific benchmarks (e.g., coverage, false positives, debug time, iteration speed).

• Own delivery state across multiple workstreams, making trade-offs between scope, speed, and robustness to protect production impact.

• Distill deployment learnings into hardened primitives, reference implementations, playbooks, and tooling that can be reused across customers.

• Surface field insights that inform model behavior, tooling gaps, and future product direction across the semiconductor stack.

You might thrive in this role if you:

• Bring 5+ years of engineering experience in chip design, verification, EDA, or FPGA development (including RTL design, timing closure, and hardware/software co-design), or closely adjacent systems domains such as firmware, distributed systems, compilers, or performance-critical infrastructure.

• Have worked directly with RTL, verification environments, simulators, or large-scale performance/debug tooling , or have partnered closely with teams who do.

• Have delivered complex systems end-to-end in environments where scale, correctness, and long feedback loops shaped how you build and ship.

• Write and review production-grade code in Python and/or systems-adjacent languages, and are comfortable integrating across heterogeneous toolchains.

• Have experience deploying or experimenting with LLM-powered systems and understand how model behavior, evaluation, and guardrails affect trust and adoption.

• Communicate clearly with hardware engineers, software engineers, product teams, and executives, translating technical trade-offs into delivery decisions.

• Apply systems thinking with high execution standards, turning failures, regressions, and unexpected model behavior into improved operating patterns.

• Stay calm and decisive in technically deep, high-stakes environments where progress depends on credibility and follow-through.

Success in this role means shipping AI systems that semiconductor engineers trust in their daily workflows, establishing repeatable deployment patterns across chip design and verification, and helping OpenAI become a long-term partner across the semiconductor ecosystem.

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This position requires a blend of systems engineering expertise, hands-on technical proficiency, and a deep understanding of complex test environments. You will be responsible for defining the architectural roadmap, integrating cutting-edge sensors, data acquisition systems, and telemetry solutions, and ensuring the robust operation of our mission-critical test assets.

Responsibilities

• Architectural Design & Development:
• Lead the architectural design, development, and evolution of comprehensive instrumentation systems and associated range infrastructure for complex test and evaluation systems.
• Define system requirements, specifications, and interface control documents (ICDs) for new and upgraded range capabilities.
• Develop long-term architectural roadmaps, technology insertion plans, and strategic upgrades to maintain state-of-the-art range capabilities.
• Instrumentation Systems Engineering:
• Select, integrate, and validate various instrumentation technologies including, but not limited to: telemetry (RF/Optical), radar, optics (high-speed cameras, IR, EO), GPS/PNT, environmental sensors, and acoustic arrays.
• Design and implement robust data acquisition (DAQ), processing, storage, and analysis pipelines to support real-time and post-test data needs.
• Develop and manage calibration procedures and ensure accuracy and traceability of all instrumentation.
• Range Infrastructure Development:
• Design and oversee the implementation of critical range infrastructure components, such as fiber optic networks, RF distribution systems, power distribution, communication systems, timing and synchronization, and environmental controls for instrumentation shelters.
• Perform RF Survey analysis to ensure noise floor is within desired tolerance ranges for various test sites and environments.
• Ensure network connectivity, cybersecurity, and data security for all instrumentation systems across the range.
• Coordinate with facility engineers and construction teams for physical infrastructure modifications and deployments.
• Test & Operations Support:
• Collaborate closely with test directors, mission planners, range operators, and data analysts to understand requirements and provide technical solutions.
• Provide expert support during testing, anomaly resolution, and post-test data analysis.
• Ensure compliance with all relevant range safety, security, environmental, and regulatory requirements.
• Technical Leadership & Mentorship:
• Provide technical leadership, guidance, and mentorship to junior engineers and cross-functional teams.
• Conduct trade studies, feasibility analyses, and risk assessments for proposed architectural changes and technology investments.
• Prepare detailed technical reports, presentations, and documentation for internal stakeholders and external customers.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Aerospace Engineering, Systems Engineering, Computer Science, or a related technical field.
• 15+ years of progressive experience in instrumentation systems architecture, leadership, or complex range infrastructure development, preferably within the defence or aerospace industry.
• Demonstrated experience in systems architecture development for complex real-time systems.
• Strong understanding of data acquisition (DAQ) principles, telemetry systems (e.g., IRIG 106), RF systems, and various sensor technologies.
• Proficiency with system modeling tools (e.g., SysML, MATLAB/Simulink), CAD software, and/or programming languages (e.g., Python, C++).
• Extensive experience in the design, development, integration, operation, and maintenance of test range infrastructure and instrumentation supporting high-speed weapons systems and Unmanned Aerial Vehicles (UAVs)/drones.
• Experience with network design, distributed systems, and real-time data processing.
• Excellent written and verbal communication skills, with the ability to articulate complex technical concepts to diverse audiences.
• Ability to work independently, manage multiple priorities, and lead technical efforts within a team environment.
• Ability to travel as required to multiple test locations CONUS and OCONUS.
• Must be able to obtain and maintain a U.S. Security Clearance (Secret or Top Secret preferred).

Preferred Qualifications

• Master's or Ph.D. in a relevant engineering discipline.
• Experience with specific missile test range instrumentation, such as high-speed video systems, precision timing systems, advanced radar tracking, or target scoring systems.
• Knowledge of cybersecurity best practices and implementation for critical infrastructure and classified systems.
• Familiarity with industry standards (e.g., IRIG, MIL-STD-1553, ARINC 429).
• Project management experience (PMP certification a plus).
• Hands-on experience with hardware design, prototyping, and testing.

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We are seeking an experienced Stablecoins Product Manager to define, build, and scale institutional stablecoin products powering cross-border settlement, and USD liquidity for regulated financial institutions. This role owns the end-to-end product strategy for stablecoin institutional use cases.

Role Responsibilities:

• Define and own the product vision and roadmap for Anchorage Digital’s stablecoin solutions platform, and translate institutional client needs across banks, PSPs, and clearing networks into scalable and repeatable product capabilities.
• Partner with engineering to deliver secure, resilient, and compliant stablecoin products, settlement flow, and fiat to stablecoin conversion, and liquidity management.
• Collaborate closely with compliance, legal, risk, and banking teams to embed regulatory requirements directly into product design.
• Incorporate client feedback, regional market insights, and regulatory developments into actionable product decisions.

Technical Skills:

• Proven ownership of financial products for banks and regulated institutions.
• Deep understanding of API design (webhooks, idempotency, etc) and payment rails (ACH, RTP, Fedwire) for high-value payment and settlement systems.
• Experience guiding API and data model design in partnership with engineering, with a focus on security, resiliency, and auditability.
• Ability to set technical standards for authentication, permissions, rate limits, versioning, and backward compatibility.
• Proficiency in SQL or scripting languages (Python, Node, etc) to automate workflows or perform data analysis.
• Strong understanding of fiat rails (ACH, wires, RTP/SEPA), FX and on/off-ramps, reconciliation, settlement timing, and how fiat conversions interact with stablecoins and treasury flows.

Qualifications:

• 8+ years of product management experience, with a strong focus on banking, financial products, payments, FX, or capital markets.
• Demonstrated experience owning complex, regulated financial products from concept through production.
• Deep understanding of stablecoins, institutional payments, FX, and treasury workflows.
• Strong analytical and systems-level thinking, with the ability to balance regulatory, technical, and commercial constraints.
• Strong familiarity with U.S. clearing systems, payments networks and messaging systems - guidelines, restrictions, membership requirements, permissible use cases, future roadmap.
• Proven ability to influence cross-functional stakeholders without direct authority.

Preferred Experience:

• Experience working with banks, payment service providers, or clearing and settlement networks.
• Exposure to blockchain-based settlement, digital assets, or tokenized money.
• Exposure or interest in AI-driven product development and tools.
• Familiarity with regulatory frameworks impacting stablecoins across the U.S. and international markets.
• Experience partnering closely with sales or coverage teams while maintaining clear product ownership.

Additional Information About Anchorage Digital:

Anchorage Digital is committed to being a welcoming and inclusive workplace for everyone, and we are intentional about making sure people feel respected, supported, and connected at work,regardless of who you are or where you come from. We value and celebrate our differences and we believe being open about who we are allows us to do the best work of our lives.

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

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Your key responsibilities will include driving product adoption through competitive benchmarking, customer evaluations, and articulating product advantages to design teams and management. You will also deliver customer training, technical presentations, and hands-on workshops to maximize user proficiency and satisfaction.

In addition, you will provide tape-out support, troubleshoot complex timing issues, and ensure successful project completion. You will collaborate with R&D, marketing, and sales to relay customer feedback and influence product enhancements.

To succeed in this role, you will need expertise in Synopsys PrimeTime STA tool, with hands-on experience and deep knowledge of its features. You will also require strong understanding of timing corners, process variations, and signal integrity-related issues.

If you are a collaborative team player who values diverse perspectives and fosters inclusive environments, we encourage you to apply.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.

You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.

You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks. Performing digital design validation and functional verification at both block and SoC levels. Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs. Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing. Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance. Utilizing and scripting in languages such as Tcl to automate design and verification workflows. Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides.

Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies. Shape the evolution of embedded memory test and SLM architectures that power next-generation devices. Drive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products. Enhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support. Contribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks. Mentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth. Influence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization. Support strategic decision-making by providing technical insights and market-driven recommendations.

2-4 years of relevant experience in ASIC digital design and verification. Proficiency in RTL simulation, logic synthesis, and timing verification tools. Strong understanding of DFT architectures. Familiarity with debug tools such as Verdi and workflows for performance analysis. Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl. Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.

Analytical thinker with exceptional problem-solving skills. Effective communicator, able to collaborate across disciplines and with external partners. Proactive, self-motivated, and adaptable in fast-paced environments. Committed to quality, detail, and continuous learning. Team player who values diversity, inclusion, and mentorship. Customer-focused, dedicated to delivering timely and effective solutions.

You'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Responsibilities:

• Collaborate with R&D architects and customers on hardware-assisted verification products.

• Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.

• Define test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.

• Become an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.

• Leverage your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.

• Adapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.

• Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.

The Impact You Will Have:

• Enhance Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.

• Improve the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.

• Provide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.

• Ensure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.

• Support the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.

• Facilitate the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.

What You’ll Need:

• BSEE/MS with 7+ years of related experience.

• Expertise in Emulation and/or Prototyping flows, systems, and methodologies.

• Strong proficiency in Verilog, System Verilog, and VHDL.

• Understanding of verification concepts and experience with functional simulators.

• Experience with scripting languages.

• Knowledge in Simulation flows, Assertion, DPI, and Transactors.

• Complex problem-solving and debugging skills.

• Strong communication skills and the ability to interact with customers and peers.

• Knowledge in synthesis and timing analysis concepts (preferred).

• Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).

• Experience with Xilinx & Altera architecture and toolchains (preferred).

• Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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big_They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a Staff Engineer in our Analog Design team, you will be responsible for designing and developing full custom analog circuit macros for high-speed SERDES PHY IP.

Your responsibilities will include designing and developing full custom analog circuit macros for high-speed SERDES PHY IP, including transceivers, voltage/current-mode drivers, PLLs, DLLs, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, and clock data recovery circuits.

You will also collaborate with cross-functional teams locally and globally to refine circuit implementations and achieve optimal power, area, and performance targets.

In addition, you will ensure analog sub-block performance adheres to SerDes standards and architecture specification documents.

You will lead verification strategies using advanced simulator features to guarantee the highest quality design outcomes.

You will oversee physical layout processes to minimize parasitic effects, device stress, and process variations.

You will present simulation data for peer and customer reviews, and document design features and test plans.

You will consult on electrical characterization and support the integration of your circuit within the SerDes IP product.

You will handcraft high-performance clock and data paths using digital/CMOS logic cells and verify timing margins with SPICE and STA tools.

You will address ESD and latch-up design verification, crosstalk coupling impacts, and ensure robust mixed-signal analog design.

The impact you will have includes accelerating development of high-performance silicon chips critical to emerging technologies like AI, IoT, and 5G.

You will optimize chip designs for power, cost, and performance, helping customers reduce project schedules by months.

You will advance Synopsys' leadership in high-speed interface IP and mixed-signal design innovation.

You will contribute to the creation of next-generation processes and models for manufacturing advanced chips.

You will support global collaboration, knowledge sharing, and technical excellence across teams and sites.

You will enhance customer satisfaction by delivering reliable, scalable, and high-quality analog IP solutions.

You will drive technical best practices and mentor junior engineers, strengthening the team's capabilities.

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As a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.

Key responsibilities include:

Creating and debugging test benches and test cases Running RTL and gate-level simulations Supporting application engineers and customers on HBM/DDR PHY topics Contributing to technical documentation Driving product improvements based on customer feedback

The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

ASIC RTL design and verification experience Verilog, PERL, TCL, Python skills Static timing analysis and synthesis knowledge Simulation and debugging abilities HBM/DDR protocol experience is an asset

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.

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You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.

What You'll Be Doing:

• Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM and Test solutions into customers' projects.
• Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys' Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
• Driving the adoption of Synopsys' SLM and DFT solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You'll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.

• 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.

• Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.

• Knowledge on memory defectivities soft errors and reliability.

• Familiarity with error correcting codes such as Hamming and Hsiao.

• Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.

• Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.

• Debugging abilities to identify and resolve issues in functional verification in UVM environment.

• Hands on experience in flow automation.

• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).

• Knowledge of Lint, CDC, RDC is a plus.

• Knowledge of physical implementation is not a must, but good to have.

• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.

• Customer facing experience is a plus – educating/guiding customer on technical details of a solution.

• Good to have:

• Hands-on bring-up and debug experience of silicon is a plus.

• Architecture/micro-architecture experience.

• Understanding of GenAI and Agentic AI workflows.

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You are a seasoned R&D Engineer with over 4 years of experience, specializing in the development of complex software projects. Your expertise in C/C++ coding and a solid understanding of data structures and algorithms are second to none. You are passionate about learning and exploring new technologies, which drives your innovative approach to problem-solving. Your ability to resolve issues creatively and autonomously select methods and techniques to achieve solutions sets you apart. You thrive on working from project inception to completion and enjoy contributing to complex aspects of a project. Your ability to mentor junior peers and network with internal and external personnel on assigned tasks showcases your leadership and communication skills.

As a Staff R&D SW Engineer - Power Analysis, you will be responsible for designing, developing, and troubleshooting software programs as part of the Platform Power team for Fusion Compiler/ICC2. You will lead the development of complex software projects with a focus on C/C++ coding, applying your knowledge of data structures and algorithms to solve intricate problems, and exploring and integrating new technologies to enhance software performance and functionality.

The impact you will have is enhancing the efficiency and effectiveness of software programs within the Platform Power team, driving innovation through the application of cutting-edge technologies, contributing to the successful completion of complex projects that push the boundaries of technological advancements, fostering a collaborative environment by networking with internal and external personnel, elevating the team's capabilities by mentoring junior engineers, and ensuring the delivery of high-quality software solutions that meet and exceed organizational goals.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Responsibilities:

Define and develop ASIC RTL design and verification at both chip level and block level. Collaborate with cross-functional teams to design, implement, and verify PCIe interfaces. Perform RTL coding, synthesis, and simulation to ensure design functionality and performance. Conduct design reviews and provide technical guidance to junior engineers. Work closely with physical design teams to ensure seamless integration and optimization. Debug and resolve design issues to ensure timely delivery of high-quality products.

Impact:

Contribute to the development of high-performance silicon chips that power next-generation technologies. Enhance the functionality and performance of Synopsys' PCIe solutions. Drive innovation and improve design methodologies within the team. Ensure the successful delivery of complex ASIC projects on time and within budget. Mentor and guide junior engineers, fostering a culture of continuous learning and development. Collaborate with cross-functional teams to deliver integrated and optimized solutions for our customers.

Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Extensive experience in ASIC digital design and verification. Strong knowledge of PCIe protocols and interfaces. Proficiency in RTL coding (Verilog/SystemVerilog) and simulation tools. Experience with synthesis, timing analysis, and formal verification.

Team:

Join a dynamic and collaborative team of engineers dedicated to designing and delivering high-performance silicon solutions. Our team focuses on innovation, quality, and continuous improvement, working together to solve complex technical challenges and deliver industry-leading products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Designing and analysing algorithms for end-to-end timing constraint management across the Synopsys flow.
• Driving the success and evolution of Synopsys' constraint flow and tools, enhancing product performance and integration.
• Collaborating within a highly skilled engineering team to deliver innovative solutions for static timing analysis (STA) during design and optimisation.
• Designing, developing, troubleshooting, and debugging advanced software programs for constraint generation and verification.
• Architecting, developing, and testing constraint management solutions, contributing to the advancement of R&D software development.

As a member of our team, you will have the opportunity to work on cutting-edge projects, collaborate with talented engineers, and contribute to the development of innovative solutions. You will also have access to professional development opportunities, competitive compensation, and a comprehensive benefits package.

To be successful in this role, you will need to have a strong foundation in programming fundamentals, including data structures, sorting, searching algorithms, and numerical methods. You should also have experience with C/C++, scripting languages, and a keen eye for detail. Additionally, you should be able to communicate effectively with cross-functional teams and have a strong understanding of software development principles and practices.

If you are a motivated and experienced engineer looking for a challenging and rewarding opportunity, please apply today!

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.

You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.

You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.

You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.

You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.

You will mentor junior engineers and contribute to team knowledge sharing initiatives.

Impact

You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.

You will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.

You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.

You will facilitate seamless cross-site collaboration, ensuring global project success.

You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.

You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.

3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).

Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.

Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.

Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.

Strong analytical and debugging skills for addressing complex design challenges.

Team

You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.

The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.

Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include designing and analysing algorithms for end-to-end timing constraint management, driving the success and evolution of Synopsys' constraint flow and tools, collaborating within a highly skilled engineering team to deliver innovative solutions for static timing analysis (STA) during design and optimisation, and designing, developing, troubleshooting, and debugging advanced software programs for constraint generation and verification.

The ideal candidate will have a B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute, 8 years of experience with strong foundational knowledge of programming fundamentals, including data structures, sorting, searching algorithms, and numerical methods, ability to read and analyse code in C/C++, exceptional debugging skills and proficiency in scripting languages (such as Python, Perl, or TCL), demonstrated analytical and problem-solving skills, with a keen attention to detail, independent judgment in selecting methods and techniques to obtain technical solutions, experience with Synopsys Static Timing Analysis (STA) tools and EDA tool/CAD flow development (preferred), and experience with Synopsys Design Constraints (SDC) is a strong plus.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. The total rewards include both monetary and non-monetary offerings.

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Key responsibilities include:

• Strong problem-solving skills and the ability to debug complex software issues in large-scale systems.
• 2–5 years of industry experience in software development or EDA-related R&D roles.
• Ability to contribute independently to feature development, bug fixes, and performance improvements.
• Good communication skills and the ability to collaborate effectively within a cross-functional team.

Ideal candidates will have proficiency in C/C++ development, with strong fundamentals in data structures and algorithms. Experience working on Linux platforms and familiarity with build systems, debugging tools, and development workflows on Linux is a plus. Exposure to scripting languages such as Tcl, Perl, or Python will be an added advantage.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

Get an idea of what your daily routine around the office can be like

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15411

Remote Eligible

No

Date Posted

02/23/2026

Alternate Job Titles:

• Staff Applications Engineer, Digital Implementation

• Staff AE – RTL-to-GDS Solutions

• Senior Digital Design Flow Engineer

• Customer Success Engineer – Physical Design

• Staff Field Applications Engineer – EDA

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.

You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.

You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.

What You’ll Be Doing:

• Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.

• Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.

• Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.

• Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.

• Collaborate with global Applications Engineering, R&D, and Product Management teams to enhance methodologies and influence tool development.

• Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.

• Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.

The Impact You Will Have:

• Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.

• Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.

• Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.

• Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.

• Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.

• Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.

• Champion best practices and knowledge sharing within the Applications Engineering community.

What You’ll Need:

• Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).

• Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.

• Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.

• Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.

• Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.

Who You Are:

• Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.

• Exceptional communicator, comfortable engaging with both internal teams and external partners.

• Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.

• Collaborative team player, eager to share knowledge and learn from others.

• Customer-focused, energetic, and adaptable to fast-paced, evolving environments.

The Team You’ll Be A Part Of:

You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15391

Remote Eligible

No

Date Posted

02/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.

• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.

• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.

• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.

• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.

• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.

• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

• Proven expertise with FinFET technologies and CMOS tape-outs.

• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

• Excellent communication and documentation skills.

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.

• Detail-oriented and thorough, with a commitment to delivering high-quality results.

• Analytical thinker with strong problem-solving abilities and a proactive approach.

• Excellent communicator, able to convey complex technical concepts clearly.

• Adaptable and resilient in fast-paced, dynamic environments.

• Committed to fostering an inclusive, innovative, and supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and patern

XML job scraping automation by YubHub

Job Description

We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.

Responsibilities

• Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.
• Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.
• Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.
• Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power & IR drop signoff to debug and resolve critical implementation bottlenecks.
• Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.
• Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock & reset architecture improvements for enabling high speed timing closure, PPA improvements.

Requirements

• MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
• Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
• Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
• Must have experience in leading and managing local, remote implementation teams.
• Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
• Strong scripting and software skills.

What You'll Need

• Inclusive leader and effective communicator.
• Innovative, collaborative, and quality-driven.
• Thrives in dynamic environments.

The Team You'll Be A Part Of

Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

What You'll Be Doing

• Deliver signoff-quality, high-performance silicon solutions.
• Mentor and develop engineering teams.
• Drive process improvements and technical innovation.
• Enhance Synopsys’ leadership in high-speed IP.
• Facilitate successful cross-team collaboration.
• Enable next-generation chip architectures.

The Impact You Will Have

• Deliver signoff-quality, high-performance silicon solutions.
• Mentor and develop engineering teams.
• Drive process improvements and technical innovation.
• Enhance Synopsys’ leadership in high-speed IP.
• Facilitate successful cross-team collaboration.
• Enable next-generation chip architectures.

What You’ll Need

• MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
• Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
• Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
• Must have experience in leading and managing local, remote implementation teams.
• Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
• Strong scripting and software skills.

Who You Are

• Inclusive leader and effective communicator.
• Innovative, collaborative, and quality-driven.
• Thrives in dynamic environments.

The Team You’ll Be A Part Of

Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

XML job scraping automation by YubHub

You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.

What You’ll Be Doing:

• Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.
• Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.
• Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.
• Collaborating with R&D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.
• Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.

The Impact You Will Have:

• Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.
• Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.
• Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.
• Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.
• Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.
• Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design

What You’ll Need:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.
• Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.
• 7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.
• Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).
• Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.
• Experience in Unix/Linux development environments.

Who You Are:

• Collaborative team player with excellent communication skills and a global mindset.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.
• Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.
• Adaptable and eager to stay updated with the latest industry trends and technologies.
• Customer-focused, with a dedication to supporting and enabling client success.

The Team You’ll Be A Part Of:

You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What You'll Be Doing:

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
• Perform STA (Static Timing Analysis) using industry-standard EDA tools.
• Support constraint development and validation for timing sign-off.
• Collaborate with design, verification, and physical implementation teams to resolve timing issues.
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)

Authority:

• Normally receives detailed instructions on all work.
• Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.
• Applies company policies and procedures to resolve routine issues.

What You'll Need:

• Bachelor's or Master's degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.
• 1-2 year working experience in similar roles or fresh graduates

(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position's requirements.)

• Basic understanding of timing analysis, SPICE simulation, and STA concepts.
• Experience with scripting languages such as Python and TCL for automation and data processing.
• Familiarity with EDA tools for timing characterization and verification.
• Strong problem-solving abilities and keen attention to detail.
• Good verbal and written English communication skills.
• Highly responsible and self-motivated, with a strong sense of ownership over your work.
• Collaborative team player, open to feedback and eager to learn from others.
• Detail-oriented and methodical, always striving for accuracy and quality.
• Effective communicator, able to articulate technical concepts clearly.
• Adaptable and resilient in the face of new challenges or shifting priorities.
• Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.

The Team You’ll Be A Part Of:

You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.

As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.

About the Role

We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.

You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.

In this role, you will:

• Develop, build and own tools, flows and methodologies for physical implementation
• Own physical implementation of floorplan blocks from floorplanning to final signoff
• Collaborate with RTL designers to drive optimal block implementation solutions
• Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

Qualifications:

• BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
• Demonstrated success in taping out complex silicon designs
• Hands-on experience with block physical implementation and PPA convergence
• Strong coding experience with python, bazel, TCL
• Strong experience building physical design tools, flows and methodologies
• Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
• Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Bonus:

• Experience with AI or HPC-focused chips
• Experience with optimizing PPA for high performance compute cores
• Hands-on experience with top-level design methodologies

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What We Offer

• An organization where 100% of time is dedicated as groups see fit
• The opportunity to collaborate with experts across a range of disciplines
• A work environment and flexible schedule in support of families and domestic partnerships
• A culture eager to become stronger through diversity of all forms
• Exceptional health insurance coverage
• Unrivaled employer match for our 401(k) retirement plan
• Generous vacation and family leave
• On-site amenities in support of health and efficiency
• Fertility and adoption assistance
• Reimbursement for child care during interviews

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Bachelor's and/or masters with a minimum 10+yrs of Industry experience or equivalent
• At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB

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What you'll do

• Providing world-class support to customers and channel partners, ensuring effective usage and satisfaction with Apache BU simulation products focused on Power, Power Integrity, and Reliability.
• Applying advanced knowledge in custom circuit analysis, RTL design, high-performance VLSI design, standard cell physical layout, power-grid extraction, timing analysis, noise analysis, and voltage drop effects to solve complex SoC challenges.

What you need

• Bachelor’s degree in Electrical Engineering (BSEE) with at least 6 years of experience, Master’s degree (MSEE) with 4 years, or PhD with 2 years in VLSI design.
• Expertise in custom circuit analysis, standard cell physical layout, timing and noise analysis, and voltage drop effects using CAD tools.
• Strong technical knowledge of EDA tools for layout, STA, Extraction (SPEF/DSPF), and Spice simulation.

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What you'll do

• Develop and implement high-performance PCIe-based designs on FPGA platforms, ensuring optimal functionality and efficiency.
• Collaborate closely with cross-functional teams to gather requirements, evaluate design tradeoffs, and deliver robust FPGA solutions that satisfy project goals.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in FPGA design and development.
• Proficiency in HDL languages such as Verilog.
• Strong expertise with industry-standard FPGA development tools like Vivado.
• In-depth understanding of digital design principles, including clock domains and timing analysis.
• Experience with high-speed interfaces (PCIe or Ethernet).
• Excellent analytical, debug, and problem-solving skills.
• Ability to collaborate effectively in a multi-disciplinary, team-based environment.
• Strong verbal and written communication skills.

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What you'll do

• Reviewing and analyzing customer and partner feedback to enhance product and solution performance.
• Collaborating with R&D to shape technical roadmaps, specifications, and validation processes for product improvements.
• Diagnosing, troubleshooting, and resolving complex technical issues on-site and remotely for customer installations.

What you need

• BS or MS in Electrical or Computer Engineering.
• 6-8 years of relevant experience in the semiconductor industry.
• Hands-on expertise with Place & Route (P&R), extraction, Static Timing Analysis (STA), and Engineering Change Order (ECO) tools.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Providing expert support and training to customers on PrimeTime, PrimeClosure, and PrimeShield, ensuring optimal use and maximum productivity.
• Independently coordinating and supporting multiple customer designs through tape-out, verifying designs meet or exceed customer expectations.

What you need

• Bachelor’s degree in Electrical Engineering with a minimum of 12 years of experience, or a Master’s degree with at least 8 years of experience.
• In-depth understanding of timing, power, statistical and electromigration characterization, and signal integrity in advanced SoC design.

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What you'll do

• Providing expert-level support for PrimeTime, Synopsys’ industry-leading Static Timing Analysis (STA) tool, to both prospective and existing customers.
• Leading competitive product benchmarks and technical evaluations, demonstrating PrimeTime’s advantages to customer design teams and management.
• Delivering customer training sessions and workshops, enabling teams to maximize their productivity and achieve successful tape-outs.

What you need

• Bachelor’s degree in Electrical Engineering or equivalent with 5-7 years of relevant experience, or Master’s degree (MSEE or equivalent) with 4-6 years of experience.
• Hands-on experience and in-depth knowledge of Synopsys PrimeTime or similar STA tools.

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What you'll do

• Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.
• Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.
• Providing technical guidance and mentorship.
• Continuously improving design methodologies and processes to enhance efficiency and quality.

What you need

• BE or MSEE with 10+ years of direct physical design experience.
• Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.
• Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.

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What you'll do

• Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.
• Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.
• Providing technical guidance and mentorship to junior engineers.

What you need

• BE or MSEE with 2+ years of direct physical design experience.
• Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.
• Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.

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What you'll do

• Drive global customer adoption of Synopsys Implementation products by providing expert technical guidance and support throughout the RTL-to-GDS flow.
• Diagnose and resolve synthesis and place-and-route challenges, leveraging in-depth knowledge of customer designs and Synopsys tools.

What you need

• Expertise in implementation methodologies, with deep hands-on experience in Synopsys Fusion Compiler.
• Thorough understanding of RTL-to-GDS flows and methodologies, including synthesis, place & route, and timing analysis.

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What you'll do

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.

What you need

• BS/MS in Electronics, Electromechanics, or Telecommunications.
• 5-8 years in analog/mixed signal or custom logic design.

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What you'll do

• Drive global customer adoption of Synopsys Implementation products by providing expert technical guidance and support throughout the RTL-to-GDS flow.
• Diagnose and resolve synthesis and place-and-route challenges, leveraging in-depth knowledge of customer designs and Synopsys tools.

What you need

• Expertise in implementation methodologies, with deep hands-on experience in Synopsys Fusion Compiler.
• Thorough understanding of RTL-to-GDS flows and methodologies, including synthesis, place & route, and timing analysis.

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What you'll do

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.
• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 9+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes (like 2nm/3nm/5nm etc).
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.
• Outstanding verbal and written communication, presentation, and customer interaction skills.

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What you'll do

• Apply engineering expertise to support EDA product specifications and deployment for leading semiconductor design houses and foundries.
• Engage directly with global customers, IP providers, and foundries to understand and address design challenges for cutting-edge SoCs and 3DICs.

What you need

• At least 5+ years of experience in the semiconductor domain, with a strong background in STA analysis, ECO, timing closure, or PDN at block or SoC level.
• Proficiency in providing technical support for PDN and/or Timing Signoff domains, with proven ability to assist clients and resolve issues.

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What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

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What you'll do

Intro.

• Performs development activities, including the design, implementation, maintenance, testing and documentation of software modules and sub-systems
• Learns and employs best practices
• Performs bug verification, release testing and beta support for assigned products
• Researches problems discovered by QA or product support and develops solutions

What you need

• BS in Electrical Engineering, or related field with 5 years’ experience
• Experience with EDA solution, EDA companies, semiconductor design companies, semiconductor foundries

Why this matters

One paragraph about career impact and value.

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What you'll do

Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.

Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.

Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.

Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.

Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.

Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.

Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.

What you need

MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).

Proven expertise with FinFET technologies and CMOS tape-outs.

Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.

Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).

Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.

Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).

Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.

Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.

Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).

Excellent communication and documentation skills.

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What you'll do

You are an accomplished analog and mixed-signal design engineer, passionate about pushing the boundaries of high-speed interface technology. With a strong foundation in Electrical, Electronics, or VLSI Engineering, you have hands-on expertise in custom analog circuit design, particularly in the nanometer CMOS domain.

• Designing and developing high-speed analog and mixed-signal (AMS) circuit macros, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, CDR circuits, and injection-locked loops for High-Speed PHY IP in planar and FinFET CMOS technologies.

What you need

• Bachelor’s degree (BE) plus 3+ years or Master’s degree (MTech) plus 2+ years of relevant experience in mixed-signal analog/custom circuit design, preferably in Electrical/Electronics/VLSI Engineering.

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What you'll do

As a Performance Engineer, you will work alongside our support team and the engineering groups in Cologne to deliver comprehensive performance analysis of drivers, teams, and cars using car data, timing data, and simulation tools across various categories, championships, events, and circuits.

• Work alongside our support team and the engineering groups in Cologne to deliver comprehensive performance analysis of drivers, teams, and cars using car data, timing data, and simulation tools across various categories, championships, events, and circuits
• Liaise with our customer teams to understand the limiting factors for performance against competition.

What you need

• A Bachelor’s or Master’s degree in Mechanical Engineering, Automotive Engineering, or a related discipline
• Several years of experience in a similar role or as a race team performance engineer in GT3
• Strong communication skills with the ability to confidently and knowledgeably engage as a customer-facing representative of the company

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What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

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