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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_44645300-ced"},"title":"Hardware Engineering, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a global leader in semiconductor design and verification solutions, we enable the world&#39;s most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.</p>\n<p>You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.</p>\n<p>You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&amp;D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you&#39;ll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_44645300-ced","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/hardware-engineering-sr-engineer/44408/93159885392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL simulation","logic synthesis","timing verification tools","DFT architectures","debug tools","SystemVerilog","UVM","Verilog","C/C++","Python","Tcl","EDA tools","VC Auto-Testbench","protocol compliance checking"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:43.007Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL simulation, logic synthesis, timing verification tools, DFT architectures, debug tools, SystemVerilog, UVM, Verilog, C/C++, Python, Tcl, EDA tools, VC Auto-Testbench, protocol compliance checking"}]}