Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

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Growth - Emails, Notifications and Lifecycle

Location

New York City

Employment Type

Full time

Location Type

Hybrid

Department

-

Compensation

• $239K – $265K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About The Team

The Growth team drives user and revenue growth across ChatGPT’s consumer and business segments worldwide. We operate across the full funnel - from awareness and acquisition through activation, retention, and expansion - using a combination of surface optimizations, in-product funnel improvements, actionable insights, disciplined experimentation, global performance marketing, and AI-powered workflows.

About The Role

We are seeking a full-funnel ‘growth athlete’ with deep expertise in email, notifications, and lifecycle growth initiatives. You will design and scale this motion and associated campaigns across ChatGPT user journeys with rigorous analytical thinking and high-velocity experimentation. This team thrives on rapid testing, precise measurement, and creative problem solving, always keeping user value at the center of our decision-making.

You will own email/notification/lifecycle growth programs end-to-end—from strategy and creative development to deployment, measurement, and iteration. This role is highly cross-functional and will require close collaboration with engineering, product, data science, and design teams to drive engagement, retention, and monetization through these growth levers.

This role is based in San Francisco, CA or New York, NY. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Design, launch, and optimize global lifecycle tests and programs (email, push notifications, in-app messaging) to drive activation, engagement, and retention across B2C and B2B segments.

• Own end-to-end messaging strategy, including audience segmentation, personalized journeys, channel selection, and timing to maximize conversion and long-term value.

• Develop testing roadmaps for lifecycle campaigns, running A/B and multivariate experiments to improve open rates, click-through rates, and downstream metrics such as paid conversion, DAU/WAU impact, and LTV.

• Partner with product and engineering to enhance messaging infrastructure (event triggers, experimentation tools, data pipelines) and enable sophisticated targeting and automation.

• Build and maintain funnel performance dashboards to surface opportunities and guide prioritization.

• Collaborate with creative and design teams to craft compelling copy and visuals that reinforce ChatGPT’s brand and value proposition while driving measurable outcomes.

• Leverage AI-powered workflows to personalize communications at scale, using predictive models to optimize content, timing, and delivery.

• Partner with data science to develop attribution models and measure the incremental impact of these growth levers. Share these learnings with the broader organization.

You might thrive in this role if you are/have:

• 8+ years of growth experience spanning both consumer (B2C) and business (B2B) products, with a track record of scaling email, push, and in-app messaging platforms and growth initiatives driving activation, engagement, and paid conversion.

• Deep expertise in audience segmentation, targeting, and multi-channel orchestration (email, push, in-app, SMS) across self-serve consumer funnels and multi-stakeholder B2B purchase journeys.

• Hands-on experience with automation, email, and messaging platforms (e.g., SendGrid, Braze, Iterable, Customer.io, Marketo) and comfort working with APIs, event triggers, and CRM data.

• Proven ability to design and interpret experimentation and measurement frameworks—A/B tests, multivariate testing, and incrementality studies—to optimize lifecycle touchpoints across different customer types.

• Strong analytical skills with the ability to model consumer funnels and lead-to-customer pipelines, leveraging data to identify growth opportunities and measure impact.

• Demonstrated success collaborating with cross-functional teams to drive business outcomes and growth.

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What you'll do

• Designing, developing, debugging, and optimizing large-scale software programs, increasingly leveraging AI-assisted coding workflows.
• Developing core algorithms for global placement, detailed placement, global routing, detailed routing, and timing optimization.
• Improving product usability, robustness, and user experience, ensuring high-quality engineering workflows.
• Engineering runtime-efficient software to accelerate the overall digital implementation (DI) flow.
• Designing algorithms and data structures optimized for runtime performance and memory footprint.
• Collaborating closely with cross-functional teams to ensure seamless integration of new capabilities across Fusion Compiler.

What you need

• A degree in Electrical Engineering or Computer Science.
• Proficiency in C/C++ programming.
• Experience with place-and-route tool development (a plus).
• Strong background in data structures and algorithms.
• Experience in EDA tool development.

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What you'll do

You will be responsible for independently owning and driving full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.

What you need

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.

• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).

• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.

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