You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.

What You'll Be Doing:

• Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM and Test solutions into customers' projects.
• Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys' Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
• Driving the adoption of Synopsys' SLM and DFT solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You'll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.

• 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.

• Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.

• Knowledge on memory defectivities soft errors and reliability.

• Familiarity with error correcting codes such as Hamming and Hsiao.

• Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.

• Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.

• Debugging abilities to identify and resolve issues in functional verification in UVM environment.

• Hands on experience in flow automation.

• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).

• Knowledge of Lint, CDC, RDC is a plus.

• Knowledge of physical implementation is not a must, but good to have.

• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.

• Customer facing experience is a plus – educating/guiding customer on technical details of a solution.

• Good to have:

• Hands-on bring-up and debug experience of silicon is a plus.

• Architecture/micro-architecture experience.

• Understanding of GenAI and Agentic AI workflows.

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Job Description

We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.

Responsibilities

• Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.
• Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.
• Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.
• Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power & IR drop signoff to debug and resolve critical implementation bottlenecks.
• Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.
• Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock & reset architecture improvements for enabling high speed timing closure, PPA improvements.

Requirements

• MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
• Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
• Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
• Must have experience in leading and managing local, remote implementation teams.
• Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
• Strong scripting and software skills.

What You'll Need

• Inclusive leader and effective communicator.
• Innovative, collaborative, and quality-driven.
• Thrives in dynamic environments.

The Team You'll Be A Part Of

Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

What You'll Be Doing

• Deliver signoff-quality, high-performance silicon solutions.
• Mentor and develop engineering teams.
• Drive process improvements and technical innovation.
• Enhance Synopsys’ leadership in high-speed IP.
• Facilitate successful cross-team collaboration.
• Enable next-generation chip architectures.

The Impact You Will Have

• Deliver signoff-quality, high-performance silicon solutions.
• Mentor and develop engineering teams.
• Drive process improvements and technical innovation.
• Enhance Synopsys’ leadership in high-speed IP.
• Facilitate successful cross-team collaboration.
• Enable next-generation chip architectures.

What You’ll Need

• MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
• Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
• Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
• Must have experience in leading and managing local, remote implementation teams.
• Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
• Strong scripting and software skills.

Who You Are

• Inclusive leader and effective communicator.
• Innovative, collaborative, and quality-driven.
• Thrives in dynamic environments.

The Team You’ll Be A Part Of

Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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