{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/timing-constraints"},"x-facet":{"type":"skill","slug":"timing-constraints","display":"Timing Constraints","count":2},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_606388e5-d2c"},"title":"Solutions Engineering, Sr Staff Engineer (DFT, RTL Design product Engineer)","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Working closely with a world-class R&amp;D team, you&#39;ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.</li>\n<li>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</li>\n<li>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</li>\n<li>Driving the deployment and smooth execution of SLM and Test solutions into customers&#39; projects.</li>\n<li>Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enhancing Synopsys&#39; Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.</li>\n<li>Driving the adoption of Synopsys&#39; SLM and DFT solutions at premier customer base worldwide.</li>\n<li>Influencing the development of next-generation SLM IPs and solutions.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li><p>BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.</p>\n</li>\n<li><p>8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.</p>\n</li>\n<li><p>Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.</p>\n</li>\n<li><p>Knowledge on memory defectivities soft errors and reliability.</p>\n</li>\n<li><p>Familiarity with error correcting codes such as Hamming and Hsiao.</p>\n</li>\n<li><p>Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.</p>\n</li>\n<li><p>Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.</p>\n</li>\n<li><p>Debugging abilities to identify and resolve issues in functional verification in UVM environment.</p>\n</li>\n<li><p>Hands on experience in flow automation.</p>\n</li>\n<li><p>Knowledge of Synthesis is a must with understanding of timing constraints (SDC).</p>\n</li>\n<li><p>Knowledge of Lint, CDC, RDC is a plus.</p>\n</li>\n<li><p>Knowledge of physical implementation is not a must, but good to have.</p>\n</li>\n<li><p>Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&amp;D) to make decisions.</p>\n</li>\n<li><p>Customer facing experience is a plus – educating/guiding customer on technical details of a solution.</p>\n</li>\n<li><p>Good to have:</p>\n</li>\n<li><p>Hands-on bring-up and debug experience of silicon is a plus.</p>\n</li>\n<li><p>Architecture/micro-architecture experience.</p>\n</li>\n<li><p>Understanding of GenAI and Agentic AI workflows.</p>\n</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_606388e5-d2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/solutions-engineering-sr-staff-engineer-dft-rtl-design-product-engineer/44408/92871142560","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL implementation","DFT/BIST","verification","flow automation","hierarchical SoC architectures","IEEE1149/1500 and 1687 standards","pattern porting","Synopsys TestMAX Tool chain","UVM environment","Synthesis","timing constraints (SDC)","Lint","CDC","RDC"],"x-skills-preferred":["error correcting codes","Hamming and Hsiao","GenAI","Agentic AI workflows"],"datePosted":"2026-04-05T13:20:45.356Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL implementation, DFT/BIST, verification, flow automation, hierarchical SoC architectures, IEEE1149/1500 and 1687 standards, pattern porting, Synopsys TestMAX Tool chain, UVM environment, Synthesis, timing constraints (SDC), Lint, CDC, RDC, error correcting codes, Hamming and Hsiao, GenAI, Agentic AI workflows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4ed1875c-bd2"},"title":"Physical Design Lead (With STA & Timing Constraints Expertise)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.</li>\n<li>Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.</li>\n<li>Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.</li>\n<li>Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power &amp; IR drop signoff to debug and resolve critical implementation bottlenecks.</li>\n<li>Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.</li>\n<li>Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock &amp; reset architecture improvements for enabling high speed timing closure, PPA improvements.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver signoff-quality, high-performance silicon solutions.</li>\n<li>Mentor and develop engineering teams.</li>\n<li>Drive process improvements and technical innovation.</li>\n<li>Enhance Synopsys’ leadership in high-speed IP.</li>\n<li>Facilitate successful cross-team collaboration.</li>\n<li>Enable next-generation chip architectures.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>MS in Electrical Engineering; 10+ years in physical design, static timing analysis.</li>\n<li>Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development &amp; qualification</li>\n<li>Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.</li>\n<li>Must have experience in leading and managing local, remote implementation teams.</li>\n<li>Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.</li>\n<li>Strong scripting and software skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Inclusive leader and effective communicator.</li>\n<li>Innovative, collaborative, and quality-driven.</li>\n<li>Thrives in dynamic environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a global engineering team advancing high-speed silicon IP design. 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