We are looking for a passionate and highly skilled engineer who thrives in a collaborative, fast-paced environment. With a deep understanding of analog design principles, you have honed your expertise in static timing analysis (STA) and timing characterization over 4-8 years in the semiconductor industry. You are driven by curiosity and a desire to solve complex challenges, always seeking innovative solutions to enhance performance and reliability.

As a STA and Timing Characterization Specialist, you will be responsible for driving DDR, HBM, and UCIE timing generation and validation in partnership with circuit design and layout teams. You will perform static timing analysis (STA) and timing characterization, ensuring robust timing constraints and accurate correlation with design requirements. You will also debug and resolve timing violations at both circuit and system levels, applying deep transistor-level simulation expertise.

You will utilize SiliconSmart, NanoTime, and advanced scripting to automate timing analysis workflows and improve efficiency. You will collaborate closely with internal development teams to communicate findings, propose solutions, and implement best practices. You will provide technical leadership, mentoring junior engineers, and championing quality and accountability throughout project lifecycles.

As a member of our team, you will be empowered to drive innovation and technical excellence, contributing to Synopsys' global leadership in chip design and integration.

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What You'll Be Doing:

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
• Perform STA (Static Timing Analysis) using industry-standard EDA tools.
• Support constraint development and validation for timing sign-off.
• Collaborate with design, verification, and physical implementation teams to resolve timing issues.
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)

Authority:

• Normally receives detailed instructions on all work.
• Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.
• Applies company policies and procedures to resolve routine issues.

What You'll Need:

• Bachelor's or Master's degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.
• 1-2 year working experience in similar roles or fresh graduates

(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position's requirements.)

• Basic understanding of timing analysis, SPICE simulation, and STA concepts.
• Experience with scripting languages such as Python and TCL for automation and data processing.
• Familiarity with EDA tools for timing characterization and verification.
• Strong problem-solving abilities and keen attention to detail.
• Good verbal and written English communication skills.
• Highly responsible and self-motivated, with a strong sense of ownership over your work.
• Collaborative team player, open to feedback and eager to learn from others.
• Detail-oriented and methodical, always striving for accuracy and quality.
• Effective communicator, able to articulate technical concepts clearly.
• Adaptable and resilient in the face of new challenges or shifting priorities.
• Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.

The Team You’ll Be A Part Of:

You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.

As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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