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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7c858523-91f"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_106cfbf6-843"},"title":"Physical Design Specialist (PDS)","description":"<p>We&#39;re looking for a Physical Design Specialist (PDS) to join our team. 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Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro &amp; Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.</p>\n<p>You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</p>\n<p>As a member of our high-performing Customer Application Services team, you will collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Support customers in enjoying Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge.</li>\n<li>Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n<li>Collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</li>\n<li>Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.</li>\n<li>Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.</li>\n</ul>\n<p>Key Qualifications:</p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.</li>\n<li>Tool knowledge expected: Back end P&amp;R tools (Fusion Compiler, ICC2, Innovus)</li>\n<li>Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),</li>\n<li>Tool knowledge (preferred): STA (Primetime, Tempus)</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_106cfbf6-843","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-principal-engineer/44408/92840962656","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Place & Route (physical)","Synthesis (logical and physical)","STA experience and knowledge","Macro & Standard Cell Placement","Clock Tree Synthesis","Routing","Advanced Timing Optimization techniques","Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2)"],"x-skills-preferred":["RTL to GDSII full flow experience","Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis)","Clock Tree Synthesis methodologies like H-Tree, MS-CTS"],"datePosted":"2026-04-05T13:22:15.432Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge, Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques, Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2), RTL to GDSII full flow experience, Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis), Clock Tree Synthesis methodologies like H-Tree, MS-CTS"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2f9b4dd6-6f1"},"title":"Emulation Applications Engineer, Sr. Staff","description":"<p>We currently have an opening for an Emulation Applications Engineer, Sr. Staff to join our team. As a member of our team, you will collaborate closely with R&amp;D architects and customers on hardware-assisted verification products. You will drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.</p>\n<p>Responsibilities:</p>\n<ul>\n<li><p>Collaborate with R&amp;D architects and customers on hardware-assisted verification products.</p>\n</li>\n<li><p>Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.</p>\n</li>\n<li><p>Define test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.</p>\n</li>\n<li><p>Become an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.</p>\n</li>\n<li><p>Leverage your close interaction with customers, R&amp;D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.</p>\n</li>\n<li><p>Adapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.</p>\n</li>\n<li><p>Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.</p>\n</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li><p>Enhance Synopsys&#39; emulation and prototyping solutions by driving technology development and customer deployment.</p>\n</li>\n<li><p>Improve the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.</p>\n</li>\n<li><p>Provide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.</p>\n</li>\n<li><p>Ensure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.</p>\n</li>\n<li><p>Support the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.</p>\n</li>\n<li><p>Facilitate the proliferation of Synopsys&#39; differentiated emulation/verification environment through close collaboration with multiple teams.</p>\n</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li><p>BSEE/MS with 7+ years of related experience.</p>\n</li>\n<li><p>Expertise in Emulation and/or Prototyping flows, systems, and methodologies.</p>\n</li>\n<li><p>Strong proficiency in Verilog, System Verilog, and VHDL.</p>\n</li>\n<li><p>Understanding of verification concepts and experience with functional simulators.</p>\n</li>\n<li><p>Experience with scripting languages.</p>\n</li>\n<li><p>Knowledge in Simulation flows, Assertion, DPI, and Transactors.</p>\n</li>\n<li><p>Complex problem-solving and debugging skills.</p>\n</li>\n<li><p>Strong communication skills and the ability to interact with customers and peers.</p>\n</li>\n<li><p>Knowledge in synthesis and timing analysis concepts (preferred).</p>\n</li>\n<li><p>Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).</p>\n</li>\n<li><p>Experience with Xilinx &amp; Altera architecture and toolchains (preferred).</p>\n</li>\n<li><p>Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).</p>\n</li>\n</ul>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2f9b4dd6-6f1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/emulation-applications-engineer-sr-staff-15518/44408/92669904624","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$157000-$235000","x-skills-required":["Emulation and/or Prototyping flows, systems, and methodologies","Verilog, System Verilog, and VHDL","Verification concepts and functional simulators","Scripting languages","Simulation flows, Assertion, DPI, and Transactors"],"x-skills-preferred":["Synthesis and timing analysis concepts","Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality","Xilinx & Altera architecture and toolchains","SW/HW debug methodologies and standard SW/HW debug tools"],"datePosted":"2026-04-05T13:21:37.842Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Emulation and/or Prototyping flows, systems, and methodologies, Verilog, System Verilog, and VHDL, Verification concepts and functional simulators, Scripting languages, Simulation flows, Assertion, DPI, and Transactors, Synthesis and timing analysis concepts, Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality, Xilinx & Altera architecture and toolchains, SW/HW debug methodologies and standard SW/HW debug tools","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e14d730c-676"},"title":"Analog Design, Staff Engineer - SERDES","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p><em>big_They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</em></p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Staff Engineer in our Analog Design team, you will be responsible for designing and developing full custom analog circuit macros for high-speed SERDES PHY IP.</p>\n<p>Your responsibilities will include designing and developing full custom analog circuit macros for high-speed SERDES PHY IP, including transceivers, voltage/current-mode drivers, PLLs, DLLs, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, and clock data recovery circuits.</p>\n<p>You will also collaborate with cross-functional teams locally and globally to refine circuit implementations and achieve optimal power, area, and performance targets.</p>\n<p>In addition, you will ensure analog sub-block performance adheres to SerDes standards and architecture specification documents.</p>\n<p>You will lead verification strategies using advanced simulator features to guarantee the highest quality design outcomes.</p>\n<p>You will oversee physical layout processes to minimize parasitic effects, device stress, and process variations.</p>\n<p>You will present simulation data for peer and customer reviews, and document design features and test plans.</p>\n<p>You will consult on electrical characterization and support the integration of your circuit within the SerDes IP product.</p>\n<p>You will handcraft high-performance clock and data paths using digital/CMOS logic cells and verify timing margins with SPICE and STA tools.</p>\n<p>You will address ESD and latch-up design verification, crosstalk coupling impacts, and ensure robust mixed-signal analog design.</p>\n<p>The impact you will have includes accelerating development of high-performance silicon chips critical to emerging technologies like AI, IoT, and 5G.</p>\n<p>You will optimize chip designs for power, cost, and performance, helping customers reduce project schedules by months.</p>\n<p>You will advance Synopsys&#39; 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.</p>\n<p><strong>Responsibilities</strong></p>\n<p>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</p>\n<p>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</p>\n<p>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</p>\n<p>Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&amp;R-aware synthesis using tools such as Fusion Compiler.</p>\n<p>Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.</p>\n<p>Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</p>\n<p>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</p>\n<p>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</p>\n<p>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</p>\n<p>Familiarity with high-speed design (&gt;600MHz), P&amp;R-aware synthesis, and EDA tools such as Fusion Compiler.</p>\n<p>Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.</p>\n<p>Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).</p>\n<p>Exposure to quality processes in IP design and verification is an advantage.</p>\n<p>Prior experience as a technical lead or mentor is highly desirable.</p>\n<p><strong>Who We Are Looking For</strong></p>\n<p>Innovative thinker with a solutions-oriented mindset and a passion for technology.</p>\n<p>Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.</p>\n<p>Natural leader with mentoring abilities, fostering inclusion and diversity within the team.</p>\n<p>Detail-oriented professional with strong analytical and problem-solving skills.</p>\n<p>Self-motivated, adaptable, and eager to drive technical excellence and process improvements.</p>\n<p>Committed to continuous learning and staying ahead of industry trends.</p>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry 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intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/09/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>\n<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b5f1283c-76e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","System architecture","ASIC solutions","High-performance protocols","DDR PHY","PCIe","USB","HBM","Verilog","SystemVerilog","Simulation tools","Design flows","Lint","CDC","Synthesis","Static timing analysis","Formal verification","Control path-oriented designs","Asynchronous FIFOs","DMA","SPRAM/DPRAM interfaces","Scripting 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semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15411</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff Applications Engineer, Digital Implementation</li>\n</ul>\n<ul>\n<li>Staff AE – RTL-to-GDS Solutions</li>\n</ul>\n<ul>\n<li>Senior Digital Design Flow Engineer</li>\n</ul>\n<ul>\n<li>Customer Success Engineer – Physical Design</li>\n</ul>\n<ul>\n<li>Staff Field Applications Engineer – EDA</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.</p>\n<p>You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&amp;D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.</p>\n<p>You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.</li>\n</ul>\n<ul>\n<li>Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.</li>\n</ul>\n<ul>\n<li>Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.</li>\n</ul>\n<ul>\n<li>Collaborate with global Applications Engineering, R&amp;D, and Product Management teams to enhance methodologies and influence tool development.</li>\n</ul>\n<ul>\n<li>Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.</li>\n</ul>\n<ul>\n<li>Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.</li>\n</ul>\n<ul>\n<li>Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.</li>\n</ul>\n<ul>\n<li>Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.</li>\n</ul>\n<ul>\n<li>Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.</li>\n</ul>\n<ul>\n<li>Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.</li>\n</ul>\n<ul>\n<li>Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.</li>\n</ul>\n<ul>\n<li>Champion best practices and knowledge sharing within the Applications Engineering community.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.</li>\n</ul>\n<ul>\n<li>Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.</li>\n</ul>\n<ul>\n<li>Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.</li>\n</ul>\n<ul>\n<li>Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.</li>\n</ul>\n<ul>\n<li>Exceptional communicator, comfortable engaging with both internal teams and external partners.</li>\n</ul>\n<ul>\n<li>Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.</li>\n</ul>\n<ul>\n<li>Collaborative team player, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Customer-focused, energetic, and adaptable to fast-paced, evolving environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&amp;D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine **around the office*</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9a8cc13a-0a3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/penang/staff-applications-engineer-digital-implementation/44408/92092150640","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDS flows","digital synthesis","physical implementation","static timing analysis","advanced node design","floorplanning","PPA optimization","signoff-driven closure","scripting languages","Tcl","Python","Perl","EDA tool ecosystems"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:20.254Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Penang, Malaysia"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDS flows, digital synthesis, physical implementation, static timing analysis, advanced node design, floorplanning, PPA optimization, signoff-driven closure, scripting languages, Tcl, Python, Perl, EDA tool ecosystems"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4b33752-a69"},"title":"Application Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.</p>\n<p>You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.</p>\n<p>You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.</p>\n<p>You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.</p>\n<p>The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.</p>\n<p>You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&amp;D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys&#39; reputation as a trusted partner and thought leader in the semiconductor industry.</p>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.</li>\n<li>Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).</li>\n<li>Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place &amp; Route, and timing analysis.</li>\n<li>Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.</li>\n<li>Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.</li>\n<li>Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.</li>\n<li>Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent communicator able to build trust and rapport with diverse stakeholders.</li>\n<li>Analytical thinker with strong troubleshooting and debugging skills.</li>\n<li>Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.</li>\n<li>Highly collaborative team player who thrives in fast-paced, multicultural environments.</li>\n<li>Self-motivated, innovative, and passionate about continuous learning and process improvement.</li>\n<li>Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, expert team within the Silicon Design &amp; Verification business at Synopsys, based in Hyderabad. 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This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.</p>\n<p>As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits:</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine around the office can be like</p>\n<p>\\ Explore Ho Chi Minh City</p>\n<p>View Map</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_eb9218fe-189","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/timing-analog-mixed-signal-design-engineer-hcmc/44408/92554331200","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["timing analysis","SPICE simulation","STA concepts","Python","TCL","EDA tools","timing characterization","verification"],"x-skills-preferred":["problem-solving","detail-oriented","effective communication","adaptability","resilience"],"datePosted":"2026-03-09T11:00:31.108Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"timing analysis, SPICE simulation, STA concepts, Python, TCL, EDA tools, timing characterization, verification, problem-solving, detail-oriented, effective communication, adaptability, resilience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_42529dfa-e50"},"title":"Staff Software Engineer (R&D Engineering)","description":"<p>We are seeking a highly skilled Staff Software Engineer to join our R&amp;D Engineering team. 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