You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.

What You'll Be Doing:

• Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
• Driving the deployment and smooth execution of SLM and Test solutions into customers' projects.
• Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• Enhancing Synopsys' Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
• Driving the adoption of Synopsys' SLM and DFT solutions at premier customer base worldwide.
• Influencing the development of next-generation SLM IPs and solutions.

What You'll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.

• 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.

• Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.

• Knowledge on memory defectivities soft errors and reliability.

• Familiarity with error correcting codes such as Hamming and Hsiao.

• Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.

• Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.

• Debugging abilities to identify and resolve issues in functional verification in UVM environment.

• Hands on experience in flow automation.

• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).

• Knowledge of Lint, CDC, RDC is a plus.

• Knowledge of physical implementation is not a must, but good to have.

• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.

• Customer facing experience is a plus – educating/guiding customer on technical details of a solution.

• Good to have:

• Hands-on bring-up and debug experience of silicon is a plus.

• Architecture/micro-architecture experience.

• Understanding of GenAI and Agentic AI workflows.

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This role is ideal for an engineer who enjoys deep technical work , analysing complex logic simulations, working across hardware and software, and driving improvements in test efficiency and overall QoR. You’ll be hands-on with Verilog, simulation/debug, and C/C++ development, influencing key aspects of next-generation DFT solutions.

Responsibilities:

• Contribute across the entire DFT flow: RTL, netlist, ATPG, and logic simulation
• Analyse DFT IP behaviour, debug logic issues, and deliver robust fixes
• Enhance pattern-generation workflows for better performance and QoR
• Develop C/C++ components for pattern processing, automation, and data handling
• Work closely with multi-site R&D teams to ensure smooth flow integration
• Use AI-based tools to accelerate debugging, code comprehension, and analysis

Requirements:

• Master’s degree in Electronics, Computer Science, or equivalent, with background in both Verilog and C/C++.
• Strong understanding of DFT, scan architectures, and test-generation concepts
• Hands-on experience with Verilog and logic-simulation debug
• Proficiency in C/C++ programming
• Ability to work effectively across large-scale SoC hardware and complex software environments.
• Strong analytical and root-cause-debugging skills
• Openness to using AI tools to boost productivity

Nice to Have:

• Experience with TestMAX, Tessent, Modus, or similar DFT/ATPG tools
• Knowledge of pattern compression, hierarchical DFT, or test scheduling
• Experience with automation or performance-oriented C/C++ code

Why Join Synopsys:

You’ll work on core DFT technologies used by the world’s leading semiconductor companies. Your contributions will directly strengthen the Streaming Fabric and SEQ solution and support their integration into the TestMAX ecosystem , enabling improved scalability, test efficiency, and product quality.

If you’re excited by deep technical challenges and want to work on impactful DFT innovation, we’d love to hear from you.

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