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  <jobs>
    <job>
      <externalid>89a82cda-38e</externalid>
      <Title>ASIC Physical Design, Sr Staff Engineer</Title>
      <Description><![CDATA[<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>
<p>We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.</p>
<p>As a Sr Staff Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship, continuously improving design methodologies and processes to enhance efficiency and quality.</p>
<p>The impact you will have is driving the development of high-performance physical IP that powers next-generation technologies, ensuring the reliability and efficiency of physical design solutions in our products, contributing to the success of Synopsys&#39; strategic goals through innovative design solutions, sharing technical expertise to elevate team capabilities, fostering a culture of continuous improvement and excellence within the engineering team, and supporting the adoption and usability of our products by providing top-tier engineering expertise.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>Physical Design, Mixed Signal IPs, Test Chips, RTL to GDSII, Synopsys Tools and Methodologies, Chip Architecture, Circuit Design, Verification, Problem-Solving, Communication</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and services used to design, implement, and verify complex integrated circuits and systems-on-chip (SoCs).</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-staff-engineer-in-hcmc-or-da-nang/44408/94030515824</Applyto>
      <Location>Ho Chi Minh City</Location>
      <Country></Country>
      <Postedate>2026-04-24</Postedate>
    </job>
    <job>
      <externalid>3bb7e3ce-9f9</externalid>
      <Title>ASIC Physical Design, Principal Engineer</Title>
      <Description><![CDATA[<p>We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. As an ASIC Physical Design, Principal Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</p>
<p><strong>What you&#39;ll do</strong></p>
<ul>
<li>Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</li>
<li>Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.</li>
<li>Providing technical guidance and mentorship.</li>
<li>Continuously improving design methodologies and processes to enhance efficiency and quality.</li>
</ul>
<p><strong>What you need</strong></p>
<ul>
<li>BE or MSEE with 10+ years of direct physical design experience.</li>
<li>Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.</li>
<li>Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.</li>
</ul>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>Physical Design, Mixed Signal IPs, Test Chips, RTL to GDS, Timing and Physical Sign-off, Cross-functional Team Collaboration</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and intellectual property (IP) for the semiconductor industry. The company&apos;s technology is used to design and develop complex semiconductor solutions, enabling innovations in various industries.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-principal-engineer-in-tan-binh-district/44408/91117302576</Applyto>
      <Location>Tan Binh district, Ho Chi Minh City</Location>
      <Country></Country>
      <Postedate>2026-03-06</Postedate>
    </job>
    <job>
      <externalid>24cf88fb-d67</externalid>
      <Title>Software Engineering, Staff</Title>
      <Description><![CDATA[<p>Opening. This role is for an experienced and innovative software engineer ready to tackle complex challenges at the intersection of hardware and software.</p>
<p><strong>What you&#39;ll do</strong></p>
<p>You will design, develop, troubleshoot, and debug software programs for PCIe IP evaluation and test chip platforms.</p>
<ul>
<li>Designing, developing, troubleshooting, and debugging software programs for PCIe IP evaluation and test chip platforms.</li>
<li>Developing scalable software tools, APIs, and architectures focused on evaluation software for Synopsys PCIe evaluation boards.</li>
</ul>
<p><strong>What you need</strong></p>
<ul>
<li>Comprehensive expertise in PCIe protocol, SERDES, and hands-on experience with evaluation boards, silicon validation, or test chips.</li>
<li>Advanced proficiency in Python, C++, or similar programming languages for embedded, driver, or system-level development.</li>
</ul>
<p><strong>Why this matters</strong></p>
<p>Accelerate the evaluation and adoption of Synopsys&#39;s latest PCIe IP and test chips by delivering robust, user-friendly software tools. Enable seamless hardware bring-up and protocol validation, empowering both customers and internal teams to assess performance and compliance efficiently.</p>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>staff</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange>$120000-$180000</Salaryrange>
      <Skills>Comprehensive expertise in PCIe protocol, Advanced proficiency in Python, C++, or similar programming languages, Hands-on experience with evaluation boards, silicon validation, or test chips, Experience with evaluation software, hardware bring-up, or test automation frameworks for high-speed IP, Knowledge of signal integrity, compliance testing, and PCIe ecosystem tools, Customer-facing support experience</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys drives the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/hillsboro/software-engineering-staff-15410/44408/92145153776</Applyto>
      <Location>Hillsboro, Oregon, United States</Location>
      <Country></Country>
      <Postedate>2026-03-04</Postedate>
    </job>
  </jobs>
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