{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/technical-mentorship"},"x-facet":{"type":"skill","slug":"technical-mentorship","display":"Technical Mentorship","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ac561bbf-75b"},"title":"Memory Compiler Architect","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>As a Memory Compiler Architect, you will be responsible for designing, developing, and evaluating physical IP,Memory compilers (SRAM/RF/ROM/TCAM etc.). You will apply expertise in circuit design, memory architecture optimization for best-in-class PPA and industry-standard verification tools to optimize workflows and enhance design efficiency.</p>\n<p>Collaborate with cross-functional teams to align project deliverables with business objectives. Contribute to the technical direction and problem-solving efforts within the engineering group. Share knowledge and support the professional growth of team members through technical mentorship.</p>\n<p>Advance our product portfolio with innovative solutions addressing market demands. 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Support the growth and technical development of colleagues through guidance and collaboration.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Designing, developing, and evaluating physical IP,Memory compilers (SRAM/RF/ROM/TCAM etc.)</li>\n<li>Applying expertise in circuit design, memory architecture optimization for best-in-class PPA and industry-standard verification tools to optimize workflows and enhance design efficiency</li>\n<li>Collaborating with cross-functional teams to align project deliverables with business objectives</li>\n<li>Contributing to the technical direction and problem-solving efforts within the engineering group</li>\n<li>Sharing knowledge and supporting the professional growth of team members through technical mentorship</li>\n</ul>\n<p>Requirements include:</p>\n<ul>\n<li>Bachelor&#39;s or master&#39;s degree in Electrical Engineering, Computer Science, or a related field</li>\n<li>15+ years of experience in embedded memory design (SRAM/RF/ROM/TCAM), including functional verification with industry-standard tools</li>\n<li>Significant experience in memory compiler flow</li>\n<li>Proficiency in Python and Hspice/XA</li>\n<li>Familiarity with industry-standard verification tools for design and signoff flows</li>\n<li>Strong problem-solving and technical skills</li>\n<li>Ability to work collaboratively and communicate effectively within and across teams</li>\n</ul>\n<p>The ideal candidate will be an effective communicator who engages and influences stakeholders. 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and scalability of the next generation of model serving and inference platforms for Ads.</p>\n<p>As a senior technical leader, you’ll design and optimize high-performance serving systems and GPU inference frameworks that drive measurable latency improvements and cost efficiency across Microsoft’s ad ecosystem.</p>\n<p>You’ll work across the stack,from CUDA kernel tuning and NUMA-aware threading to large-scale distributed orchestration and model deployment for deep learning and LLM workloads.</p>\n<p>This is a rare opportunity to shape the architecture of one of the world’s most advanced, mission-critical online serving platforms, collaborating with world-class engineers to deliver innovation at Internet scale.</p>\n<p>Microsoft’s mission is to empower every person and every organization on the planet to achieve more.</p>\n<p>As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals.</p>\n<p>Each day we build on our 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tiers).</p>\n<p>Profile and optimize performance across the full stack,from CUDA kernels and GPU pipelines to CPU threads and OS-level scheduling,identifying bottlenecks, tuning latency tails, and improving cost efficiency through advanced profiling and instrumentation.</p>\n<p>Own live-site reliability as a DRI: design telemetry, alerting, and fault-tolerance mechanisms; drive rapid diagnosis and mitigation of performance regressions or outages in globally distributed systems.</p>\n<p>Collaborate and mentor across teams,driving architecture reviews, enforcing engineering excellence, promoting system-level optimization practices, and mentoring others in deep debugging, profiling, and performance engineering.</p>\n<p>Qualifications:</p>\n<p>Required Qualifications:</p>\n<p>Bachelor’s Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.</p>\n<p>Preferred Qualifications:</p>\n<p>Master’s Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor’s Degree in Computer Science or related technical field AND 12+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.</p>\n<p>Industry experience in advertising or search engine backend systems, such as large-scale ad ranking, real-time bidding (RTB), or relevance-serving infrastructure.</p>\n<p>Hands-on experience with real-time data streaming systems (Kafka, Flink, Spark Streaming), feature-store integration, and multi-region deployment for low-latency, globally distributed services.</p>\n<p>Familiarity with LLM inference optimization,model sharding, tensor/kv-cache parallelism, paged attention, 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rollout, and adaptive inference scheduling across CPU/GPU tiers.</p>\n<p>Proven ability to profile and optimize GPU and system workloads,including tensor/memory alignment, compute–memory balancing, embedding table management, parameter servers, hierarchical caching, and vectorized inference for transformer/LLM architectures.</p>\n<p>Expertise in low-level system and OS internals, including multi-threading, process scheduling, NUMA-aware memory allocation, lock-free data structures, context switching, I/O stack tuning (NVMe, RDMA), kernel bypass (DPDK, io_uring), and CPU/GPU affinity optimization for large-scale serving pipelines.</p>\n<p>#MicrosoftAI Software Engineering IC5 – The typical base pay range for this role across the U.S. is USD $139,900 – $274,800 per year. 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