As a Senior RTL/Synthesis Digital Design Engineer, you will be responsible for architecting and developing RTL for high-bandwidth PHY IP and test chips. You will define synthesis constraints, resolve STA and simulation issues, and collaborate with verification, controller, and lab teams.

Key responsibilities include:

• Performing logical and physical synthesis, formal verification, and quality checks
• Analysing timing violations and generating reports
• Mentoring junior engineers and supporting digital flow development

The ideal candidate will have a strong background in RTL design and synthesis, with expertise in industry tools such as VCS, Verdi, Spyglass, and Synopsys sign-off. You should also have good English communication skills and be able to work effectively in a team.

At Synopsys, we value talented individuals who are passionate about technology and problem-solving. We offer a comprehensive benefits package, including health and wellness programs, time away, family support, and competitive compensation.

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Your responsibilities will include:

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

To be successful in this role, you will need:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.

The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.

To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).

You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.

Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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We are seeking a skilled Firmware Design Engineer to join our team. As a Firmware Design Engineer, you will be responsible for designing, implementing, and validating firmware for embedded microprocessors in advanced SerDes and PHY IP.

Key Responsibilities:

• Architect, implement, and validate firmware for embedded microprocessors in advanced SerDes and PHY IP.
• Lead silicon bring-up and debug cycles, supporting lab triage, instrumented root-cause analysis, and cross-functional closure with design, DV, validation, and applications teams.
• Apply mixed-signal debugging expertise to isolate HW/FW boundary issues, leveraging knowledge of analog behavior, clocks/resets, power states, and link training.
• Develop high-quality embedded code in C/C++, ensuring robust design reviews, code reviews, unit testing, and disciplined defect prevention practices.
• Scale automation through CI/CD pipelines using Jenkins and test frameworks to improve coverage, reliability, and release confidence.
• Define validation strategies, create automated test cases, and drive coverage analysis across multiple firmware projects.
• Build and maintain AI-assisted firmware workflows using tools such as Cursor, focusing on prompt/trace hygiene, guardrails, and verification practices.
• Operationalize agentic AI patterns for firmware development, including planning, code generation, refactoring, test creation, log triage, and regression analysis with explicit human review points.
• Author and curate reusable rules, skills, and commands to standardize AI usage (coding standards, spec templates, “definition of done,” test expectations, and safety checks).
• Lead process maturity initiatives, driving adoption of coding standards, branching/release hygiene, documentation quality, and review discipline, making adherence measurable.
• Operationalize status and quality tracking via JIRA dashboards and Confluence, providing clear, repeatable reporting on best-practice and AI-workflow adoption.
• Mentor and provide technical leadership, elevating team capability through coaching, review guidance, and hands-on problem solving in critical debug cycles.

Requirements:

• Embedded firmware experience: 5+ years building and debugging embedded firmware for silicon products (bring-up, lab debug, sustained maintenance).
• Programming: Expert in C/C++; strong scripting proficiency in Python (plus Bash and/or Tcl).
• Debug: Demonstrated strength in silicon bring-up, lab instrumentation, and HW/FW boundary root-cause analysis.
• Mixed-signal systems: Practical experience debugging systems involving analog and digital behavior (SerDes/PHY, clocking, resets, power, signal integrity impacts).
• Validation and automation: Proven ability to build automation, test frameworks, and coverage strategy; experience with Jenkins CI/CD.
• AI tooling: Hands-on experience using Cursor (or equivalent) in production engineering workflows, including building reusable prompts/workflows and enforcing verification/quality gates.
• Agentic workflows: Experience defining agentic workflows with clear boundaries, review points, and safety rails (including when not to use AI).
• Process leadership: Track record of scaling best practices across a team (reviews, test discipline, release hygiene, documentation standards).
• Collaboration: Strong cross-functional communication across firmware, hardware/design, DV/validation, and multi-site teams.
• Education: BSEE/MSEE (or equivalent practical experience).

We offer a competitive salary and benefits package, as well as opportunities for professional growth and development.

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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As a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team

Impact:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys
• Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail
• A collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

You are an Automation Engineer/Software Developer who develops scripts, tools, and workflows to automate routine design tasks, enhancing efficiency, precision, and standardization. With a strong foundation in Software Development lifecycle, Software testing and deployment. You are creating methodologies and documentation for the users you support.

Your problem-solving skills and proficiency in UNIX/Linux and programming languages make you a valuable team player.

Your strong communication skills in English enable you to effectively document methods and training materials, ensuring your team can leverage new tools and flows to increase efficiency. You are proactive in providing feedback to improve internal tools and are committed to streamlining design processes and reducing time-to-market.

What You’ll Be Doing:

• Design, develop, troubleshoot, or debug software tools for integrated circuits.
• Develop automation tools, data pipelines, workflows for Analog design teams, to improve project methodologies and lifecycle efficiency.
• Providing feedback to internal tools teams to enhance tool functionality and usability.
• Documenting methods, creating documentation, and training materials for internal designers.
• Collaborating with cross-functional teams to ensure seamless integration and optimization of design tools.

The Impact You Will Have:

• Ensuring the successful implementation of new design methodologies and tools within the team.

• Enhancing the overall efficiency of analog design processes within Synopsys.

• Reducing time-to-market for high-performance silicon chips and software content.

• Driving innovation by providing valuable feedback to improve internal design tools and flows.

• Contributing to the development of cutting-edge technology that shapes the future of the industry.

What You’ll Need:

• Bachelor’s degree in software engineering/electrical engineering or similar field and 2 years of related experience.
• Experience with OOP languages, Python is preferred.
• Experience with CI/CD tools and workflows.
• Familiarity with UNIX/Linux operating systems and shell scripting,
• Experience with Tcl, Perl, Bash, JavaScript is a plus.
• Experience with latest GenAI tools development is a big plus.
• Experience with EDA tools for schematic entry, physical layout, design verification and circuit simulations is a big plus.
• Prior experience working with VLSI design methodology is big plus.

Who You Are:

• Excellent communication skills in English.
• A team player with a collaborative mindset.
• Proactive in debugging and resolving issues independently.
• Skilled in creating clear and concise documentation.

The Team You’ll Be A Part Of:

You will be part of a dynamic team dedicated to streamlining design processes and reducing time-to-market. This team focuses on developing, testing, improving and training designers on cutting-edge flows and tools at Synopsys to enhance analog design efficiency. Your role will involve significant collaboration with cross-functional teams to foster a culture of continuous improvement and innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.

Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.

What You’ll Be Doing:

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.
• Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.
• Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
• Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.

The Impact You Will Have:

• Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.
• Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.
• Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.
• Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.
• Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.
• Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimisation, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.
• Exposure to high-frequency design and low-power design methodologies.

Who You Are:

• Proactive, self-motivated, and driven to achieve technical excellence.
• Exceptional problem-solving and analytical skills with a keen attention to detail.
• Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
• Collaborative team player who values knowledge sharing and mentoring others.
• Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.

The Team You’ll Be A Part Of:

You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.

As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.

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Your key responsibilities will include driving product adoption through competitive benchmarking, customer evaluations, and articulating product advantages to design teams and management. You will also deliver customer training, technical presentations, and hands-on workshops to maximize user proficiency and satisfaction.

In addition, you will provide tape-out support, troubleshoot complex timing issues, and ensure successful project completion. You will collaborate with R&D, marketing, and sales to relay customer feedback and influence product enhancements.

To succeed in this role, you will need expertise in Synopsys PrimeTime STA tool, with hands-on experience and deep knowledge of its features. You will also require strong understanding of timing corners, process variations, and signal integrity-related issues.

If you are a collaborative team player who values diverse perspectives and fosters inclusive environments, we encourage you to apply.

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As a Senior Staff Engineer in RTL Design and Verification, you will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance.

You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.

You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

You will accelerate the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions.

You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy. You will enable successful integration of advanced 3D-IC technologies, expanding Synopsys' leadership in the market.

You will foster strong customer relationships through technical expertise and responsive support. You will contribute to a culture of excellence and continuous learning within the engineering team.

To succeed in this role, you will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will require 8+ years of hands-on experience in RTL design and verification.

You will need proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. You will need experience working in Unix/Linux environments.

You will need strong debugging and problem-solving skills, especially in complex chip design environments. You will need excellent written and verbal communication skills in English.

Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus. Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

As a Principal STA Engineer, you will be responsible for owning full-chip and block-level STA sign-off across all PVT corners and operational modes. You will drive timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.

Responsibilities

• Owning full-chip and block-level STA sign-off across all PVT corners and operational modes.
• Driving timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.
• Analyzing and resolving setup/hold violations, noise, signal integrity (SI), OCV, and derates.
• Defining and validating timing margins, guard-bands, and sign-off criteria for advanced node designs.
• Managing complexities at 7nm, 5nm, and 3nm nodes, including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution.
• Developing and reviewing SDC constraints (clocks, IO delays, exceptions) for MCMM designs.
• Building scalable timing methodologies and driving constraint validation and consistency across teams.
• Utilizing STA tools (Primetime, Tempus) and scripting (Tcl/Python) for automation and flow efficiency.
• Leading timing reviews and sign-off meetings with cross-functional stakeholders.

The Impact You Will Have

• Ensuring successful tapeouts and robust silicon performance at advanced technology nodes.
• Driving innovation in timing sign-off methodologies, influencing industry standards and best practices.
• Reducing time-to-market by achieving efficient timing closure and minimizing design iterations.
• Enhancing cross-functional collaboration and knowledge sharing within Synopsys engineering teams.
• Mentoring and developing junior engineers, building a stronger and more resilient team.
• Contributing to architectural decisions that improve timing convergence and silicon reliability.
• Streamlining timing analysis workflows through automation, improving productivity and accuracy.

What You’ll Need

• B.Eng, or MS in Electrical Engineering or a related field.
• 10–15+ years of experience in STA and timing sign-off for SoCs.
• Proven record of successful tapeouts in advanced nodes (7nm, 5nm, 3nm).
• Expertise in STA tools (Primetime, Tempus) and scripting languages (Tcl, Python, Perl).
• Deep understanding of EM/IR and reliability impacts on timing.
• Experience with full-chip integration and hierarchical STA methodologies.
• Ability to develop scalable timing methodologies for MCMM designs.

Who You Are

• Technical leader and mentor, passionate about knowledge sharing.
• Collaborative communicator, able to lead cross-functional teams and drive consensus.
• Detail-oriented and analytical, with a relentless focus on quality and accuracy.
• Innovative thinker, eager to explore new approaches and technologies.
• Adaptable, capable of navigating fast-paced and evolving engineering environments.
• Confident decision-maker, able to advocate for best practices and influence architectural choices.

The Team You’ll Be A Part Of

You will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

In addition to company holidays, we have ETO and FTO Programs.

• Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

Save for your future with our retirement plans that vary by region and country.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a passionate and detail-oriented engineering professional who thrives in collaborative environments and enjoys working at the intersection of technology and customer engagement. You possess a deep understanding of VLSI and Design for Testability (DFT) methodologies, and you are eager to use your expertise to drive innovation in semiconductor design.

Collaborating with leading semiconductor design companies to understand their engineering methodologies and unique challenges. Partnering with Account and R&D teams to develop, implement, and optimize stable and scalable tool solutions tailored to customer needs. Gathering and refining technical requirements, providing regular updates, and ensuring alignment across cross-functional teams. Applying advanced Design for Testability (DFT) concepts, including scan insertion, to enhance the reliability and manufacturability of customer designs. Delivering impactful presentations and hands-on demonstrations to customers, highlighting the value and capabilities of Synopsys solutions. Monitoring industry developments and integrating the latest advancements into customer engagements and tool methodologies. Automating workflows and customizing solutions using scripting languages such as TCL, Python, or Perl.

Empowering semiconductor companies to streamline their design processes and achieve higher quality outcomes. Driving customer satisfaction by delivering robust, scalable, and innovative solutions that address real-world engineering challenges. Enhancing the adoption and effectiveness of Synopsys toolsets through expert guidance and technical support. Contributing to the evolution of industry best practices in Design for Testability and automation. Facilitating strong partnerships between Synopsys and its customers, fostering long-term collaboration and success. Enabling faster time-to-market and improved product reliability for customer designs. Helping Synopsys maintain its leadership position in semiconductor innovation and technology advancement.

Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or related field. 3+ years of relevant experience in semiconductor design, DFT, or related domains. Strong understanding of VLSI design principles and DFT methodologies. Expertise in DFT scan insertion and related verification techniques. Proficiency with scripting languages such as TCL, Python, or Perl for automation and tool customization. Experience with semiconductor design tools and tool flows is highly desirable.

Excellent communicator, able to present complex technical concepts clearly to diverse audiences. Collaborative team player who thrives in cross-functional environments. Analytical thinker with strong problem-solving skills and a proactive approach. Adaptable and resilient, comfortable working in a fast-paced and dynamic industry. Customer-focused, always seeking to deliver value and build positive relationships. Continuous learner, passionate about staying at the forefront of industry trends and technologies.

You’ll join a dynamic, highly skilled team of Application Engineers and Product Specialists dedicated to advancing semiconductor design methodologies and delivering value to customers. The team collaborates closely with Account Managers and R&D experts, ensuring that customer requirements are met with innovative, reliable, and scalable solutions. Together, you will contribute to Synopsys’ reputation for excellence, support each other’s growth, and drive the future of technological innovation in the semiconductor industry.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.

To be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

As a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces.

With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers.

Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs.

You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges.

Your experience spans both the theoretical and practical aspects of circuit design,from transistor-level fundamentals to silicon-proven implementations.

You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes.

As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence.

You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement.

Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.

Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.

Track and review the technical progress of sub-block owners, ensuring alignment with project goals.

Interpret SerDes standards and architecture documents to develop detailed analog specifications.

Identify and refine circuit implementations, optimizing for power, area, and performance targets.

Propose and execute design and verification strategies using advanced simulator features for robust outcomes.

Oversee physical layout to minimize parasitics, device stress, and process variation impacts.

Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.

Present simulation data and technical insights for peer and customer reviews.

Mentor and review the progress of junior engineers, fostering growth and technical excellence.

Document design features, methodologies, and test plans for internal and customer use.

Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.

Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.

Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.

Contribute to the success of global customers by delivering robust, silicon-proven analog macros.

Enhance cross-functional collaboration across design, layout, and digital teams.

Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.

Influence the direction of advanced analog design methodologies and verification strategies.

Provide technical leadership in customer engagements and peer reviews.

Support continuous improvement in design processes and documentation practices.

PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.

Expertise in transistor-level circuit design and strong CMOS design fundamentals.

Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.

Leadership experience in guiding small teams through macro-level design projects.

In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.

Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.

Awareness of ESD and reliability issues, including circuit techniques and layout strategies.

Proficiency with EDA tools for schematic entry, physical layout, and design verification.

Experience with SPICE simulators for detailed circuit analysis.

Familiarity with analog behavioral modeling and simulation control using Verilog-A.

Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.

Analytical thinker with exceptional problem-solving skills.

Collaborative leader and effective communicator.

Detail-oriented and methodical in approach.

Adaptable and open to learning new technologies.

Mentor and role model for junior engineers.

Self-motivated and proactive in driving project outcomes.

Committed to excellence, reliability, and innovation.

You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions.

The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products.

Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce.

We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

Should you require an accommodation, please contact hr-help-canada@synopsys.com.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.

You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.

You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks. Performing digital design validation and functional verification at both block and SoC levels. Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs. Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing. Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance. Utilizing and scripting in languages such as Tcl to automate design and verification workflows. Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides.

Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies. Shape the evolution of embedded memory test and SLM architectures that power next-generation devices. Drive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products. Enhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support. Contribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks. Mentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth. Influence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization. Support strategic decision-making by providing technical insights and market-driven recommendations.

2-4 years of relevant experience in ASIC digital design and verification. Proficiency in RTL simulation, logic synthesis, and timing verification tools. Strong understanding of DFT architectures. Familiarity with debug tools such as Verdi and workflows for performance analysis. Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl. Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.

Analytical thinker with exceptional problem-solving skills. Effective communicator, able to collaborate across disciplines and with external partners. Proactive, self-motivated, and adaptable in fast-paced environments. Committed to quality, detail, and continuous learning. Team player who values diversity, inclusion, and mentorship. Customer-focused, dedicated to delivering timely and effective solutions.

You'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hsinchu, Taiwan site is home to a vibrant, collaborative team developing cutting-edge solutions for multi-die systems and advanced packaging. Synopsys powers breakthroughs in AI, cloud computing, 5G, IoT, and automotive, delivering industry-leading tools for chip design and software security.

Responsibilities

• Designing, developing, and delivering software solutions for physical layout automation in advanced packaging and multi-die systems.
• Contributing to technical specifications, implementing robust and efficient code, and applying test-driven development practices.
• Debugging and resolving complex issues collaboratively, employing systematic approaches and leveraging your expertise in computational geometry.
• Ensuring software meets strict quality, performance, and reliability standards required by industry-leading customers.
• Supporting product deployment, releases, and troubleshooting customer issues to ensure seamless adoption and satisfaction.
• Collaborating with cross-functional, global teams to deliver innovative EDA solutions that advance Synopsys' technology leadership.
• Continuously learning and integrating new technologies and methodologies to enhance product capabilities and efficiency.

Impact

• Driving innovation in physical design automation for advanced packaging, enabling the creation of high-performance, next-generation silicon chips.
• Empowering leading technology companies to accelerate their chip design cycles and achieve superior outcomes.
• Contributing to Synopsys' reputation as a pioneer in EDA solutions, strengthening our market leadership and customer trust.
• Improving software reliability and performance, directly impacting customer productivity and success.
• Facilitating the adoption of cutting-edge design methodologies and multi-die systems across the semiconductor industry.
• Mentoring and collaborating with global teammates, fostering knowledge sharing and continuous improvement.
• Enhancing the scalability and adaptability of Synopsys tools to meet evolving industry demands.

Requirements

• Master's degree in Computer Science, Electrical Engineering, or a related field.
• 8+ years of professional software development experience, ideally within EDA or physical design/layout automation.
• Strong proficiency in C++ or other object-oriented programming languages, with solid understanding of algorithms and data structures.
• Experience with computational geometry and software development workflows/tools.
• Exceptional debugging skills and systematic problem-solving abilities.
• Proficiency in Linux; scripting experience (e.g., Tcl, Perl, or similar) preferred.
• Strong written and verbal communication skills in English (intermediate or higher).

Who You Are

• Analytical thinker with outstanding attention to detail.
• Quick learner and self-starter, comfortable with ambiguity and change.
• Collaborative team player who thrives in diverse, global environments.
• Effective communicator who can explain complex ideas clearly to technical and non-technical audiences.
• Adaptable and resilient, able to manage multiple priorities and deadlines.
• Driven by curiosity and a passion for continuous improvement.

Team

You'll join Synopsys' EDA Group R&D team, a dynamic, innovative group focused on developing industry-leading solutions for physical layout automation and advanced packaging. Our team collaborates across global locations, sharing expertise and driving technical excellence. We value creativity, initiative, and a commitment to delivering best-in-class software that shapes the future of chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements. As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment. Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions. You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team. Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design engineer with deep expertise in high-speed SERDES IP. You thrive on solving complex circuit challenges, leading technical initiatives, and collaborating across multidisciplinary teams. Your track record in advanced CMOS design, effective communication skills, and passion for innovation make you a trusted mentor and a key contributor to project and team success.

What You’ll Be Doing:

• Develop and specify SERDES transceiver architectures and sub-blocks based on standards.
• Design, simulate, and verify high-speed analog circuits for optimal power and performance.
• Collaborate with analog, digital, and CAD teams to ensure design quality and efficiency.
• Present technical results internally and externally to customers and industry groups.
• Oversee physical layout to address parasitics and reliability concerns.
• Document features and test plans, and support post-silicon analysis and updates.

The Impact You Will Have:

• Advance industry-leading SERDES IP for next-generation SoCs.
• Enhance product differentiation and customer value.
• Streamline design processes for quality and time-to-market.
• Mentor junior team members and share best practices.
• Influence technical direction and innovation at Synopsys.
• Support customer success and product reliability.

What You’ll Need:

• Ph.D. with 6+ years or M.Sc. with 8+ years of analog IC design experience.
• Expertise in transistor-level CMOS design and SERDES sub-circuits.
• Proficiency with schematic, layout, and verification tools; SPICE simulators.
• Experience with scripting languages (Verilog-A, TCL, Python, etc.).
• Strong communication and documentation skills.

Who You Are:

• Technical leader and mentor
• Collaborative and proactive
• Analytical and detail-oriented
• Adaptable and innovative

The Team You’ll Be A Part Of:

A collaborative, high-performing analog and mixed-signal design group focused on developing advanced SERDES IP for leading-edge applications. The core purpose of the team is the development of 224-Gb/s Ethernet SerDes Transceivers for network infrastructure ICs, driving the future of high-speed connectivity in data centers and communications networks for the world.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key Responsibilities:

• Develop emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers.
• Engage in software development using C/C++ and synthesizable RTL development with Verilog.
• Verify solutions to ensure high performance and reliability.
• Interact with customers during the deployment and debug phases to ensure smooth implementation.
• Collaborate with cross-functional teams to integrate emulation solutions.
• Maintain and enhance existing emulation solutions to meet evolving industry standards.

Impact:

• Drive the development of advanced emulation solutions that meet industry standards.
• Enhance the performance and reliability of semiconductor products through innovative solutions.
• Ensure customer satisfaction by providing robust and efficient deployment support.
• Contribute to the continuous improvement of Synopsys' emulation technologies.
• Support the adoption of new protocols and standards in the semiconductor industry.

Requirements:

• 5+ years of relevant experience
• In-depth knowledge of PCIe, CXL, and UCIe protocols.
• Proficiency in C/C++ programming and object-oriented programming concepts.
• Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog.
• Experience with scripting languages like Python, Perl, or TCL.
• Familiarity with ARM architecture and UVM/functional verification is a plus.

Who You Are:

• A collaborative team player with excellent communication skills.
• A problem-solver with a keen eye for detail and a passion for innovation.
• Adaptable and able to work effectively in a fast-paced, dynamic environment.
• Customer-focused, with the ability to handle deployment and debugging challenges efficiently.
• Committed to continuous learning and staying updated with industry advancements.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You have a strong passion for working with embedded processors or processor-based systems.

You bring knowledge of HDL design, with a preference for experience in RISC processor architectures, DSP, AI (Neural Processing Unit), and multi-core systems.

You are familiar with design and verification languages such as Verilog and SystemVerilog, and have experience with RTL simulation tools, such as VCS.

Scripting or programming skills in languages such as assembler, C, Tcl, Csh, and Python is desirable.

Experience with embedded software related to DSP or AI reference models is a plus.

You have strong analytical and problem-solving abilities, as well as excellent written and verbal communication skills, including proficiency in English, detailed status reporting, and the ability to present results to program management teams.

What You’ll Be Doing:

• Develop and maintain microprocessor hardware IP including specification, implementation, verification, and FPGA validation, with an emphasis on validating system architecture and performance for DSP processor IP or Neural Processing Unit (NPU) IP.

• Optimize designs for performance, area, and power efficiency.

• Create and enhance tests for hardware IP verification and validation, improving functional coverage and performance through the application of state-of-the-art methodologies.

• Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.

The Impact You Will Have:

• Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.

• Enable customers to create sophisticated and efficient embedded designs.

• Support the delivery of world-class microprocessors used in advanced applications.

• Help improve functional coverage and performance of processor IP through advanced verification methods.

• Collaborate globally to deliver customer-focused solutions.

• Drive continuous improvement in processor system verification.

What You’ll Need:

• Passion for embedded processors or processor-based systems.

• Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.

• Familiarity with Verilog and SystemVerilog.

• Experience with RTL simulation tools (e.g., VCS).

• Scripting or programming skills in assembler, C, Tcl, Csh, or Python.

• Experience with embedded software for DSP or AI reference models is a plus.

Who You Are:

• Strong analytical and problem-solving abilities.

• Excellent written and verbal communication skills.

• Proficient in English.

• Capable of detailed status reporting and presenting results to program management teams.

The Team You’ll Be A Part Of:

Join our dynamic team dedicated to developing highly optimized hardware IP for the ARC family of configurable processors, enabling customers to create sophisticated and efficient embedded designs.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.

Key responsibilities include: Planning tests, checklists, coverage, and assertion planning. Creating detailed verification environments from functional specifications. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Writing test cases, checkers, and coverage that implement the verification test plan. Debugging simulations, including those of real signals modeled using SystemVerilog for analog. Performing RTL, GLS, and co-simulations and ensuring coverage closure. Participating in technical reviews and contributing actively. Providing customer support with the bring-up of IP in customer simulation environments. Following and improving development processes to ensure high-quality output.

Requirements include: BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 2+ years of experience in design verification. Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Ideal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written. A great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and detail-oriented engineer who thrives in the fast-paced world of advanced semiconductor layout. You possess a deep understanding of analog and mixed-signal CMOS design principles, with a particular focus on high-speed SerDes interfaces. Your expertise is backed by a solid academic foundation and practical experience, enabling you to tackle complex layout challenges with confidence.

What You’ll Be Doing:

• Drive layout development for high-speed SerDes physical interfaces and complex analog/mixed-signal CMOS blocks.

• Lead the complete layout design process, including floorplanning, verification, and quality assurance, with a strong emphasis on reliability and manufacturability.

• Port designs across multiple foundry nodes, ensuring optimal performance and compliance with technology-specific requirements.

• Implement advanced techniques for signal integrity, ESD, and latch-up mitigation, such as differential routing, shielding, and biasing.

• Collaborate closely with design, verification, and manufacturing teams to deliver robust and scalable layout solutions.

• Utilize Synopsys EDA tools and scripting languages (TCL, Python) to automate layout tasks and optimize workflow efficiency.

The Impact You Will Have:

• Enable Synopsys customers to achieve higher performance and reliability in their silicon designs.

• Accelerate the time-to-market for cutting-edge semiconductor products by delivering high-quality, manufacturable layouts.

• Enhance the robustness and scalability of Synopsys IP through meticulous attention to detail and innovative design solutions.

• Drive advancements in deep submicron CMOS technology adoption and integration.

• Foster a collaborative environment that supports knowledge sharing, mentorship, and professional growth.

• Support Synopsys’ leadership in chip design and verification by contributing to the development of industry-leading IP blocks.

What You’ll Need:

• MSc in Electrical/Computer Engineering (or equivalent).

• Minimum 3 years hands-on experience in analog and mixed-signal CMOS layout, including high-speed SerDes interfaces.

• Deep knowledge of deep submicron CMOS technologies and design for reliability (EM/IR, matching, proximity effects).

• Proficiency in layout floorplanning, porting designs across foundry nodes, and implementing signal integrity and ESD mitigation strategies.

• Experience with custom digital and high-speed digital layout, as well as Synopsys EDA tools.

• Strong skills in UNIX environments, including shell scripting and command-line operations.

• Familiarity with scripting languages such as TCL and Python.

Who You Are:

• Excellent problem-solving, organizational, and communication skills.

• Self-motivated and proactive, with the ability to work independently and as part of a team.

• Effective collaborator who values diverse perspectives and fosters inclusive teamwork.

• Adaptable and open to new challenges, with a commitment to continuous improvement.

• Detail-oriented with a strong sense of ownership and pride in delivering high-quality work.

The Team You’ll Be A Part Of:

You will join a dynamic, highly skilled team dedicated to developing world-class analog and mixed-signal IP for Synopsys’ global customer base. The team is focused on pushing the boundaries of high-speed interface design, reliability, and manufacturability, working together to solve complex challenges and deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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As a DFT Applications Engineer, Staff, you will collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements. You will work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.

Responsibilities:

• Collaborate with semiconductor design companies to understand their methodologies, challenges, and requirements.
• Work closely with Account and R&D teams to develop and implement stable, scalable tool solutions tailored to customer needs.
• Gather detailed requirements and provide regular updates on solution progress to internal stakeholders and customers.
• Demonstrate expertise in Design for Testability (DFT), including scan insertion, and deliver impactful presentations to customers.
• Conduct technical demonstrations and training sessions, showcasing the benefits and capabilities of Synopsys solutions.
• Stay abreast of industry advancements, continuously updating your knowledge to ensure best-in-class solutions.
• Contribute to the development of automation and custom scripts to enhance tool functionality and customer productivity.

Impact:

• Enable customers to achieve higher quality and reliability in their semiconductor designs through advanced DFT methodologies.
• Drive customer satisfaction by delivering tailored, scalable, and robust solutions that address unique design challenges.
• Strengthen Synopsys' reputation as a trusted partner in the semiconductor industry by providing expert guidance and support.
• Accelerate adoption of Synopsys tools and technologies, contributing to the company’s growth and market leadership.
• Foster innovation by integrating latest industry trends and methodologies into customer solutions.
• Promote cross-team collaboration, ensuring seamless communication and alignment between Account, R&D, and customer teams.
• Support diversity and inclusion initiatives by contributing your unique perspective and fostering a welcoming work environment.

Requirements:

• Master’s degree (M.Tech or equivalent) in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant experience in semiconductor design or related areas.
• Strong understanding of VLSI and Design for Testability (DFT) concepts and methodologies.
• In-depth knowledge and practical experience with DFT scan insertion.
• Familiarity with semiconductor design tools and scripting languages (TCL, Python, Perl) for automation and customization.
• Excellent communication and presentation skills, with a proven ability to interact effectively with customers and internal teams.
• Ability to work collaboratively in a cross-functional team environment.
• Strong problem-solving skills and adaptability in a fast-paced, dynamic setting.

Who You Are:

• Innovative thinker with a customer-centric approach.
• Collaborative and open-minded team player.
• Proactive learner, eager to stay ahead of industry trends.
• Effective communicator, able to simplify complex technical topics.
• Resilient and adaptable, thriving in dynamic environments.
• Committed to diversity, inclusion, and fostering a supportive workplace.

The Team You’ll Be A Part Of:

You’ll join a dedicated engineering team in Bangalore focused on delivering advanced solutions to semiconductor design companies. Our team values collaboration, innovation, and continuous learning, working closely with Account and R&D departments to ensure customer success. We foster a supportive environment where every member’s expertise and perspective contribute to our shared goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are looking for a passionate, detail-oriented engineer with an insatiable curiosity for technology and its impact on the world. You will thrive in collaborative environments, bringing together diverse perspectives to solve complex challenges. With a strong foundation in RTL design and verification, you will approach every project with a sense of ownership and a commitment to excellence.

As an effective communicator, you will clearly articulate technical concepts to both internal teams and external customers, fostering strong partnerships and driving innovation. You will be adaptable, self-motivated, and resilient in the face of challenges, always seeking opportunities to learn and grow.

Your responsibilities will include designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance. You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.

You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

The impact you will have includes accelerating the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions. You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy.

You will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will have 5+ years of hands-on experience in RTL design and verification. You will be proficient in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.

You will be an analytical and critical thinker with a detail-oriented approach. You will be an effective communicator, comfortable collaborating across teams and with customers. You will be self-motivated and proactive in seeking solutions and driving projects forward.

You will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.

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As a Staff ASIC Digital Design Engineer, you will be part of our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. You will work with experts in design, implementation, and verification.

Key responsibilities include:

Creating and debugging test benches and test cases Running RTL and gate-level simulations Supporting application engineers and customers on HBM/DDR PHY topics Contributing to technical documentation Driving product improvements based on customer feedback

The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

ASIC RTL design and verification experience Verilog, PERL, TCL, Python skills Static timing analysis and synthesis knowledge Simulation and debugging abilities HBM/DDR protocol experience is an asset

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and perks during the hiring process.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.

With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.

Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.

You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.

Responsibilities

• Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.

• Define synthesis constraints and resolve STA and gate-level simulation issues.

• Collaborate with verification, controller, and lab teams for design and debugging.

• Support RTL to GDS flow during logic implementation.

• Lead projects and train junior engineers.

• Work with customers to resolve technical RTL issues.

The Impact You Will Have

• Deliver robust RTL designs for advanced silicon solutions.

• Drive successful project completion and tape-outs.

• Enhance design quality and verification efficiency.

• Support customer success and strengthen Synopsys’ reputation.

• Mentor and grow engineering talent within the team.

• Contribute to digital flow improvements and innovation.

What You’ll Need

• BS/MS/PhD in Electronics Engineering or Telecommunications.

• 5+ years of RTL design experience for ASIC or PHY IP.

• Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).

• Knowledge of clock domain crossing, APB, JTAG protocols.

• Strong English communication skills.

Who You Are

• Responsible, result-oriented, and self-motivated.

• Collaborative and proactive problem solver.

• Effective communicator and mentor.

The Team You’ll Be A Part Of

Join a collaborative engineering team delivering innovative PHY IP solutions.

Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about salary and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We are seeking an experienced SerDes Analog Behavioral Modeling & Validation Engineer to join our team.

As a key member of our engineering team, you will be responsible for developing and refining behavioral models for high-speed SerDes blocks, collaborating with analog teams for SPICE-vs-model correlation and sign-off, and working with digital verification teams on edge-case coverage.

Responsibilities

• Collaborate with analog teams for SPICE-vs-model correlation and sign-off.
• Develop and refine behavioral models for high-speed SerDes blocks.
• Capture calibration, adaptation, and impairments in models.
• Work with digital verification teams on edge-case coverage.
• Automate comparison flows and improve model fidelity.
• Embed realistic non-idealities and verify behavioral netlists.

Impact

• Deliver high-trust models, reducing mixed-signal bugs.
• Enable realistic digital verification and improve coverage.
• Strengthen Synopsys' reputation for robust connectivity IP.
• Catch issues early and accelerate debug cycles.
• Foster collaboration between analog, modeling, and DV teams.

Requirements

• BSc, MSc, or PhD in Electrical/Computer Engineering with 5+ years experience.
• Expertise in SerDes analog blocks and modeling impairments.
• Fluency with SPICE tools and waveform analysis.
• Strong scripting/programming in Python, TCL, Perl, C/C++.
• Experience automating comparisons and reporting.

Team

You'll join a multidisciplinary group focused on modeling, validation, and verification of high-speed SerDes IP,bridging analog and digital domains for industry-leading solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Accelerate the adoption of industry-leading formal verification solutions, enabling customers to achieve robust, high-quality silicon designs. Strengthen Synopsys' reputation as a trusted partner for verification innovation and excellence. Drive customer success by delivering tailored consulting services and assertion IPs that address complex verification challenges. Enhance productivity and efficiency for customers through advanced formal methodologies and flows. Influence the direction of formal verification technology by collaborating with R&D and Product Management teams. Foster a culture of technical excellence and inclusion within your team, empowering members to grow and contribute meaningfully. Enable strategic customers to meet critical industry requirements such as design security, automotive safety, and verification signoff.

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Your primary focus will be on analyzing automated test execution results, investigating anomalies, and reporting detailed issues for resolution. You will also ensure zero functional regression across product releases by executing comprehensive regression testing suites.

In addition, you will contribute to the creation and enhancement of detailed test plans for new product features and updates, collaborate closely with Development teams to support troubleshooting and effective root-cause analysis, and uphold Synopsys' high standards for product quality and long-term reliability through proactive quality initiatives.

As a member of our team, you will participate in code reviews and provide feedback on testability and quality improvements. You will deliver high-quality, reliable software that powers cutting-edge technologies in AI, 5G, and autonomous systems, ensuring seamless user experiences for our global customer base, including leading semiconductor and tech companies.

To succeed in this role, you will need a Bachelor's or Master's degree in Electronics Engineering / Semiconductor Engineering or a related field, with a minimum of 6 years of experience in industry or 5 years of industry experience with a Master's degree in a related field.

You will be proficient in scripting in shell, python, tcl, and have experience in EDA tools and AI systems. You will also be able to work in a fast-paced development cycle, autonomously and proactively manage quality and defect tracking, and have solid analytical and troubleshooting skills, especially in complex systems.

If you are a detail-oriented and analytical individual with a rigorous approach to problem-solving, a collaborative and communicative team player with strong written and verbal communication skills in English, we encourage you to apply for this exciting opportunity.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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OPC Applications Engineer, Staff

Hsinchu, Taiwan

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Category: EngineeringHire Type: Employee

Job ID 16166Date posted 03/30/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled engineer with a passion for enabling customer success in advanced semiconductor manufacturing. Your expertise in photolithography, optical proximity correction (OPC), and scripting allows you to bridge technical and customer-facing roles with ease. You thrive in collaborative environments, consistently seeking out opportunities to add value through proactive technical support, consultation, and training. Your background includes hands-on experience with lithography rule checks, patterning applications, and fab lithography processes, empowering you to drive project outcomes and foster strong relationships across diverse customer bases in Japan and Asia.

As a proactive communicator, you enjoy sharing your knowledge, whether through publishing technical papers or presenting at industry conferences. Your honesty and teamwork make you a trusted partner, and you are adept at balancing multiple projects with an organized, detail-oriented approach. You embrace working in a global, multicultural environment and are eager to join a team where your technical skills and customer-first mindset will make a tangible impact. Your motivation lies in delivering innovative solutions, contributing to industry advancements, and ensuring both Synopsys and its customers achieve exceptional results.

What You’ll Be Doing:

• Supporting advanced photolithography process Mask Synthesis tools, including script development, implementation, and recipe/model creation (OPC, AF, Verification, etc.).

• Providing proactive technical support and consultancy services to customers, ensuring successful project outcomes.

• Delivering customer-specific technical trainings to enhance user knowledge and adoption of Synopsys solutions.

• Collaborating with external customers on joint projects, driving technical success.

• Maintaining regular, intensive contact with customers to address technical challenges and provide ongoing support.

• Interacting closely with internal global teams,including software R&D and product development,to achieve technical goals and ensure seamless solution delivery.

The Impact You Will Have:

• Empowering customers to achieve optimal results in semiconductor manufacturing through advanced OPC and mask synthesis solutions.

• Accelerating adoption and maximizing utilization of Synopsys S-Litho Sentaurus Lithography and Proteus products.

• Enhancing customer satisfaction and loyalty by delivering exceptional technical support and consultation.

• Contributing to industry knowledge through publication of technical papers and participation in conferences.

• Strengthening Synopsys' reputation as a leader in photolithography and semiconductor process innovation.

• Driving cross-team collaboration to refine and advance product capabilities based on real-world customer feedback.

What You’ll Need:

• Strong scripting skills in Python, Tcl, or other high-level languages, and proficiency with Linux operating systems.

• MS degree in a relevant field and 3+ years of experience in OPC, lithography rule check, patterning applications, or fab lithography processes.

• English-based communication at an engineering level with global customers and employees is required.

• Experience collaborating with teams to achieve project goals and technical milestones.

• Ability to deliver effective customer trainings and support, with a consultative mindset.

Who You Are:

• Excellent team player, committed to honest and effective communication.

• Strong interpersonal skills and relationship-building capabilities.

• Proactive problem-solver with a customer-first attitude.

• Detail-oriented, organized, and able to manage multiple projects simultaneously.

• Comfortable working in a global, multicultural environment.

The Team You’ll Be A Part Of:

You’ll join our dynamic OPC team,a group of passionate professionals dedicated to supporting customer success in advanced photolithography and mask synthesis. The team collaborates closely with global R&D and product development groups, driving innovation and excellence in semiconductor manufacturing solutions. Together, we work to empower customers, share expertise, and advance the industry through continuous learning and technological progress.

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As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.

You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.

You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.

You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.

You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.

You will mentor junior engineers and contribute to team knowledge sharing initiatives.

Impact

You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.

You will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.

You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.

You will facilitate seamless cross-site collaboration, ensuring global project success.

You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.

You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.

3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).

Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.

Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.

Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.

Strong analytical and debugging skills for addressing complex design challenges.

Team

You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.

The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.

Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Applications Engineering, Staff Engineer (OPC)

Hsinchu, Taiwan

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Category: EngineeringHire Type: Employee

Job ID 15261Date posted 03/01/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled engineer with a passion for enabling customer success in advanced semiconductor manufacturing. Your expertise in photolithography, optical proximity correction (OPC), and scripting allows you to bridge technical and customer-facing roles with ease. You thrive in collaborative environments, consistently seeking out opportunities to add value through proactive technical support, consultation, and training. Your background includes hands-on experience with lithography rule checks, patterning applications, and fab lithography processes, empowering you to drive project outcomes and foster strong relationships across diverse customer bases in Japan and Asia.

As a proactive communicator, you enjoy sharing your knowledge, whether through publishing technical papers or presenting at industry conferences. Your honesty and teamwork make you a trusted partner, and you are adept at balancing multiple projects with an organized, detail-oriented approach. You embrace working in a global, multicultural environment and are eager to join a team where your technical skills and customer-first mindset will make a tangible impact. Your motivation lies in delivering innovative solutions, contributing to industry advancements, and ensuring both Synopsys and its customers achieve exceptional results.

What You’ll Be Doing:

• Supporting advanced photolithography process Mask Synthesis tools, including script development, implementation, and recipe/model creation (OPC, AF, Verification, etc.).

• Providing proactive technical support and consultancy services to customers, ensuring successful project outcomes.

• Delivering customer-specific technical trainings to enhance user knowledge and adoption of Synopsys solutions.

• Collaborating with external customers on joint projects, driving technical success.

• Maintaining regular, intensive contact with customers to address technical challenges and provide ongoing support.

• Interacting closely with internal global teams,including software R&D and product development,to achieve technical goals and ensure seamless solution delivery.

The Impact You Will Have:

• Empowering customers to achieve optimal results in semiconductor manufacturing through advanced OPC and mask synthesis solutions.

• Accelerating adoption and maximizing utilization of Synopsys S-Litho Sentaurus Lithography and Proteus products.

• Enhancing customer satisfaction and loyalty by delivering exceptional technical support and consultation.

• Contributing to industry knowledge through publication of technical papers and participation in conferences.

• Strengthening Synopsys' reputation as a leader in photolithography and semiconductor process innovation.

• Driving cross-team collaboration to refine and advance product capabilities based on real-world customer feedback.

What You’ll Need:

• Strong scripting skills in Python, Tcl, or other high-level languages, and proficiency with Linux operating systems.

• MS degree in a relevant field and 3+ years of experience in OPC, lithography rule check, patterning applications, or fab lithography processes.

• Fluent in Japanese is advantageous; however, English-based communication at an engineering level with global customers and employees is required.

• Experience collaborating with teams to achieve project goals and technical milestones.

• Ability to deliver effective customer trainings and support, with a consultative mindset.

Who You Are:

• Excellent team player, committed to honest and effective communication.

• Strong interpersonal skills and relationship-building capabilities.

• Proactive problem-solver with a customer-first attitude.

• Detail-oriented, organized, and able to manage multiple projects simultaneously.

• Comfortable working in a global, multicultural environment.

The Team You’ll Be A Part Of:

You’ll join our dynamic OPC team,a group of passionate professionals dedicated to supporting customer success in advanced photolithography and mask synthesis. The team collaborates closely with global R&D and product development groups, driving innovation and excellence in semiconductor manufacturing solutions. Together, we work to empower customers, share expertise, and advance the industry through continuous learning and technological progress.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include designing and analysing algorithms for end-to-end timing constraint management, driving the success and evolution of Synopsys' constraint flow and tools, collaborating within a highly skilled engineering team to deliver innovative solutions for static timing analysis (STA) during design and optimisation, and designing, developing, troubleshooting, and debugging advanced software programs for constraint generation and verification.

The ideal candidate will have a B.Tech/M.Tech in Computer Science or Electrical Engineering from a reputed institute, 8 years of experience with strong foundational knowledge of programming fundamentals, including data structures, sorting, searching algorithms, and numerical methods, ability to read and analyse code in C/C++, exceptional debugging skills and proficiency in scripting languages (such as Python, Perl, or TCL), demonstrated analytical and problem-solving skills, with a keen attention to detail, independent judgment in selecting methods and techniques to obtain technical solutions, experience with Synopsys Static Timing Analysis (STA) tools and EDA tool/CAD flow development (preferred), and experience with Synopsys Design Constraints (SDC) is a strong plus.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. The total rewards include both monetary and non-monetary offerings.

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You are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly.

Supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality. Applying extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption. Interacting with other Synopsys R&D members and customers to understand their needs and product goals. Contributing to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules. Exercising judgment in developing methods, techniques, and evaluation criteria to meet project goals. Collaborating with a team of enthusiastic and creative engineers to drive innovation and excellence.

Enhancing the performance and quality of our verification tools, leading to increased customer satisfaction and adoption. Driving continuous improvement in software development processes and practices. Contributing to the development of cutting-edge technologies that power innovations in various industries. Helping Synopsys maintain its leadership position in the market by delivering high-performance solutions. Influencing the direction and success of our hardware verification tools through your expertise and innovation. Fostering a collaborative and innovative work environment that encourages growth and learning.

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Collaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).

Utilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.

Implementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...

Developing SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.

Applying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.

Ensuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.

Designing custom digital logic cell layouts and associated logic path routing for mixed-signal integration.

Refining layouts to minimize parasitic effects and enhance matching, reliability, and performance.

Delivering high-quality IP that powers next-generation semiconductor products for global customers.

Enabling Synopsys to maintain leadership in advanced technology node design and IP development.

Contributing to the creation of reliable, high-performance silicon chips used in communications.

Driving innovation in analog and mixed-signal layout methodologies and tools.

Enhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.

Ensuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.

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As a Staff Software Engineer, you will be responsible for supporting the existing functionality of our tools and continually enhancing their versatility, performance, and memory utilization while improving software quality.

You will apply extensive knowledge of algorithms and data structure design to develop robust and efficient implementations that improve tool performance and customer adoption.

You will interact with other Synopsys R&D members and customers to understand their needs and product goals.

You will contribute to the development of complex software code-based tools in a multi-person product development environment with high dependencies and tight schedules.

You will exercise judgment in developing methods, techniques, and evaluation criteria to meet project goals.

You will collaborate with a team of enthusiastic and creative engineers to drive innovation and excellence.

The impact you will have includes enhancing the performance and quality of our verification tools, driving continuous improvement in software development processes and practices, contributing to the development of cutting-edge technologies, helping Synopsys maintain its leadership position in the market, influencing the direction and success of our hardware verification tools, and fostering a collaborative and innovative work environment.

Key responsibilities include supporting existing tool functionality, applying knowledge of algorithms and data structures, interacting with R&D members and customers, contributing to complex software development, exercising judgment in method development, and collaborating with a team of engineers.

Key qualifications include a Bachelor's degree in Electrical/Electronics/Computer-Science Engineering with a minimum of 5 years of related experience, or a Master's degree with 3 years of relevant experience, in-depth understanding of data structures, algorithms, and their applications, excellent software development experience with C/C++ on UNIX/Linux platforms, exposure to Python, TCL, and shell scripting languages, and demonstrated history of good analytical, debugging, and problem-solving skills.

You will join the Hardware Assisted Verification team at Synopsys, a group of dedicated and innovative engineers focused on developing and enhancing our verification tools.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Key responsibilities include:

• Strong problem-solving skills and the ability to debug complex software issues in large-scale systems.
• 2–5 years of industry experience in software development or EDA-related R&D roles.
• Ability to contribute independently to feature development, bug fixes, and performance improvements.
• Good communication skills and the ability to collaborate effectively within a cross-functional team.

Ideal candidates will have proficiency in C/C++ development, with strong fundamentals in data structures and algorithms. Experience working on Linux platforms and familiarity with build systems, debugging tools, and development workflows on Linux is a plus. Exposure to scripting languages such as Tcl, Perl, or Python will be an added advantage.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

13752

Remote Eligible

No

Date Posted

12/16/2025

Responsibilities

• Reviewing Die, package, and PCB physical layout designs
• Modelling, simulating, and verifying high-speed interface performance against specifications
• Participating in the improvement of SI/PI methodology flows
• Collaborating and networking with other teams on task-oriented projects
• Independently driving SI/PI research and development activities

Impact

• Enabling SI/PI sign-off of high-speed interfaces for various Customer SoC/PKG/PCB designs targetting different applications
• Improve SI/PI methodology flows, increasing efficiency and accuracy
• Foster collaboration and innovation across globally distributed teams
• Drive research and development initiatives of next gen IP's (MRDIMM, LPDDR6, HBM4, UCIE) to stay ahead in the industry and offer guidance to our customers
• Support Synopsys' mission to lead in the Era of Pervasive Intelligence

Requirements

• Bachelor's or Master's degree in Electrical or Electronics Engineering
• Minimum of 8 years of relevant experience
• Proficient in Transmission line theory and time/frequency-domain analysis
• Experienced with SPICE and familiar with 3D field solvers
• Conversant with working of DDR, HBM, UCIE and PCIe/Ethernet interfaces
• Good verbal and written English communication skills
• Experience in scripting languages such as Python and TCL is a plus
• Familiarity with both Windows and Linux operating systems

Who You Are

You are a proactive and innovative engineer who thrives in a collaborative environment. You have a strong technical background and excellent problem-solving skills. Your ability to communicate effectively and work well with diverse teams makes you an asset to any project. You are dedicated to continuous learning and development, and your passion for technology drives you to stay ahead of industry trends. You are adaptable, detail-oriented, and committed to delivering high-quality results.

Team

You will be working with a group of highly-skilled, supportive, and globally spread-out teams. Our team is dedicated to driving innovation and excellence in SIPI analysis of high speed interface IP's. We value collaboration, continuous learning, and a can-do attitude. Together, we strive to develop the most advanced technologies and deliver exceptional results for our clients.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.

With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.

You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.

Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.

As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.

Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.

You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.

Work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As a Failure Analysis Engineer, you will be responsible for diagnosing and analyzing functional failures in highly complex electronic assemblies throughout the product lifecycle. You will provide expert technical support to Contract Manufacturers during production and test phases, ensuring rapid resolution of manufacturing-related failures.

Key responsibilities:

• Diagnose and analyze functional failures in highly complex electronic assemblies
• Provide expert technical support to Contract Manufacturers during production and test phases
• Collaborate closely with R&D teams to root-cause prototype and pre-production issues
• Perform hands-on failure analysis, including hardware manipulation, measurement, mounting/demounting, and rework of assemblies
• Utilize laboratory equipment (oscilloscopes, multimeters, logic analyzers, power supplies) to characterize failures and confirm hypotheses
• Leverage Linux-based environments and develop/maintain Tcl scripts to automate tests, extract data, reproduce failures, and support diagnostics
• Document analysis results, root causes, and corrective actions clearly and thoroughly
• Interface with cross-functional teams (Engineering, Manufacturing, Quality, Field Service) to drive timely and aligned issue resolution
• Identify recurring failure patterns and propose continuous improvements to design, process, or test methodologies
• Ensure compliance with internal procedures, quality requirements, and relevant industrial standards

Requirements:

• Engineering degree in Electronics (mandatory)
• Minimum 5 years of experience in failure analysis, hardware debugging, electronics design, manufacturing support, or related technical role
• Deep expertise in complex electronic assemblies, including mixed-signal, digital, analog, and power electronics
• Strong system-level understanding of mechanical integration, power management, and thermal impacts on electronics reliability
• Hands-on proficiency with laboratory equipment (oscilloscopes, multimeters, logic analyzers, power supplies)
• Solid experience working in Linux environments for analysis, data extraction, and debugging
• Proven ability to develop and deploy Tcl scripts for test automation and diagnostics
• Fluency in both French and English (spoken and written); German language skills are a plus

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Competitive salary Required Skills: Failure analysis, electronics design, manufacturing support, Linux, Tcl scripting, oscilloscopes, multimeters, logic analyzers, power supplies Preferred Skills: German language skills, experience with complex electronic assemblies, system-level understanding of mechanical integration, power management, and thermal impacts on electronics reliability

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Staff Engineer, Application Engineering (AE), you will work on latest Synopsys implementation technologies (AI-ML Implementation, Physical Synthesis RTL-GDS, Multi Source CTS, Indesign Fusion technologies etc.) to solve complex PPA challenges Synopsys customers face.

Responsibilities:

• Work on developing and debugging RTL-GDS implementation methodologies and flows.
• Provide technical solutions by identifying the design and/or EDA tool issues and providing appropriate solutions for customers.
• Effectively translate the findings into requirements for R&D to improve both tool behaviors with enhancements as adaptive long-term solutions.
• Involved in the deployment of new technologies on the latest EDA versions and enabling customers to migrate to newer versions achieving the best PPA.
• Come up with proactive knowledge of customers' pain point and come up with innovative solutions to address the same.
• Closely interacting with Synopsys R&D team and product development team to develop future technologies.

Requirements:

• At least 5+ years of experience in Physical Implementation RTL-GDS.
• Candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs.
• Proficiency in Synopsys implementation tools is an advantage.
• The person must be self-motivated and dedicated with excellent debug skills.
• Requires proficiency in scripting (tcl / unix / perl).
• Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

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Role Details:

Responsibilities:

• Develop physical design methodologies for rail analysis and signoff.
• Come up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
• Craft workflows and tool methodologies for power and noise analysis across multiple projects.

Requirements:

• Master's degree or equivalent experience in Electrical Engineering or related field.
• Minimum 5+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiar with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff
• Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

Ways to Stand Out:

• Experience in crafting custom workflows from scratch.
• Adaptability and problem-solving skills: Ability to thrive in a dynamic, fast-paced environment where quick thinking and creative solutions are often required.
• Experience using AI tools to improve capabilities in the power integrity domain, such as automating analysis and improving tool/flow features

You will also be eligible for equity and benefits.

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You are an exceptional C++ developer with a background in or a keen interest in Custom Design and Layout in the field of Integrated Circuits. With a passion for solving complex problems, you thrive in a collaborative environment and are eager to contribute to the development of cutting-edge software solutions.

Responsibilities

• Designing new solutions to high-value problems in Custom Design and Layout areas, including new layout methodologies and applications of analytics and machine learning in layout.
• Collaborating on flagship layout automation projects maintained by local peers.
• Improving existing systems and providing solutions in Synopsys Custom products.
• Working with corporate application engineers to understand customer needs and provide tailored solutions.
• Writing well-designed, well-tested, high-quality C++ programs.
• Creating design specifications and reviewing code written by peer members.

Impact

• Driving innovation in Custom Design and Layout solutions, addressing underserved areas and creating new methodologies.
• Enhancing the efficiency and effectiveness of layout automation tools, benefiting both internal and external stakeholders.
• Improving the performance and reliability of Synopsys Custom products, contributing to the overall success of the company.
• Ensuring high-quality software development practices, leading to robust and maintainable codebases.
• Providing critical insights and solutions that meet the evolving needs of our customers.
• Contributing to the development of advanced silicon analog and mixed-signal designs, optimizing for power, cost, and performance.

Requirements

• Bachelor's or Master's Degree in Computer Science or Electrical Engineering.
• 12+ years of experience in software development, including C++, TCL, Python, Linux, build and revision control systems, and specification writing/reviewing.
• Expertise in software design, including data structures, algorithms, GUI and interactive systems, and event-driven systems.
• Background in Layout Editor and its automation engines for Analog Design is highly desirable.
• Knowledge of digital EDA tools and flows, circuit analysis, layout principles, and semiconductor manufacturing.

Team

You will be part of the Custom Design & Manufacturing business unit, which focuses on building software solutions for custom design, analog, and mixed-signal design. Our team collaborates closely with the signoff extraction, verification, and simulation teams to develop differentiated solutions for designing and verifying advanced silicon analog and mixed-signal designs. We work together to design the next-generation processes and models needed to manufacture these chips, enabling our customers to optimize their designs for power, cost, and performance.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Health & Wellness: Comprehensive medical and healthcare plans that work for you and your family.
• Time Away: In addition to company holidays, we have ETO and FTO Programs.
• Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Retirement Plans: Save for your future with our retirement plans that vary by region and country.
• Compensation: Competitive salaries.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15411

Remote Eligible

No

Date Posted

02/23/2026

Alternate Job Titles:

• Staff Applications Engineer, Digital Implementation

• Staff AE – RTL-to-GDS Solutions

• Senior Digital Design Flow Engineer

• Customer Success Engineer – Physical Design

• Staff Field Applications Engineer – EDA

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.

You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.

You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.

What You’ll Be Doing:

• Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.

• Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.

• Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.

• Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.

• Collaborate with global Applications Engineering, R&D, and Product Management teams to enhance methodologies and influence tool development.

• Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.

• Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.

The Impact You Will Have:

• Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.

• Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.

• Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.

• Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.

• Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.

• Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.

• Champion best practices and knowledge sharing within the Applications Engineering community.

What You’ll Need:

• Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).

• Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.

• Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.

• Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.

• Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.

Who You Are:

• Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.

• Exceptional communicator, comfortable engaging with both internal teams and external partners.

• Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.

• Collaborative team player, eager to share knowledge and learn from others.

• Customer-focused, energetic, and adaptable to fast-paced, evolving environments.

The Team You’ll Be A Part Of:

You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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We are seeking a proactive, results-driven leader with a deep technical background in physical design and processor implementation. Your expertise is grounded in architecting high-performance, energy-efficient silicon solutions, and you thrive in fast-paced, collaborative environments. You possess a strong sense of ownership and are comfortable navigating ambiguity to deliver innovative solutions to complex engineering challenges.

As an Applications Engineering Architect (PPA), you will be responsible for architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems, targeting aggressive power and performance goals for diverse end-user applications. You will develop and refine advanced EDA tools and design methodologies to support state-of-the-art processor implementations.

Key Responsibilities:

• Architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems
• Developing and refining advanced EDA tools and design methodologies
• Collaborating closely with key Synopsys customers to guide their development of processor-based platforms in advanced silicon technologies
• Partnering with Synopsys R&D and marketing teams to influence and define future product roadmaps and features
• Working in synergy with leading IP partners to ensure seamless integration of EDA tools, methodologies, and IP

Requirements:

• Proven expertise in physical design and implementation of high-performance processors, SoCs, or processor-based subsystems
• In-depth experience with advanced EDA tools, flows, and methodologies for digital implementation
• Strong knowledge of silicon technologies at advanced nodes and associated design challenges
• Hands-on experience integrating IP and collaborating with IP vendors for seamless tool and methodology interoperability
• Track record of working directly with customers, understanding their requirements, and delivering tailored solutions

We offer a comprehensive range of health, wellness, and financial benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off. We also provide opportunities for professional growth and development, including training and education programs, mentorship, and career advancement opportunities.

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.

You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.

You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.

You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.

The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.

You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys' reputation as a trusted partner and thought leader in the semiconductor industry.

What You'll Need:

• B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.
• Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).
• Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place & Route, and timing analysis.
• Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.
• Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.
• Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.
• Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.

Who You Are:

• Excellent communicator able to build trust and rapport with diverse stakeholders.
• Analytical thinker with strong troubleshooting and debugging skills.
• Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.
• Highly collaborative team player who thrives in fast-paced, multicultural environments.
• Self-motivated, innovative, and passionate about continuous learning and process improvement.
• Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.

The Team You’ll Be A Part Of:

You will join a dynamic, expert team within the Silicon Design & Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&D, and field teams to deliver transformative solutions and advance industry-leading technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk.

You Are:

You are a talented Firmware Development Engineer with a passion for embedded systems and software innovation. You thrive in environments where high-speed and precision matter, bringing a strong programming background and an aptitude for developing reliable, scalable firmware solutions. Your expertise in C programming and familiarity with scripting languages such as Perl, TCL, or Python make you a versatile contributor. You are experienced in developing firmware for complex embedded systems and high-speed interfaces, and you take pride in rigorous problem-solving and debugging. You enjoy collaborating with hardware engineers to ensure seamless integration between firmware and hardware, and you are skilled at navigating verification and emulation environments to enhance product quality. Your attention to detail and commitment to delivering robust, high-quality firmware are matched by your ability to adapt to new challenges in a fast-moving industry. You value diversity and inclusion, and you are comfortable working in a dynamic, multicultural team. Whether you are mentoring junior engineers, spearheading integration efforts, or contributing to pre-silicon environments, you consistently demonstrate initiative, innovation, and a collaborative spirit. If you are excited to power the Era of Smart Everything and help shape tomorrow’s breakthroughs, you’ll find your place at Synopsys.

What You’ll Be Doing:

• Designing and implementing firmware for high-speed PHY IPs using C programming.
• Developing and maintaining software development environments and tools to streamline workflows.
• Collaborating with hardware engineers to ensure firmware compatibility and optimized integration with hardware designs.
• Conducting rigorous unit testing and debugging to ensure high-quality firmware performance
• Utilizing verification and emulation environments to enhance the integration process and support pre-silicon development.
• Documenting design processes, maintaining code quality, and ensuring compliance with industry standards.
• Staying current with emerging technologies in embedded systems and high-speed interfaces.

The Impact You Will Have:

• Accelerating the integration of advanced capabilities into SoCs through robust firmware development.
• Enhancing product reliability, performance, and time-to-market for customers in diverse industries.
• Supporting the development of differentiated products that power innovations like AI, 5G, IoT, and self-driving cars.
• Reducing risk and optimizing project outcomes by leveraging your expertise in embedded systems and high-speed interfaces.
• Driving cross-functional collaboration between software and hardware teams to deliver seamless solutions.
• Contributing to Synopsys’ leadership in silicon IP and embedded technology by delivering high-quality, scalable firmware.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Strong programming skills in C and familiarity with software development methodologies.
• Experience with scripting languages such as Perl, TCL, or Python.
• Proven experience in firmware development for complex embedded systems or high-speed interfaces.
• Excellent problem-solving and debugging skills, especially in unit testing and integration scenarios.
• Knowledge of high-speed interface protocols such as DDR, LPDDR (preferred).
• Experience with pre-silicon environments, including verification or emulation (preferred).

Who You Are:

• Analytical, detail-oriented, and committed to delivering high-quality results.
• Collaborative and effective communicator, able to work across diverse teams and disciplines.
• Adaptable and eager to learn new technologies and methodologies.
• Proactive, with a passion for innovation and continuous improvement.
• Inclusive and respectful, supporting a diverse and multicultural work environment.

The Team You’ll Be A Part Of:

You will join a vibrant Silicon IP engineering team dedicated to developing and integrating advanced firmware for high-speed interfaces. The team consists of experts in embedded systems, software, and hardware design, working together to solve complex challenges and deliver industry-leading solutions. Collaboration, innovation, and a commitment to excellence define the team’s culture as they support customers in bringing differentiated products to market quickly and efficiently.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.

Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.

Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.

Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.

You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 02/24/2026

Category EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.

What You’ll Be Doing:

• Developing robust functional verification environments (test benches) for high-speed PHY IPs.
• Creating comprehensive test plans and detailed test cases to ensure thorough coverage.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Executing simulations, generating both random and focused stimuli, and performing coverage analysis to validate design functionality.
• Building architectural and micro-architectural understanding of complex digital design blocks under verification.
• Collaborating with cross-functional engineering teams to resolve issues and optimize verification strategies.
• Contributing to process improvements and sharing best practices within the team.

The Impact You Will Have:

• Accelerate the integration of advanced capabilities into SoCs, enabling customers to meet performance, power, and size requirements.
• Ensure the delivery of differentiated, high-quality silicon IP products with reduced risk and faster time-to-market.
• Drive innovation in verification methodologies that support the development of next-generation technologies, including AI, cloud, 5G, and IoT.
• Enhance the reliability and functionality of high-speed digital interfaces, powering smart devices across industries.
• Support Synopsys’ leadership in chip design and software security by maintaining rigorous verification standards.
• Contribute to a culture of inclusion and excellence, mentoring junior engineers and promoting diversity within the team.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Solid background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Experience with industry-standard development and verification tools and methodologies.
• Excellent diagnostic and problem-solving skills for identifying and resolving verification issues.
• Preferred: Experience with formal verification, System Verilog Assertions, and code/functional coverage implementation and analysis.
• Preferred: Familiarity with scripting languages such as Perl, TCL, and Shell scripting.
• Preferred: Knowledge of high-speed interface protocols such as DDR and LPDDR.

Who You Are:

• Detail-oriented and analytical thinker with a proactive approach to problem-solving.
• Effective communicator who thrives in collaborative and diverse team environments.
• Adaptable and eager to learn new technologies and methodologies.
• Resourceful and resilient in overcoming technical challenges.
• Committed to fostering inclusion, respect, and continuous improvement within the workplace.

The Team You’ll Be A Part Of:

You will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

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Workplace Resources, Sr Director

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Senior Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.

What You’ll Be Doing:

• Developing functional verification environments (test benches) for complex digital design blocks.
• Creating comprehensive test plans and test cases to ensure thorough coverage and robust design validation.
• Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs).
• Performing simulations, generating random and focused stimulus, and conducting coverage analysis to verify functionality.
• Building architecture and micro-architecture knowledge of digital blocks under test to drive effective verification strategies.
• Collaborating with cross-functional teams to share insights and resolve issues throughout the pre-silicon verification process.
• Utilizing industry-standard verification tools and methodologies to enhance efficiency and quality.

The Impact You Will Have:

• Ensuring the reliability and performance of high-speed PHY IPs through rigorous pre-silicon functional verification.
• Accelerating product time-to-market by identifying and resolving design issues early in the development cycle.
• Reducing risk for customers by delivering thoroughly verified and differentiated silicon IP solutions.
• Supporting the development of next-generation products that power innovations in AI, 5G, IoT, and more.
• Contributing technical expertise to the team, fostering a culture of continuous improvement and learning.
• Promoting collaboration and knowledge sharing across engineering teams to achieve collective goals.

What You’ll Need:

• Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years.
• Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs.
• Proficiency in Verilog, System Verilog, UVM, and netlist simulations.
• Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows.
• Experience with industry-standard development and verification tools and methodologies.
• Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred).
• Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred).
• Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred).

Who You Are:

• Analytical thinker with a strong eagerness to learn and grow.
• Dynamic personality, energizing and motivating team members.
• Strong communicator, able to collaborate effectively in diverse environments.
• Self-motivated leader, capable of driving verification activities independently and as part of a team.
• Detail-oriented, ensuring thorough validation and quality in all deliverables.

The Team You’ll Be A Part Of:

You will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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The impact you will have is accelerating time-to-market for Synopsys customers through robust, automated design flows. You will elevate the quality, reliability, and scalability of EDA methodologies and toolchains across multiple projects and technology nodes. You will influence the roadmap and strategic direction of Synopsys' automation and methodology offerings. You will empower engineering teams with state-of-the-art tools, training, and support to maximize productivity and innovation. You will enhance collaboration between R&D, application engineers, and customers by standardizing best practices and methodologies. You will reduce engineering overhead and manual intervention through data-driven process improvements and automation.

You will need 10+ years of experience in EDA methodology, CAD automation, or semiconductor process development (analog, mixed-signal, or digital domains). You will have proven leadership, mentoring, and project management skills in a cross-functional engineering environment. You will have deep hands-on expertise with industry-standard EDA tools (e.g., Synopsys Custom Compiler, Cadence Virtuoso, Calibre, ICV, or similar). You will have strong programming and scripting skills in Python, Perl, TCL, Shell, SKILL, or related languages, with a focus on automation and tool integration.

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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What You'll Be Doing:

• Develop accurate timing models for macros used in multi-die designs.
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements.
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards.
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks.
• Perform STA (Static Timing Analysis) using industry-standard EDA tools.
• Support constraint development and validation for timing sign-off.
• Collaborate with design, verification, and physical implementation teams to resolve timing issues.
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA)

Authority:

• Normally receives detailed instructions on all work.
• Follows standard practices and procedures in analyzing situations or data from which answers can be readily obtained.
• Applies company policies and procedures to resolve routine issues.

What You'll Need:

• Bachelor's or Master's degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.
• 1-2 year working experience in similar roles or fresh graduates

(Fresh graduates are also welcomed and offered the on-the-job training to adapt the position's requirements.)

• Basic understanding of timing analysis, SPICE simulation, and STA concepts.
• Experience with scripting languages such as Python and TCL for automation and data processing.
• Familiarity with EDA tools for timing characterization and verification.
• Strong problem-solving abilities and keen attention to detail.
• Good verbal and written English communication skills.
• Highly responsible and self-motivated, with a strong sense of ownership over your work.
• Collaborative team player, open to feedback and eager to learn from others.
• Detail-oriented and methodical, always striving for accuracy and quality.
• Effective communicator, able to articulate technical concepts clearly.
• Adaptable and resilient in the face of new challenges or shifting priorities.
• Enthusiastic about contributing to a diverse, inclusive, and innovative workplace.

The Team You’ll Be A Part Of:

You’ll join the Synopsys UCIe Design Team, a dynamic group of engineers specializing in advanced chiplet interconnect and analog mixed-signal technologies. This is global team, which is working on state-of-the-art UCIe, 2.5D/3D IC, and Tbps die-to-die interfaces.

As a team member, you’ll receive structured training, mentorship, and exposure to the complete design flow, helping you grow into a technical expert or future design leader. If you are passionate about precision timing analysis and eager to work in a collaborative, innovative environment, we’d love to have you on our team.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

What is it like to be an Analog Design Engineer at Synopsys?

Arman Shahmuradyan

Analog Design, Manager

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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You are a passionate and versatile engineering professional who thrives in a dynamic, fast-paced environment. With a deep technical acumen and a knack for creative problem-solving, you are driven to deliver innovative solutions that address complex challenges. You have a proven track record in application engineering, accompanied by a strong understanding of EDA tools, chip design flows, and customer-centric solution delivery.

Responsibilities

• Collaborating with customers to understand their technical challenges and providing comprehensive solutions using Synopsys tools and platforms.
• Driving the adoption and integration of EDA tools in customer design flows, ensuring optimal utilization and performance.
• Developing and delivering technical workshops, training sessions, and product demonstrations tailored to customer needs.
• Partnering with R&D and product management teams to influence product direction and resolve complex technical issues.
• Authoring and maintaining technical documentation, application notes, and best practice guides.
• Providing pre- and post-sales technical support, including troubleshooting, bug tracking, and solution development.
• Mentoring and guiding junior engineers, fostering a culture of technical excellence and innovation.

Impact

• Accelerating customer success by ensuring seamless deployment and integration of Synopsys solutions.
• Enhancing product quality and usability through direct feedback and collaboration with R&D teams.
• Expanding Synopsys' footprint in key accounts by demonstrating technical excellence and building strong customer relationships.
• Reducing design cycle times and improving overall productivity for our customers.
• Contributing to the growth of Synopsys' technical community through knowledge sharing and mentoring.
• Influencing future product innovations by identifying emerging customer needs and market trends.

Requirements

• Strong expertise in ASIC/FPGA design and verification methodologies.
• Hands-on experience with industry-leading EDA tools such as synthesis, simulation, and formal verification platforms.
• Proficiency in scripting languages (e.g., Python, Perl, TCL) and automation frameworks.
• Solid understanding of digital design, SoC architectures, and semiconductor manufacturing processes.
• Ability to analyze and resolve complex technical issues quickly and effectively.

Team

You'll join an accomplished team of application engineering experts at the forefront of EDA and semiconductor innovation. Our team partners closely with customers, R&D, and product management to deliver world-class solutions and technical support. We foster a collaborative, inclusive culture that encourages continuous learning, knowledge sharing, and professional growth.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15995

Remote Eligible

No

Date Posted

03/05/2026

Alternate Job Titles:

• Staff ASIC Digital Design Engineer

• Staff DFT Engineer

• Staff SoC Testability Engineer

We Are:

At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.

You Are:

You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.

What You’ll Be Doing:

• Define and implement DFT architecture for IP designs

• Perform SCAN insertion and ATPG simulation

• Analyze and improve test coverage

• Develop STA DFT timing constraints

• Prepare DFT integration guidelines for SoC

• Conduct quality checks and FMEDA/DFMEA analysis

The Impact You Will Have:

• Enhance product reliability and quality

• Support functional safety standards (ISO26262, FUSA)

• Streamline SoC integration

• Reduce debug cycles and time-to-market

• Mentor peers

• Drive innovation in test methodology

What You’ll Need:

• BS/MS/PhD in Electronics or related field

• 5+ years DFT design experience

• Expertise in Scan insertion, ATPG, JTAG

• Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)

• Scripting (Perl, TCL, Python) is a plus

Who You Are:

• Responsible and collaborative

• Excellent English communication

• Team player and problem solver

The Team You’ll Be A Part Of:

Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are: You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

Responsibilities: Develop and validate DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team. Stay up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Impact: Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

Requirements: B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 5-8 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are: An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You’ll Be A Part Of: You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

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San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.

About the Role

We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.

You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.

In this role, you will:

• Develop, build and own tools, flows and methodologies for physical implementation
• Own physical implementation of floorplan blocks from floorplanning to final signoff
• Collaborate with RTL designers to drive optimal block implementation solutions
• Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners

Qualifications:

• BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
• Demonstrated success in taping out complex silicon designs
• Hands-on experience with block physical implementation and PPA convergence
• Strong coding experience with python, bazel, TCL
• Strong experience building physical design tools, flows and methodologies
• Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
• Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation

Bonus:

• Experience with AI or HPC-focused chips
• Experience with optimizing PPA for high performance compute cores
• Hands-on experience with top-level design methodologies

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• Reviewing and analyzing customer and partner feedback to enhance product and solution performance.
• Collaborating with R&D to shape technical roadmaps, specifications, and validation processes for product improvements.
• Diagnosing, troubleshooting, and resolving complex technical issues on-site and remotely for customer installations.

What you need

• BS or MS in Electrical or Computer Engineering.
• 6-8 years of relevant experience in the semiconductor industry.
• Hands-on expertise with Place & Route (P&R), extraction, Static Timing Analysis (STA), and Engineering Change Order (ECO) tools.

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What you'll do

• Design and implement SoC solutions using Synopsys EDA tools and IP.
• Advise customer design and CAD teams.

What you need

• BS/MS/PhD in relevant engineering fields.
• 7+ years in Place & Route with Fusion Compiler/ICC2.

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What you'll do

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 5 years of hands-on experience in RTL design and verification.

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What you'll do

• Creating and optimizing design flows and solutions to meet aggressive PPA targets for high-frequency cores, automotive, and high-capacity AI/compute designs.
• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong understanding of ASIC design flow, VLSI, and CAD development.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

• Providing expert support and training to customers on PrimeTime, PrimeClosure, and PrimeShield, ensuring optimal use and maximum productivity.
• Independently coordinating and supporting multiple customer designs through tape-out, verifying designs meet or exceed customer expectations.

What you need

• Bachelor’s degree in Electrical Engineering with a minimum of 12 years of experience, or a Master’s degree with at least 8 years of experience.
• In-depth understanding of timing, power, statistical and electromigration characterization, and signal integrity in advanced SoC design.

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What you'll do

• Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.
• Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.
• Carry out experiments to validate modeling and methodologies.
• Develop and document signal and power integrity requirements and flows for internal and external customer use.

What you need

• Possesses excellent communication skills, both verbal and written.
• Familiarity with both Windows and Linux operating system is required.
• An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.
• Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.
• Some experience in programming languages such as Python, TCL and Matlab is desired.
• A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. Experience with Redhawk, Totem, Ansys AEDT, Keysight ADS, etc. is a plus.
• Practical experience with package and pcb design 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.
• Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
• Bachelor's or Master's degree in Electrical or Electronics Engineering, with a minimum of 6 years of relevant experience in supporting interface IP product development (preferably DDR), system integration and Signal and Power verifications flow/methodologies.

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What you'll do

• Providing expert-level support for PrimeTime, Synopsys’ industry-leading Static Timing Analysis (STA) tool, to both prospective and existing customers.
• Leading competitive product benchmarks and technical evaluations, demonstrating PrimeTime’s advantages to customer design teams and management.
• Delivering customer training sessions and workshops, enabling teams to maximize their productivity and achieve successful tape-outs.

What you need

• Bachelor’s degree in Electrical Engineering or equivalent with 5-7 years of relevant experience, or Master’s degree (MSEE or equivalent) with 4-6 years of experience.
• Hands-on experience and in-depth knowledge of Synopsys PrimeTime or similar STA tools.

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What you'll do

• Interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB;
• Evaluating and troubleshooting digital and mixed-signal circuits to ensure optimal performance and resolve complex design challenges;
• Collaborating with digital, firmware, and analog teams to solve verification challenges and improve design methodologies;
• Adapting and debugging internal verification environments to effectively replicate challenging scenarios;
• Identifying and implementing process improvements to enhance efficiency in design procedures and methodologies;
• Documenting verification environments, plans, and procedures to ensure clear communication and knowledge sharing across teams.

What you need

• 6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification;
• Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping with logical synthesis flows;
• Strong programming and scripting skills for test automation and data analytics (Python, C/C++, TCL);
• Strong understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization techniques;
• Ability to interpret and apply digital architecture and SerDes standards documentation to develop robust verification solutions;
• Excellent technical documentation skills to ensure clear communication and knowledge transfer.

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What you'll do

As a HBM Design Verification Engineer, Principal, you will be responsible for developing verification strategies and plans for ASIC/SoC projects, defining and implementing testbench architecture and methodologies, building testbench infrastructure and verification components, and creating verification item lists, coverage models, and checkers.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 10–15+ years of relevant experience

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What you'll do

• Partnering with design teams to define verification requirements
• Developing test plans from specifications
• Building and maintaining UVM testbenches and agents

What you need

• B.Sc./M.Sc. in a relevant engineering field
• 10+ years in ASIC/UVM verification

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What you'll do

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.
• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 9+ years of relevant experience.
• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).
• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes (like 2nm/3nm/5nm etc).
• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.
• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.
• Outstanding verbal and written communication, presentation, and customer interaction skills.

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What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 7 to 10+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Collaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment.
• Demonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority.

What you need

• BS/MS in Electrical Engineering or Computer Science with 4+ years of relevant experience.
• Hands-on experience with synthesis and place and route (P&R) tools.

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.

What you need

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.

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What you'll do

As a Sr Staff Engineer, you will be responsible for designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

What you need

• MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
• Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
• Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
• Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
• Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
• Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Why this matters

• Accelerate the development of industry-leading prototyping systems, enabling faster time-to-market for cutting-edge ASIC designs.
• Enhance the functionality and reliability of Synopsys' HAPS and ProtoCompiler products through innovative hardware and software solutions.
• Drive customer satisfaction by delivering robust, scalable, and user-friendly prototyping tools that meet diverse engineering needs.
• Contribute to Synopsys' reputation as a leader in verification and prototyping technology, influencing industry standards and practices.

What you'll be doing

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
• Developing and maintaining complex EDA software for high-performance prototyping systems.
• Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
• Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
• Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
• Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
• Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
• Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Why you'll love this role

• Opportunity to work on cutting-edge projects and technologies.
• Collaborative and dynamic work environment.
• Professional growth and development opportunities.
• Recognition and rewards for outstanding performance.
• Comprehensive benefits and compensation package.

What you'll need to succeed

• Strong technical skills and knowledge in digital design, verification, and prototyping.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.
• Ability to work independently and as part of a team.
• Adaptability and flexibility in a fast-paced environment.

How to apply

• If you're ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.
• Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away, including company holidays, ETO, and FTO programs.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, with a 15% discount on Synopsys common stock.
• Retirement plans, varying by region and country.
• Competitive salaries.

How we hire

• We're proud to be an equal opportunities employer and welcome applications from diverse candidates.
• Our hiring process typically involves a phone screen, followed by an interview with the hiring team.
• We're committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.

Join our team

• If you're passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.
• We can't wait to hear from you!

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What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 2 - 4 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 6-12 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

• Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).
• Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

What you need

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).
• Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

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What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

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What you'll do

• Developing and writing high-quality user documentation for a variety of Digital and Mixed Signal IPs, including USB, PCIe, Ethernet, DDR, HDMI, and MIPI.
• Planning, organizing, and editing technical specifications, engineering schematics, application notes, and user guides to ensure clarity and usability.

What you need

• Bachelor’s or Master’s degree in Electronics, Science, Hardware, Computing, Software, Physics, Mathematics, Engineering, or a related technical discipline.
• 3-7 years of technical writing experience in the software or hardware industry, with proven ability to deliver high-quality documentation.

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What you'll do

• Providing advanced technical debugging support for Totem-SC and Totem, ensuring seamless customer experiences.
• Setting up, validating, and reproducing customer flows to investigate and resolve complex issues.
• Collaborating with R&D teams to perform root cause analysis and implement effective solutions.
• Supporting certification and evaluation flows for analog IP and power integrity tools.
• Delivering on-site or remote technical support to Korean customers, adapting to their unique needs and environments.
• Extending support to global customers as needed, contributing to Synopsys' worldwide reputation for excellence.

What you need

• Strong understanding of analog IP EM/IR analysis methodologies and challenges.
• Hands-on experience with power integrity tools such as Totem and Totem-SC.
• Proficiency in SPICE simulation and netlist debugging for analog and mixed-signal designs.
• Knowledge of DSPF/SPF formats and their application in power and signal integrity analysis.
• Expertise in Linux environments, with scripting skills in Python or TCL preferred.
• Familiarity with foundry PDKs and certification flows for advanced semiconductor processes.

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What you'll do

• Providing advanced technical debugging support for Totem-SC and Totem, ensuring seamless customer experiences.
• Setting up, validating, and reproducing customer flows to investigate and resolve complex issues.
• Collaborating with R&D teams to perform root cause analysis and implement effective solutions.
• Supporting certification and evaluation flows for analog IP and power integrity tools.
• Delivering on-site or remote technical support to Korean customers, adapting to their unique needs and environments.
• Extending support to global customers as needed, contributing to Synopsys' worldwide reputation for excellence.

What you need

• Strong understanding of analog IP EM/IR analysis methodologies and challenges.
• Hands-on experience with power integrity tools such as Totem and Totem-SC.
• Proficiency in SPICE simulation and netlist debugging for analog and mixed-signal designs.
• Knowledge of DSPF/SPF formats and their application in power and signal integrity analysis.
• Expertise in Linux environments, with scripting skills in Python or TCL preferred.
• Familiarity with foundry PDKs and certification flows for advanced semiconductor processes.

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What you'll do

This role is responsible for designing, developing, and maintaining high-performance EDA software programs used in semiconductor design and verification.

• Designing, developing, and maintaining high-performance EDA software programs used in semiconductor design and verification.
• Troubleshooting and debugging complex software issues related to partitioning, legalization, and routing algorithms.

What you need

• Bachelor’s degree with 5+ years, or Master’s degree with 3+ years of relevant experience in EDA or the semiconductor industry.
• Strong proficiency in C++ and C++11, with deep understanding of object-oriented programming and design patterns.
• Proven experience with algorithm development, particularly in partitioning, routing, or similar domains.

Why this matters

Drive the advancement of cutting-edge EDA tools that enable next-generation semiconductor designs.

What You’ll Be Doing

• Designing, developing, and maintaining high-performance EDA software programs used in semiconductor design and verification.
• Troubleshooting and debugging complex software issues related to partitioning, legalization, and routing algorithms.
• Collaborating with cross-functional teams and global stakeholders to define requirements and deliver robust solutions.
• Developing and extending APIs to support integration with various tool flows and customer environments.
• Working closely with end-users and internal partners to diagnose issues, gather feedback, and enhance tool usability.
• Utilizing scripting languages (Python, Bash, TCL) to automate tasks and improve development workflows.

The Impact You Will Have

• Drive the advancement of cutting-edge EDA tools that enable next-generation semiconductor designs.
• Enhance the performance, efficiency, and accuracy of partitioning and legalization processes in chip design flows.
• Empower semiconductor companies worldwide to accelerate their design cycles and deliver innovative products to market faster.
• Contribute to the global reputation of Synopsys as the leader in EDA software and IP solutions.
• Mentor and collaborate with engineers across regions, fostering a culture of knowledge sharing and continuous improvement.
• Shape the direction of tool development by incorporating customer feedback and industry best practices.

What You’ll Need

• Bachelor’s degree with 5+ years, or Master’s degree with 3+ years of relevant experience in EDA or the semiconductor industry.
• Strong proficiency in C++ and C++11, with deep understanding of object-oriented programming and design patterns.
• Proven experience with algorithm development, particularly in partitioning, routing, or similar domains.
• Hands-on expertise in multi-threaded and distributed software development.
• Familiarity with API-based development and scripting languages such as Bash, Python, or TCL.

Who You Are

• Analytical thinker with a passion for solving complex technical challenges.
• Excellent communicator, able to convey technical information clearly across diverse teams and cultures.
• Collaborative team player who thrives in a global, cross-functional environment.
• Self-motivated, proactive, and adaptable to changing project needs.
• Detail-oriented and committed to delivering high-quality, reliable software solutions.

The Team You’ll Be A Part Of

You’ll join a R&D team at Synopsys Korea, working alongside experts in EDA software development, algorithm research, and semiconductor design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Awards

We’re proud to receive several recognitions, including being named one of the Best Places to Work by Fortune Magazine and one of the Top 100 Most Innovative Companies by Fast Company.

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What you'll do

You will be responsible for independently owning and driving full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.

• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.

• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.

What you need

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.

• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).

• Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification.

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