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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative environments. You have a proven track record in RTL design and verification, and you are excited about contributing to cutting-edge technology. With your extensive expertise, you can handle complex and unique issues, often requiring innovative solutions. You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.</li>\n<li>Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.</li>\n<li>Developing and executing comprehensive test plans to verify the functionality and performance of your designs.</li>\n<li>Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.</li>\n<li>Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.</li>\n<li>Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.</li>\n<li>Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.</li>\n<li>Enhancing the overall quality and performance of Synopsys&#39; products through meticulous design and verification processes.</li>\n<li>Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.</li>\n<li>Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.</li>\n<li>Contributing to Synopsys&#39; reputation as a leader in the semiconductor industry through your expertise and innovative solutions.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.</li>\n<li>Proficiency in using industry-standard EDA tools and methodologies for design and verification.</li>\n<li>Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).</li>\n<li>Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.</li>\n<li>Experience with power analysis and RTL level power optimization techniques.</li>\n<li>Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.</li>\n<li>Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.</li>\n<li>Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.</li>\n<li>A strategic thinker with the ability to implement goals that have a direct impact on department results.</li>\n<li>A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.</li>\n<li>A collaborative team player who thrives in dynamic and fast-paced environments.</li>\n<li>A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a global leader in semiconductor design and verification solutions, we enable the world&#39;s most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.</p>\n<p>You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.</p>\n<p>You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&amp;D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you&#39;ll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/29/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a forward-thinking engineer with a passion for leveraging cutting-edge AI technologies to revolutionize electronic design automation and verification. You thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your experience in verification frontend flows and AI/ML frameworks enables you to bridge the gap between traditional engineering practices and intelligent automation. You are comfortable working across diverse teams, collaborating with design, verification, CAD, and methodology experts to identify impactful automation opportunities. You possess strong analytical skills, enabling you to dissect complex verification challenges and develop scalable GenAI solutions. Your commitment to professional growth is evident in your eagerness to stay current with the latest advancements in LLMs, GenAI, and verification technology. With a keen eye for detail and a drive to deliver high-quality results, you are adept at integrating AI-driven capabilities into established workflows, elevating productivity and efficiency. You value inclusivity and diverse perspectives, and you are motivated by the opportunity to shape the future of engineering through innovative, intelligent solutions.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Develop and deploy LLM/GenAI-based solutions to enhance verification productivity across static, formal, and simulation-based flows in EDA tools.</li>\n</ul>\n<ul>\n<li>Collaborate cross-functionally with design, verification, CAD, and methodology teams to identify high-impact areas for AI-assisted automation.</li>\n</ul>\n<ul>\n<li>Build tools and frameworks to generate or refine assertions, constraints, checkers, and test intent, summarize design/spec content, and analyze logs, failures, and coverage gaps.</li>\n</ul>\n<ul>\n<li>Integrate LLM-driven capabilities into existing verification flows, tools, and automation infrastructure, ensuring seamless adoption.</li>\n</ul>\n<ul>\n<li>Develop and maintain scripts, data pipelines, and evaluation frameworks for AI-assisted verification use cases.</li>\n</ul>\n<ul>\n<li>Stay current with advances in LLMs, GenAI, verification technology, and digital design methodologies to inform best practices.</li>\n</ul>\n<ul>\n<li>Participate in technical reviews and help define scalable AI adoption strategies within verification environments.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate verification planning, setup, and closure, enabling faster time-to-market for complex digital designs.</li>\n</ul>\n<ul>\n<li>Enhance productivity and efficiency for engineering teams through intelligent automation and AI-driven solutions.</li>\n</ul>\n<ul>\n<li>Reduce manual effort and potential errors in verification by automating routine and complex tasks.</li>\n</ul>\n<ul>\n<li>Improve coverage analysis, debug processes, and testbench/content generation, resulting in higher quality silicon chips.</li>\n</ul>\n<ul>\n<li>Drive innovation in verification methodologies by integrating state-of-the-art GenAI capabilities.</li>\n</ul>\n<ul>\n<li>Foster cross-functional collaboration, contributing to robust and scalable verification strategies.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ leadership in EDA technology and AI-driven engineering solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.</li>\n</ul>\n<ul>\n<li>5–8 years of experience in EDA software development with prior experience in developing GenAI-based tools.</li>\n</ul>\n<ul>\n<li>Hands-on experience with LLM/GenAI or AI/ML frameworks/tools such as PyTorch, TensorFlow, Hugging Face, LangChain, or equivalent.</li>\n</ul>\n<ul>\n<li>Proficiency in C++ and familiarity with Verilog, VHDL, or SystemVerilog.</li>\n</ul>\n<ul>\n<li>Strong understanding of verification frontend methodologies, including static analysis (CDC/RDC/Lint), formal/property-based verification, and simulation bring-up/debug.</li>\n</ul>\n<ul>\n<li>Experience with cloud or scalable compute platforms (AWS, GCP, Azure) is a plus.</li>\n</ul>\n<ul>\n<li>Familiarity with Agile development methodologies is desirable.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a passion for applying AI to real-world engineering challenges.</li>\n</ul>\n<ul>\n<li>Effective communicator, able to convey complex technical concepts to diverse audiences.</li>\n</ul>\n<ul>\n<li>Collaborative team player who thrives in cross-functional environments.</li>\n</ul>\n<ul>\n<li>Strong problem-solving abilities and analytical mindset.</li>\n</ul>\n<ul>\n<li>Adaptable, eager to learn, and comfortable with ambiguity in fast-evolving technology landscapes.</li>\n</ul>\n<ul>\n<li>Self-driven and proactive, with a commitment to delivering impactful solutions.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a collaborative and innovative engineering team focused on advancing verification productivity through AI-driven solutions. The team works closely with design, verification, CAD, and methodology groups to identify and implement high-impact automation strategies. Together, you will drive the adoption of GenAI technologies within Synopsys’ EDA ecosystem, fostering a culture of continuous improvement and technological excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>Get an idea of what your daily routine <strong>around the office</strong> can be like</strong></p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_90f641e9-987","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/ai-llm-software-developer-verification-frontend/44408/93375604432","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["LLM/GenAI","PyTorch","TensorFlow","Hugging Face","LangChain","C++","Verilog","VHDL","SystemVerilog","static analysis","formal/property-based verification","simulation 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innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You have a strong passion for working with embedded processors or processor-based systems.</p>\n<p>You bring knowledge of HDL design, with a preference for experience in RISC processor architectures, DSP, AI (Neural Processing Unit), and multi-core systems.</p>\n<p>You are familiar with design and verification languages such as Verilog and SystemVerilog, and have experience with RTL simulation tools, such as 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the application of state-of-the-art methodologies.</li>\n</ul>\n<ul>\n<li>Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.</li>\n</ul>\n<ul>\n<li>Enable customers to create sophisticated and efficient embedded designs.</li>\n</ul>\n<ul>\n<li>Support the delivery of world-class microprocessors used in advanced applications.</li>\n</ul>\n<ul>\n<li>Help improve functional coverage and performance of processor IP through advanced verification methods.</li>\n</ul>\n<ul>\n<li>Collaborate globally to deliver customer-focused solutions.</li>\n</ul>\n<ul>\n<li>Drive continuous improvement in processor system verification.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Passion for embedded processors or processor-based systems.</li>\n</ul>\n<ul>\n<li>Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.</li>\n</ul>\n<ul>\n<li>Familiarity with Verilog and SystemVerilog.</li>\n</ul>\n<ul>\n<li>Experience with RTL simulation tools (e.g., VCS).</li>\n</ul>\n<ul>\n<li>Scripting or programming skills in assembler, C, Tcl, Csh, or Python.</li>\n</ul>\n<ul>\n<li>Experience with embedded software for DSP or AI reference models is a plus.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Strong analytical and problem-solving abilities.</li>\n</ul>\n<ul>\n<li>Excellent written and verbal communication skills.</li>\n</ul>\n<ul>\n<li>Proficient in English.</li>\n</ul>\n<ul>\n<li>Capable of detailed status reporting and presenting results to program management teams.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join our dynamic team dedicated to developing highly optimized hardware IP for the ARC family of configurable processors, enabling customers to create sophisticated and efficient embedded designs.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As an experienced and visionary ASIC digital design architect, you will thrive in a fast-paced, collaborative environment. You will bring a passion for solving complex system-level challenges and a track record of delivering innovative, high-quality silicon solutions.</p>\n<p>Your deep understanding of IP and SoC architectures enables you to see the big picture while meticulously refining subsystem details. You are comfortable navigating ambiguity, building consensus across diverse teams, and translating product requirements into robust, scalable architectures.</p>\n<p>Your leadership inspires those around you, and you excel at mentoring and empowering engineers to reach their full potential. You are adept at balancing trade-offs across performance, power, area, and security, always striving for the optimal solution.</p>\n<p>Communication is your strength,you articulate technical concepts clearly to both technical and non-technical stakeholders, ensuring alignment and shared understanding.</p>\n<p>With a growth mindset, you embrace new challenges, technologies, and methodologies, continuously seeking opportunities to innovate and improve.</p>\n<p>You value inclusion and diversity, recognizing that the best ideas emerge from a culture where everyone feels empowered to contribute.</p>\n<p>As an IP Subsystems Architect, you will define architectural specifications for complex subsystems, translate system-level requirements into detailed subsystem architectures, and integrate multiple IP blocks into cohesive subsystems.</p>\n<p>You will lead cross-functional collaboration with hardware, software, verification, and physical design teams to ensure subsystem feasibility and correctness.</p>\n<p>Establishing and guiding verification and validation strategies, including defining coverage requirements and participating in silicon bring-up and debug sessions.</p>\n<p>Producing comprehensive architecture documents, specifications, and guidelines, and clearly communicating architectural intent to a wide range of stakeholders.</p>\n<p>Mentoring and coaching engineers, driving best practices, and fostering a culture of technical excellence.</p>\n<p>Shape the architecture of industry-leading silicon IP and subsystem solutions that power millions of devices worldwide.</p>\n<p>Accelerate time-to-market for differentiated products by ensuring robust and efficient subsystem design and integration.</p>\n<p>Reduce risk through rigorous requirements management, architectural clarity, and cross-functional alignment.</p>\n<p>Enhance product performance, power efficiency, and reliability, directly impacting customer satisfaction and competitive advantage.</p>\n<p>Foster innovation by mentoring teams, introducing new methodologies, and championing best practices.</p>\n<p>Strengthen Synopsys’ position as a trusted technology leader in the semiconductor ecosystem.</p>\n<p>Bachelor’s or Master’s degree in Electronics or a related field, with 15+ years of industry experience.</p>\n<p>At least 10 years in semiconductor design, IP integration, or SoC/subsystem architecture roles.</p>\n<p>Deep expertise in Verilog/SystemVerilog, simulation tools, and advanced verification methodologies (e.g., SV UVM, BFM development).</p>\n<p>Proficiency with industry-standard interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.).</p>\n<p>Experience with synthesis, lint, CDC, low-power flows, and achieving verification closure.</p>\n<p>Strong documentation and communication skills for effective cross-team alignment and requirements management.</p>\n<p>A strategic thinker with exceptional leadership and mentoring capabilities.</p>\n<p>A collaborative partner who thrives in diverse, cross-functional teams.</p>\n<p>An excellent communicator, able to tailor messaging for both technical and non-technical audiences.</p>\n<p>Innovative and proactive, always seeking opportunities to improve processes and outcomes.</p>\n<p>Resilient and adaptable, comfortable with change and ambiguity.</p>\n<p>Committed to fostering an inclusive and empowering team culture.</p>\n<p>Join the Digital IP Subsystems Team at Synopsys,a high-performing group of architects, designers, and engineers focused on delivering world-class silicon IP and subsystem solutions.</p>\n<p>The team collaborates closely with hardware, software, verification, and product teams across the globe, driving innovation in next-generation SoCs for AI, automotive, 5G, IoT, and more.</p>\n<p>Together, we value creativity, technical excellence, and inclusion, empowering each team member to make a significant impact.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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tools.</li>\n<li>Enhance Synopsys&#39; product offerings by providing actionable feedback from customer engagements and competitive benchmarking.</li>\n<li>Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.</li>\n<li>Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.</li>\n<li>Contribute to the growth of Synopsys&#39; leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.</li>\n<li>Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.</li>\n<li>Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.</li>\n<li>Proven experience in debugging simulation mismatches and verification flows.</li>\n<li>Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.</li>\n<li>Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Excellent written and oral communication skills, comfortable interfacing with global teams and customers.</li>\n<li>Collaborative team player with a proactive and innovative mindset.</li>\n<li>Detail-oriented and organized, able to manage multiple tasks and priorities.</li>\n<li>Motivated self-starter with strong problem-solving abilities.</li>\n<li>Adaptable and open to travel, eager to learn and grow in a fast-paced environment.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&amp;D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a4490a5f-125","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/sr-staff-application-engineer-vcs-simulation/44408/93232526272","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["verification technologies","simulation","UVM","SVA","LRM","HDL languages","Verilog","VHDL","SystemVerilog","digital design fundamentals","advanced scripting skills","Perl","TCL","Make","Shell","UNIX environments","Synopsys EDA tools","SpyGlass","VC SpyGlass","Verdi"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:36.950Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"verification technologies, simulation, UVM, SVA, LRM, HDL languages, Verilog, VHDL, SystemVerilog, digital design fundamentals, advanced scripting skills, Perl, TCL, Make, Shell, UNIX environments, Synopsys EDA tools, SpyGlass, VC SpyGlass, Verdi"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_06826e94-e25"},"title":"ASIC Digital Design, Sr Engineer","description":"<p>You are a passionate, detail-oriented engineer who thrives in collaborative environments and enjoys tackling complex technical challenges. With a strong theoretical and practical background in high-speed data recovery circuits, you are eager to contribute your expertise to cutting-edge mixed-signal designs.</p>\n<p>You have a proven track record in digital design and verification, and you are comfortable working across ASIC, FPGA, and firmware domains. Your experience enables you to interpret and review digital and analog specifications, create robust analog models, and write modular, constrained-random testbenches in Verilog and SystemVerilog.</p>\n<p>You are adept at performing functional, assertion, and code coverage, and you have a keen eye for failure analysis and testplan management. Your organisational skills ensure that projects move forward efficiently, and your communication abilities allow you to interface effectively with multidisciplinary teams and customer support groups.</p>\n<p>You value diversity, inclusivity, and continuous learning, seeking out opportunities to grow and mentor others. As someone who is motivated by innovation, you are excited to work with an expert team and help deliver high-end mixed-signal designs that power the next generation of smart technology.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Designing and verifying ASIC, FPGA, and firmware for high-speed mixed-signal circuits.</li>\n</ul>\n<ul>\n<li>Reviewing digital and analog specifications to ensure alignment with project goals.</li>\n</ul>\n<ul>\n<li>Creating analog models based on schematics and functional requirements.</li>\n</ul>\n<ul>\n<li>Developing modular, constrained-random testbenches in Verilog and SystemVerilog for robust verification.</li>\n</ul>\n<ul>\n<li>Performing functional, assertion, and code coverage, analysing results to identify areas for improvement.</li>\n</ul>\n<ul>\n<li>Developing, managing, and tracking comprehensive testplans to ensure thorough verification.</li>\n</ul>\n<ul>\n<li>Reviewing and analysing failure cases to drive corrective actions and enhance product reliability.</li>\n</ul>\n<ul>\n<li>Running gate-level simulations to validate design integrity and performance.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional design groups and customer support teams to resolve technical challenges.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Advancing the development of high-performance mixed-signal designs that enable next-generation applications.</li>\n</ul>\n<ul>\n<li>Ensuring functional and performance integrity of silicon IP products through rigorous verification.</li>\n</ul>\n<ul>\n<li>Accelerating time-to-market for differentiated products by reducing risk and increasing design confidence.</li>\n</ul>\n<ul>\n<li>Contributing to the world&#39;s broadest portfolio of silicon IP, supporting innovation in AI, IoT, 5G, and more.</li>\n</ul>\n<ul>\n<li>Enhancing reliability and quality of products that power smart devices and autonomous systems.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys&#39; reputation as a leader in chip design and software security by delivering excellence.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BSEE with 2 years of digital design and verification experience, or MSEE with 0 years of digital design and verification industry experience.</li>\n</ul>\n<ul>\n<li>Expertise in ASIC design, synthesis, and clock domain crossing (CDC).</li>\n</ul>\n<ul>\n<li>Hands-on experience writing complex testcases in Verilog and SystemVerilog.</li>\n</ul>\n<ul>\n<li>Familiarity with code quality metrics and best practices in verification methodologies.</li>\n</ul>\n<ul>\n<li>Ability to create system-level specifications for digital and analog domains.</li>\n</ul>\n<ul>\n<li>Strong knowledge of high-speed digital and mixed-signal design principles.</li>\n</ul>\n<ul>\n<li>Experience with asynchronous clock crossings and DFT (Design For Test) methodologies.</li>\n</ul>\n<p><strong>Team:</strong></p>\n<p>Join a highly experienced mixed-signal design team, dedicated to delivering high-end mixed-signal designs from specification development through functional and performance testing. You&#39;ll be working alongside expert digital and mixed-signal engineers, collaborating across design, verification, and customer support to push the boundaries of innovation in silicon IP and SoC integration.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. 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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>You are a passionate Computer Scientist with an exceptional analytical mind, driven by curiosity and a desire to solve some of the most challenging problems in automated logical reasoning and symbolic computation. You thrive in intellectually stimulating environments, enjoying the pursuit of innovative solutions within deep technology domains. Your expertise spans formal methods, algorithms, and complexity theory, enabling you to tackle large-scale, industrial verification challenges with confidence and creativity.</p>\n<p>You bring hands-on experience in developing robust software solutions, particularly in C/C++. Whether your background is academic or industry, your contributions have been recognized by peers, and you are eager to collaborate with leading experts in the field. You understand the nuances of hardware architecture and design languages like SystemVerilog, or you are enthusiastic to learn them, appreciating their impact on verification excellence.</p>\n<p>You are adaptable, open to new ideas, and motivated by continuous learning. You value diversity of thought, enjoy working in collaborative teams, and are committed to advancing the state of the art in formal verification. You believe in the transformative power of AI/ML-assisted design flows and are excited to shift the paradigm from design-centric to verification-centric innovation. Above all, you are ready to make a significant impact in the future of technology by joining the Synopsys Formal Technology Group.</p>\n<p>Designing and implementing advanced formal verification algorithms and proof engines for large-scale VLSI chip designs.\nDeveloping scalable, memory-efficient, and mathematically robust solvers to address industry-leading verification challenges.\nIntegrating innovative solutions into the Synopsys VC Formal platform, enhancing its capabilities and usability for thousands of engineers worldwide.\nCollaborating with cross-functional teams to extend formal verification technologies into domains such as hardware security, functional safety, and low power.\nEngaging with customers and industry partners to understand their verification needs and deliver best-in-class solutions.\nContributing to the formal verification community through peer-reviewed publications, technical presentations, and mentorship of junior team members.</p>\n<p>Advancing the scalability and reliability of formal verification tools used by leading chip design companies.\nBreaking complexity barriers, enabling verification of the most challenging and extensive industrial designs.\nDriving innovation in AI/ML-assisted design flows, transforming the verification landscape for the semiconductor industry.\nEmpowering customers to achieve functional safety, hardware security, and low power goals in their products.\nFacilitating widespread adoption of formal methods across diverse domains and applications.\nFostering a collaborative, intellectually rich environment that inspires continuous learning and knowledge sharing.</p>\n<p>8-10 years of relevant experience\nExpertise in formal methods, model checking, theorem proving, and equivalence checking.\nStrong proficiency in algorithms, data structures, and complexity analysis.\nProfessional coding skills in C/C++ and experience developing large-scale software systems.\nBackground in hardware architecture and familiarity with design languages such as SystemVerilog (preferred but not required).\nPeer recognition in the formal verification community, such as publications or industry accolades.</p>\n<p>Analytical thinker with a keen eye for detail and problem-solving.\nCollaborative team player who values diversity and open communication.\nInnovative and adaptable, willing to embrace new technologies and methodologies.\nDriven by curiosity and a passion for continuous learning.\nResilient in the face of challenging technical problems and complexity.</p>\n<p>You’ll join the Synopsys VC Formal R&amp;D Team,a vibrant community of talent and expertise dedicated to advancing formal verification technologies. The team is renowned for solving deep theoretical and practical problems and integrating them into world-leading verification tools. You will collaborate with experts in formal methods, software engineering, and AI/ML, contributing to the proliferation of formal verification across hardware security, functional safety, low power, and more.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7f282b7c-68c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hillsboro/sr-staff-formal-verification-r-and-d-engineer/44408/93232526192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":"$144000-$216000","x-skills-required":["formal methods","model checking","theorem proving","equivalence checking","algorithms","data structures","complexity analysis","C/C++","SystemVerilog"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:22.176Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"formal methods, model checking, theorem proving, equivalence checking, algorithms, data structures, complexity analysis, C/C++, SystemVerilog","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":144000,"maxValue":216000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1fe3012d-71e"},"title":"R&D Staff Software Engineer - Simulation","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification, and manufacturing.</p>\n<p>We are seeking a seasoned engineer with a passion for pushing the boundaries of technology to join our team. With 5-8 years of experience, you will bring a wealth of knowledge in software architecture and excel in C/C++ software development, digital simulation, compiler optimizations, and design patterns, data structures, and algorithms.</p>\n<p>As a member of our performance team in Digital Simulation, you will work closely with both local and global teams to drive technological advancements and achieve project goals.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Designing, developing, and troubleshooting core algorithms for compiler.</li>\n<li>Collaborating with local and global teams to enhance runtime performance for verilog compiler.</li>\n<li>Engaging in pure technical roles focused on software development and architecture.</li>\n<li>Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation.</li>\n<li>Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Driving technological innovation in chip design and verification.</li>\n<li>Enhancing the performance and quality of simulation tools used globally.</li>\n<li>Solving complex compiler optimizations problems to improve simulation performance.</li>\n<li>Collaborating with cross-functional teams to achieve project milestones.</li>\n<li>Pioneering new software architectures that set industry standards.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Strong hands-on experience in C/C++ based software development.</li>\n<li>Deep understanding of design patterns, data structures, algorithms, and programming concepts.</li>\n<li>Knowledge of ASIC design flow and EDA tools and methodologies.</li>\n<li>Proficiency in Verilog, SystemVerilog, and VHDL HDL.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Highly enthusiastic and energetic team player with excellent communication skills.</li>\n<li>Strong desire to learn and explore new technologies.</li>\n<li>Effective problem-solver with a keen analytical mind.</li>\n<li>Experienced in working on Unix/Linux platforms.</li>\n<li>Adept at using developer tools such as gdb and Valgrind.</li>\n</ul>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1fe3012d-71e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/r-and-d-staff-software-engineer-simulation/44408/88147323248","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["C/C++","Digital simulation","Compiler optimizations","Design patterns","Data structures","Algorithms","Verilog","SystemVerilog","VHDL"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:07.099Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++, Digital simulation, Compiler optimizations, Design patterns, Data structures, Algorithms, Verilog, SystemVerilog, VHDL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_de89b568-8b1"},"title":"ASIC Digital Design, Sr Manager","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. 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Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>We are seeking a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. 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You will pioneer new software architectures that set industry standards.</p>\n<p>To succeed in this role, you will need strong hands-on experience in C/C++ based software development. You will require a deep understanding of design patterns, data structures, algorithms, and programming concepts. You will need knowledge of ASIC design flow and EDA tools and methodologies. You will require proficiency in Verilog, SystemVerilog, and VHDL HDL. You will need 10+ years of relevant EDA Software experience preferably in Simulation domain.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bf6e7034-9fc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/principal-simulation-r-and-d-software-engineer/44408/93498496896","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["C/C++","Verilog","SystemVerilog","VHDL","Unix/Linux","gdb","Valgrind"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:16:35.231Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++, Verilog, SystemVerilog, VHDL, Unix/Linux, gdb, Valgrind"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5004de27-21f"},"title":"ASIC Digital Verification, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.</p>\n<p>What You&#39;ll Be Doing:</p>\n<ul>\n<li>Designing and implementing verification environments to ensure the correctness of Interface IP protocols.</li>\n<li>Creating and executing detailed test plans to verify complex ASIC designs.</li>\n<li>Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.</li>\n<li>Collaborating with design and architecture teams to identify and fix bugs.</li>\n<li>Performing functional coverage analysis and driving coverage closure.</li>\n<li>Mentoring and guiding junior verification engineers in best practices and methodologies.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.</li>\n<li>Enhancing the robustness and efficiency of our verification processes and methodologies.</li>\n<li>Contributing to the successful launch of Interface IP products, impacting various industries.</li>\n<li>Driving innovation and excellence within the verification team.</li>\n<li>Improving the overall performance and functionality of Synopsys&#39; IP offerings.</li>\n<li>Fostering a culture of continuous improvement and technical excellence.</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.</li>\n<li>Proficiency in SystemVerilog and UVM methodologies.</li>\n<li>Strong understanding of digital design and verification concepts.</li>\n<li>Experience with simulation tools such as VCS, ModelSim, or similar.</li>\n<li>Excellent problem-solving skills and attention to detail.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Detail-oriented with a strong analytical mindset.</li>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n<li>Collaborative team player who thrives in a dynamic environment.</li>\n<li>Proactive and self-motivated, with a commitment to continuous learning.</li>\n<li>Mentor and leader, capable of guiding and developing junior engineers.</li>\n</ul>\n<p>The Team You&#39;ll Be A Part Of:</p>\n<p>You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. 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Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry 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challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b5f1283c-76e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-digital-design-sr-staff-principal-engineer-ddr/44408/92599737760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","System architecture","ASIC solutions","High-performance protocols","DDR PHY","PCIe","USB","HBM","Verilog","SystemVerilog","Simulation tools","Design flows","Lint","CDC","Synthesis","Static timing analysis","Formal verification","Control path-oriented designs","Asynchronous FIFOs","DMA","SPRAM/DPRAM interfaces","Scripting languages","Perl","Shell"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:04:48.404Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, System architecture, ASIC solutions, High-performance protocols, DDR PHY, PCIe, USB, HBM, Verilog, SystemVerilog, Simulation tools, Design flows, Lint, CDC, Synthesis, Static timing analysis, Formal verification, Control path-oriented designs, Asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces, Scripting languages, Perl, Shell"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e4d64b54-9d8"},"title":"Senior Staff R&D Engineer (SoC)","description":"<p><strong>Overview</strong></p>\n<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15159</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/04/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.</li>\n</ul>\n<ul>\n<li>Creating emulation-based transactor and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Providing technical support and guidance to customers during the deployment of the ZeBu emulator.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.</li>\n</ul>\n<ul>\n<li>Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.</li>\n</ul>\n<ul>\n<li>Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.</li>\n</ul>\n<ul>\n<li>Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys&#39; market position.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.</li>\n</ul>\n<ul>\n<li>Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.</li>\n</ul>\n<ul>\n<li>A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.</li>\n</ul>\n<ul>\n<li>Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.</li>\n</ul>\n<ul>\n<li>Proficiency with UNIX and scripting.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e4d64b54-9d8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/seongnam-si/senior-staff-r-and-d-engineer-soc/44408/91427515184","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design/verification","Verilog","SystemVerilog","ZeBu emulator","UNIX","scripting"],"x-skills-preferred":["AMBA AXI/CHI","LPDDR memory controllers"],"datePosted":"2026-03-09T11:07:14.173Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Seongnam-si"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design/verification, Verilog, SystemVerilog, ZeBu emulator, UNIX, scripting, AMBA AXI/CHI, LPDDR memory controllers"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_48da4c00-386"},"title":"Design Architect (PCIe/CXL Expert)","description":"<p>You are a visionary and highly experienced logic design expert with a passion for building next-generation hardware solutions. With a strong foundation in PCI Express (PCIe) and/or Compute Express Link (CXL) protocols, you thrive in challenging technical environments, pushing the boundaries of what’s possible in high-speed, complex SoC-class platforms. Your background combines deep hands-on expertise in FPGA architecture, RTL design, and hardware validation, making you a go-to leader for mission-critical projects. You excel at architecting robust, production-quality subsystems and are adept at navigating the intricacies of hardware/software co-design and debugging.</p>\n<p>You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.</li>\n<li>Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.</li>\n<li>Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.</li>\n<li>Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.</li>\n<li>Collaborating with R&amp;D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.</li>\n<li>Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.</li>\n<li>Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.</li>\n<li>Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.</li>\n<li>Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.</li>\n<li>Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.</li>\n<li>Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.</li>\n<li>12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.</li>\n<li>Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.</li>\n<li>7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.</li>\n<li>Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).</li>\n<li>Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.</li>\n<li>Experience in Unix/Linux development environments.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative team player with excellent communication skills and a global mindset.</li>\n<li>Proactive problem solver who thrives in dynamic, fast-paced environments.</li>\n<li>Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.</li>\n<li>Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.</li>\n<li>Adaptable and eager to stay updated with the latest industry trends and technologies.</li>\n<li>Customer-focused, with a dedication to supporting and enabling client success.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&amp;D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_48da4c00-386","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/design-architect-pcie-cxl-expert/44408/92113189568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["PCIe","CXL","FPGA","RTL design","hardware validation","Unix/Linux development environments","Xilinx FPGA experience","transceiver/SERDES integration","FPGA prototyping flows","SystemVerilog/Verilog","hardware development cycle","simulation","synthesis","timing analysis"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:02:24.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"PCIe, CXL, FPGA, RTL design, hardware validation, Unix/Linux development environments, Xilinx FPGA experience, transceiver/SERDES integration, FPGA prototyping flows, SystemVerilog/Verilog, hardware development cycle, simulation, synthesis, timing analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0341b889-f73"},"title":"ASIC Digital Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are looking for a hardware verification engineer who will perform verification of complex leading-edge security systems IP components. Be a part of a world-class team, building advanced security solutions that meet the Synopsys high quality standard for best-in-class products. These products are found in some of the most advanced, high-tech devices today in areas like automotive, networking, mobile, and IoT applications.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Performing design verification of cutting-edge IP components and subsystems used in high-profile security applications.</li>\n<li>Developing comprehensive product verification strategies, including test specifications, detailed test plans, and thorough test reports.</li>\n<li>Implementing, developing, and automating test environments for regression testing to ensure robust product quality.</li>\n<li>Collaborating closely with design engineers and architects to debug products and resolve defects efficiently.</li>\n<li>Staying current with the latest verification methodologies and tools, integrating state-of-the-art practices into your workflow.</li>\n<li>Hardware verification of IP cores and subsystems with techniques such as SystemVerilog /UVM and Formal Verification</li>\n<li>Proactively researching and integrating new developments in the domain of embedded security</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Proven expertise in verification of digital hardware IP components</li>\n<li>Deep technical knowledge of and experience with modern verification methodologies including UVM, assertion-based verification, coverage driven methodology and formal verification</li>\n<li>Good knowledge about IC Design flows and excellent problem solving and debugging skills</li>\n<li>Experience with verification flow automation and scripting.</li>\n<li>Strong communication (written and verbal) and interpersonal skills</li>\n<li>Bachelor’s or Master’s degree in Electrical Engineering or Computer Science, with 8+ years of relevant experience.</li>\n<li>Familiarity with security and cryptographic protocols is desirable.</li>\n</ul>\n<p><strong>What You’ll Be A Part Of</strong></p>\n<p>You’ll join the Security IP group in Ottawa, world-class, security-focused team of hardware and software engineers dedicated to advancing the best in security technologies. The team works collaboratively to design, verify, and deliver leading-edge security solutions found in the world’s most advanced devices, from automotive to IoT. Together, you’ll challenge the status quo and set new benchmarks in embedded systems security.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0341b889-f73","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/kanata/asic-digital-design-sr-staff-engineer-13965/44408/91391709936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["verification of digital hardware IP components","modern verification methodologies","IC Design flows","verification flow automation","scripting","security and cryptographic protocols"],"x-skills-preferred":["SystemVerilog","UVM","Formal Verification"],"datePosted":"2026-03-08T22:19:57.988Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Kanata, Ontario, Canada"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"verification of digital hardware IP components, modern verification methodologies, IC Design flows, verification flow automation, scripting, security and cryptographic protocols, SystemVerilog, UVM, Formal Verification"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_61448503-aa0"},"title":"Design Verification Engineer","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Design Verification Engineer</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$226K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team:</strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong> OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.</p>\n<p><strong>In this role you will:</strong></p>\n<ul>\n<li>Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.</li>\n</ul>\n<ul>\n<li>Define verification plans based on architecture and microarchitecture specs.</li>\n</ul>\n<ul>\n<li>Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.</li>\n</ul>\n<ul>\n<li>Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.</li>\n</ul>\n<ul>\n<li>Drive bug triage, root cause analysis, and work closely with design teams on resolution.</li>\n</ul>\n<ul>\n<li>Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.</li>\n</ul>\n<p><strong>You might thrive in this role if you have:</strong></p>\n<ul>\n<li>BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.</li>\n</ul>\n<ul>\n<li>Proven success verifying complex IP or SoC designs in industry-standard flows</li>\n</ul>\n<ul>\n<li>Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).</li>\n</ul>\n<ul>\n<li>Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.</li>\n</ul>\n<ul>\n<li>Familiarity with performance modeling, formal verification, or emulation is a plus.</li>\n</ul>\n<ul>\n<li>Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_61448503-aa0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/3a415c1d-4f66-4578-8eb3-8b15ef0ab52b","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$226K – $445K • Offers Equity","x-skills-required":["SystemVerilog","UVM","VCS","Questa","Verdi","BS/MS in EE/CE/CS or equivalent","3+ years of experience in hardware verification","Proven success verifying complex IP or SoC designs in industry-standard flows"],"x-skills-preferred":["Computer architecture concepts","Memory and cache systems","Coherency","Interconnects","ML compute primitives","Performance modeling","Formal verification","Emulation"],"datePosted":"2026-03-06T18:41:15.010Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SystemVerilog, UVM, VCS, Questa, Verdi, BS/MS in EE/CE/CS or equivalent, 3+ years of experience in hardware verification, Proven success verifying complex IP or SoC designs in industry-standard flows, Computer architecture concepts, Memory and cache systems, Coherency, Interconnects, ML compute primitives, Performance modeling, Formal verification, Emulation","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":226000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_568dcff2-ed1"},"title":"RTL & Co-design Engineer (junior)","description":"<p><strong>RTL &amp; Co-design Engineer (junior)</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_568dcff2-ed1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/77b815de-b7c5-4b87-8582-e8c752aea849","x-work-arrangement":"hybrid","x-experience-level":"junior","x-job-type":"full-time","x-salary-range":"$225K – $445K • Offers Equity","x-skills-required":["RTL","Verilog","SystemVerilog","Computer Architecture","AI/ML Hardware–Software Co-design","Workload Analysis","Dataflow Mapping","Accelerator Algorithm Optimization","Hardware Design Models","Architectural Simulators","Industry-standard Design Tools","Lint","CDC/RDC","Synthesis","STA","Methodologies"],"x-skills-preferred":[],"datePosted":"2026-03-06T18:39:06.360Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL, Verilog, SystemVerilog, Computer Architecture, AI/ML Hardware–Software Co-design, Workload Analysis, Dataflow Mapping, Accelerator Algorithm Optimization, Hardware Design Models, Architectural Simulators, Industry-standard Design Tools, Lint, CDC/RDC, Synthesis, STA, Methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":225000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d094148d-0e0"},"title":"RTL & Codesign Engineer","description":"<p><strong>Job Posting</strong></p>\n<p><strong>RTL &amp; Codesign Engineer</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. 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The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong>About the Role</strong></p>\n<p>You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. 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