Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:\nYou are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.
\nYou are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.
\nWhat You’ll Be Doing:\nSpecify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\nDevelop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\nDesign, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\nPerform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\nCollaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\nLeverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\nContribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.
\nThe Impact You Will Have:\nEnsure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\nDrive innovation in verification methodologies, setting new standards for efficiency and coverage.\nEnhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\nStrengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\nMentor and support junior engineers, fostering a culture of learning and continuous improvement.\nContribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.
\nWhat You’ll Need:\nBSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\nExpertise in developing HVL (System Verilog)-based verification environments and testbenches.\nStrong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\nProficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\nSolid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\nFamiliarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\nDemonstrated ability to work with functional coverage-driven methodologies and quality metric goals.
\nWho You Are:\nAnalytical thinker with strong problem-solving and debugging skills.\nExcellent verbal and written communication abilities.\nTeam player who thrives in collaborative, multi-site environments.\nProactive, self-motivated, and able to take initiative on challenging projects.\nDetail-oriented, quality-focused, and driven by a desire to excel.\nAdaptable and eager to continuously learn and apply new technologies.
\nThe Team You’ll Be A Part Of:\nYou will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.
\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
\nBenefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nAs a Senior Staff Engineer in RTL Design and Verification, you will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance.
\nYou will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.
\nYou will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.
\nYou will participate in code reviews and technical discussions to drive innovation and continuous improvement.
\nYou will accelerate the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions.
\nYou will drive innovation in verification methodologies, setting new standards for efficiency and accuracy. You will enable successful integration of advanced 3D-IC technologies, expanding Synopsys' leadership in the market.
\nYou will foster strong customer relationships through technical expertise and responsive support. You will contribute to a culture of excellence and continuous learning within the engineering team.
\nTo succeed in this role, you will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will require 8+ years of hands-on experience in RTL design and verification.
\nYou will need proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. You will need experience working in Unix/Linux environments.
\nYou will need strong debugging and problem-solving skills, especially in complex chip design environments. You will need excellent written and verbal communication skills in English.
\nKnowledge of digital, analog, and mixed-signal IP/circuit design is a plus. Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.
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\nResponsibilities:
\nCollaborate with R&D architects and customers on hardware-assisted verification products.
\nDrive all aspects of the technology life cycle, from development to product sign-off and customer deployment.
\nDefine test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.
\nBecome an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.
\nLeverage your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.
\nAdapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.
\nWork with designs from varied verticals to enable and support key ZeBu products in early-stage development.
\nThe Impact You Will Have:
\nEnhance Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.
\nImprove the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.
\nProvide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.
\nEnsure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.
\nSupport the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.
\nFacilitate the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.
\nWhat You’ll Need:
\nBSEE/MS with 7+ years of related experience.
\nExpertise in Emulation and/or Prototyping flows, systems, and methodologies.
\nStrong proficiency in Verilog, System Verilog, and VHDL.
\nUnderstanding of verification concepts and experience with functional simulators.
\nExperience with scripting languages.
\nKnowledge in Simulation flows, Assertion, DPI, and Transactors.
\nComplex problem-solving and debugging skills.
\nStrong communication skills and the ability to interact with customers and peers.
\nKnowledge in synthesis and timing analysis concepts (preferred).
\nFamiliarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).
\nExperience with Xilinx & Altera architecture and toolchains (preferred).
\nUnderstanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nAs an effective communicator, you will clearly articulate technical concepts to both internal teams and external customers, fostering strong partnerships and driving innovation. You will be adaptable, self-motivated, and resilient in the face of challenges, always seeking opportunities to learn and grow.
\nYour responsibilities will include designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance. You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.
\nYou will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.
\nYou will participate in code reviews and technical discussions to drive innovation and continuous improvement.
\nThe impact you will have includes accelerating the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions. You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy.
\nYou will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will have 5+ years of hands-on experience in RTL design and verification. You will be proficient in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
\nYou will be an analytical and critical thinker with a detail-oriented approach. You will be an effective communicator, comfortable collaborating across teams and with customers. You will be self-motivated and proactive in seeking solutions and driving projects forward.
\nYou will join a talented and diverse engineering team focused on developing and verifying cutting-edge Silicon Lifecycle Management IPs for next-generation chip solutions.
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\nAs a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
\nKey responsibilities include:
\nThe impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.
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\nAs a Senior Manager of SOC Engineering, you will oversee and drive end-to-end RTL design, verification, architecture, and integration of advanced subsystems. You will lead teams in Bangalore/Hyderabad, manage customer communications, and ensure timely, high-quality delivery. You will guide your team through the full lifecycle: from requirements to release, ensuring excellence at every stage. Foster innovation and continuous improvement, motivating engineers to reach their full potential.
\nKey Qualifications:
\nWhat Sets You Apart:
\nHands-on experience is an absolute must for success in this role.
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\nThis role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
\nKey responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.
\nThe ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.
\nAs a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.
\nIn this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.
\nSynopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work.
\nWe consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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\nYou are an experienced verification architect who thrives on technical leadership and mentoring others. You excel in digital design and verification, enjoy collaborating with global teams, and are motivated by delivering high-quality solutions. Your expertise includes System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. You’re proactive, inclusive, and passionate about process improvement and innovation.
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\nThe Impact You Will Have:\nEnsure robust verification for complex ASIC and IP designs.\nSupport first-silicon success and faster time-to-market.\nElevate team skills and technical excellence.\nChampion best verification practices and tools.\nEnhance collaboration across global teams.\nPromote continuous improvement in verification processes.
\nWhat You’ll Need:\nBSEE or MSEE with at least 12+ years of direct industry experience in digital design verification with System Verilog, Verilog, or VHDL.\nExpertise in UVM and coverage-driven RTL verification.\nProficiency in scripting and programming (Python, Perl, C/C++).\nAbility to define verification plans and architect testbenches.\nExperience with 200G SerDes verification is an asset.
\nWho You Are:\nCollaborative leader and effective communicator.\nMentor who empowers others.\nAnalytical, detail-oriented problem solver.\nAdaptable and innovative.
\nThe Team You’ll Be A Part Of:\nJoin a diverse, world-class engineering team dedicated to delivering industry-leading verification solutions for next-generation semiconductor products.
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\nYou Are:
\nAn enthusiastic and detail-oriented ASIC Digital Design Verification Engineer with a passion for cutting-edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high-level requirements into robust and efficient designs. Your expertise, coupled with your strong understanding of digital design and verification methodologies, makes you an invaluable asset to any project. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges, and delivering innovative solutions. You are proactive, with excellent communication skills that enable you to work effectively with cross-functional teams. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements.
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\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.
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\nAs a Mixed-Signal Verification Engineer, you will contribute to the overall reliability and performance of SERDES deliverables by surfacing system-level issues and supporting their resolution.
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\nYou are a passionate and driven R&D Engineer with a deep understanding of data structures, algorithms, and their applications. You have a strong background in software development, particularly with C/C++ on UNIX/Linux platforms, and are eager to tackle complex, large-scale software code-based tool development. With a minimum of 8 years of related experience, you have honed your analytical, debugging, and problem-solving skills. You thrive in both self-directed and collaborative environments and are committed to continuous learning and exploration of new technologies. Your excellent communication skills in English enable you to effectively collaborate with team members and present your ideas clearly.
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\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.
\nAs a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.
\nYou will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.
\nYou will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.
\nYou will develop and implement advanced test plans and test environments at both unit and system levels.
\nYou will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
\nYou will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.
\nYou will manage regressions and contribute to the continuous improvement of verification strategies and test environments.
\nThis role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.
\nYou should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.
\nYou should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.
\nYou should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.
\nYou should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.
\nYou should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.
\nYou should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.
\nYou will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.
\nThe team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.
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\nToday, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.
\nAs a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
\nResponsibilities:
\nRequirements:
\nNVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.
\nYou will also be eligible for equity and benefits.
\nApplications for this job will be accepted at least until March 13, 2026.
\nThis posting is for an existing vacancy.
\nNVIDIA uses AI tools in its recruiting processes.
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\nWe are seeking a highly skilled ASIC Security Staff Engineer to join our team at Synopsys. As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.
\nJob Description
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nYou Are:
\nYou are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.
\nTechnical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.
\nYou bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity:
\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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\nYou are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.
\nCollaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.
\nEnable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.
\nMaster’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.
\nCollaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.
\nYou’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nDate posted 02/24/2026
\nCategory EngineeringHire Type EmployeeJob ID 15312Remote Eligible NoDate Posted 02/24/2026
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are an ambitious and detail-oriented engineering professional with a passion for digital verification and ASIC design. You thrive in dynamic and diverse environments, bringing a collaborative spirit and a strong eagerness to learn. Your background in electronics engineering equips you with deep technical expertise, and your experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs sets you apart. You approach challenges with a solution-oriented mindset and are adept at diagnosing intricate issues efficiently. You are comfortable working across multiple verification platforms and methodologies, and you enjoy mentoring and sharing knowledge within your team. Your adaptability enables you to keep pace with evolving technologies, and you value inclusion, diversity, and continuous improvement. You are motivated by the opportunity to contribute to groundbreaking innovations in the silicon IP domain, and you are committed to delivering quality results that help bring differentiated products to market quickly. If you are excited by the chance to be at the forefront of smart technology—powering everything from AI to IoT—you will find your next challenge here at Synopsys.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will join a high-performing Silicon IP engineering team that specializes in developing and verifying advanced digital design blocks for integration into SoCs. Our team values innovation, collaboration, and knowledge sharing, working together to deliver industry-leading solutions for customers worldwide. We are passionate about technology and driven by the success of our products and people.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
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\nWorkplace Resources, Sr Director
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\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nGet an idea of what your daily routine around the office can be like
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\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nSenior Digital Verification Engineer
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements, and get differentiated products to market quickly with reduced risk. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are a driven Digital Verification Engineer with a passion for technology and innovation. You thrive on tackling complex verification challenges and excel in pre-silicon functional verification of high-speed PHY IPs. Your strong foundation in RTL enables you to develop robust verification environments, and your eagerness to learn keeps you at the forefront of industry advancements. You possess a dynamic personality that brings energy to your team, and you’re adept at collaborating with diverse colleagues. You take ownership of verification activities, from creating comprehensive test plans and test cases to implementing advanced checkers and assertions. Your diagnostic and problem-solving skills are exceptional, allowing you to quickly analyze failures and optimize verification flows. You are comfortable with industry-standard tools and methodologies, and you enjoy working in environments that require both independent initiative and teamwork. Your familiarity with scripting languages and high-speed interface protocols further enhances your versatility. If you are ready to lead verification efforts that power the Era of Smart Everything, Synopsys is the place where your skills and passion will make a lasting impact.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nThe Team You’ll Be A Part Of:
\nYou will be part of a highly skilled Silicon IP engineering team focused on delivering robust verification solutions for high-speed PHY interfaces. The team is composed of experts in digital design, verification, and architecture, working collaboratively to solve complex challenges and push the boundaries of semiconductor technology. Together, you will contribute to the development of industry-leading products that power the next generation of intelligent devices.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
\n\\\\ Benefits vary by country and region - check with your recruiter to confirm
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\nYou Are:
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\nA technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.
\nYou bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.
\nWhat You'll Be Doing:
\nThe Impact You Will Have:
\nWhat You'll Need:
\n15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.
\nBe results driven
\nProven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
\nAdvanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
\nIn-depth knowledge of system-level validation for high-speed interface PHY
\nProven track record of working cross-functionally and driving issues to closure
\nKnowledge of mixed-signal design
\nExperience in working in cross-functional collaborations
\nBe an excellent communicator and a beacon for change
\nExcellent debugging, analytical, and problem-solving skills
\nWorking knowledge of scripting in languages such as Python and/or Perl
\nGood understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon
\nGood interpersonal skills, ability & desire to work as a standout colleague
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nInclusion and Diversity:
\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
\n#LI-DP1
\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
\nBenefits:
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nWhat you need
\nWhy this matters
\nWhat you'll be doing
\nWhy you'll love this role
\nWhat you'll need to succeed
\nHow to apply
\nBenefits
\nHow we hire
\nJoin our team
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\nWhat you'll do
\nSpecifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.
\nPerforming verification tasks for IP cores, including test planning and environment coding at both unit and system levels.
\nDeveloping and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.
\nManaging regression and ensuring adherence to verification methodologies.
\nCollaborating closely with RTL designers and a global team of verification engineers.
\nWorking on next-generation connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you need
\nBSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.
\nExperience in architecting verification environments for complex serial protocols.
\nProficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.
\nExpertise in verification methodologies such as VMM, OVM, and UVM.
\nKnowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.
\nFamiliarity with Verilog and scripting languages such as Perl, TCL, and Python.
\nExperience with IP design and verification processes, including VIP development.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_e21ac2ad-394","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-verification-principal-engineer/44408/77023412560","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["HVL (System Verilog)","industry-standard simulators","verification methodologies","protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB","HDLs like Verilog","scripting languages such as Perl, TCL, and Python"],"x-skills-preferred":["VIP development"],"datePosted":"2025-12-22T12:04:28.502Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Brackley"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"HVL (System Verilog), industry-standard simulators, verification methodologies, protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB, HDLs like Verilog, scripting languages such as Perl, TCL, and Python, VIP development"}]}