As a Container Washer, you'll play a crucial role in ensuring the cleanliness and quality of our production processes.

Responsibilities:

• Clean containers, pallets, stainless steel vessels, and washing equipment according to standard operating procedures
• Clean rooms and facilities according to standard operating procedures
• Document cleaning activities according to standard operating procedures
• Conduct inventory checks of cleaning materials after a set period
• Operate computerized cleaning systems and monitor system status, using software from the production control system
• Report any issues and assist in identifying problems
• Transport equipment within the facility and operate the automated transportation system
• Maintain safety standards and support improvements

Requirements:

• 6-12 months of work experience
• Ideally, experience in pharmaceutical production
• Knowledge of production processes
• IT skills for using standard software
• Strong quality awareness and technical understanding
• Proactive, reliable, and team-oriented with high levels of personal responsibility
• Excellent German language skills (written and spoken)
• Willingness to work in shift operations

What We Offer:

• Competitive salary of €3,307 per month (full-time) plus annual bonus, holiday pay, and Christmas bonus/13th month pay
• Opportunities for professional development through access to learning platforms such as LinkedIn Learning and Education First
• Support for health and well-being
• Sustainable mobility options, including job ticket and leased company bicycles
• Access to exclusive benefits and discounts from over 150 brands through our Corporate Benefits Program
• Celebrating diversity in an inclusive work environment where you're welcome, supported, and encouraged to bring your whole self to work

This is a 2-year fixed-term position with the possibility of extending.

XML job scraping automation by YubHub

They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Responsibilities

• Design, implement, and optimize compilation algorithms for mapping large-scale processor hardware descriptions onto the ZeBu emulator
• Develop scalable solutions to handle multi-billion-gate designs within tight runtime and memory constraints
• Apply advanced problem-solving skills to debug complex compilation, placement, and performance issues
• Develop and maintain high-quality, modular, and extensible object-oriented software in C++
• Collaborate closely with hardware architects, performance engineers, and emulator platform teams to ensure seamless integration and performance
• Contribute to continuous improvement of compilation flows, algorithms, and infrastructure for enhanced efficiency and robustness
• Participate in code reviews, design discussions, and knowledge sharing sessions with the broader engineering community

Impact

• Enable leading semiconductor companies to verify next-generation processor designs before commercialization
• Drive performance and scalability improvements, reducing compile and placement times for massive hardware designs
• Advance state-of-the-art compilation technologies in emulation, directly shaping the future of chip verification
• Enhance robustness and reliability of the ZeBu emulation platform, ensuring successful deployment in real-world scenarios
• Foster innovation and collaboration within the ZeBu Compiler Team and across Synopsys engineering groups
• Support industry leaders in achieving faster time-to-market for their products through efficient emulation workflows
• Champion best practices in software engineering, contributing to the overall quality and maintainability of the codebase

Requirements

• 3-5 years of relevant experience
• Strong skills in problem solving and algorithmic thinking, with proven experience in tackling challenging technical problems
• Solid expertise in object-oriented programming (preferably C++)
• Deep understanding of data structures and algorithms, with the ability to design efficient and scalable solutions
• Experience working with complex systems and large codebases
• Strong analytical skills and meticulous attention to detail
• Exposure to performance optimization, memory efficiency, or parallel computing (preferred)
• Familiarity with hardware description languages (Verilog, SystemVerilog, VHDL) (preferred)
• Experience with emulation, FPGA, EDA tools, or large-scale system software (preferred)

Team

You’ll join the ZeBu Compiler Team,a group of passionate engineers dedicated to advancing emulation technology for the world’s leading semiconductor companies. The team focuses on developing innovative compilation algorithms, scalable software solutions, and robust infrastructure to enable efficient verification of massive hardware designs. Collaboration, knowledge sharing, and a commitment to excellence define the team’s culture, empowering each member to make a meaningful impact.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $266K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are seeking a highly skilled cross-stack power architect with deep expertise in making ML systems energy efficient. This hands-on individual contributor will sit within our silicon implementation team and work closely with architecture, kernels, chip design, silicon implementation, platform design, and the broader industry ecosystem to architect, implement, and deploy performance-per-watt optimized next-generation AI accelerator chips and systems.

In this role, you will:

• Oversee power architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to maximize performance under power envelope

• Build chip and system-level power models grounded in empirical data and experience to guide organization-wide energy efficiency strategy. This requires a detailed understanding of ML workloads, ML chip and system architecture, silicon design, implementation, and characterization

• Collaborate with chip and platform architecture/design teams to explore and implement power management features, including the specification and implementation of digital/mixed-signal IP, sensing and telemetry, firmware/system software, and silicon characterization methodology (in partnership with engineering teams)

• Partner with silicon design and implementation teams, to optimize performance under power envelope. This includes (but is not limited to) clocking and power domain architecture, voltage/frequency selection, microarchitecture and physical-design driven power reduction, post-silicon voltage margin optimization and workload-informed power optimization

• Work with ecosystem partners (EDA, ASIC, IP, component vendors) to drive innovations that can improve energy efficiency

Qualifications:

• Relevant degree and strong industry experience focused on the end-to-end energy-efficient ML silicon codesign

• Hands-on experience with power architecture, power estimation, power management and power optimization is required.

• Fundamental understanding of ML chip and platform architecture, performance modeling and workload power/performance characteristics is strongly preferred.

• Hands-on experience with power bring-up and power validation is strongly preferred.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

About the Role

We are seeking a highly skilled cross-stack engineer with deep expertise in making ML systems reliable at scale. This hands-on individual contributor will sit within our hardware team and work closely with chip design, platform design, hardware health, and the broader industry ecosystem to architect, implement, and deploy reliable next-generation AI accelerator systems.

Responsibilities

• Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware.

• Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability.

• Collaborate with chip and platform architecture/design teams to explore and implement DFX features, including the specification and implementation of digital/mixed-signal IP, firmware/system software, and DFX methodology (in partnership with engineering teams).

• Partner with hardware health and platform design teams to continuously improve reliability and fault tolerance in NPI and HVM. This includes optimizing operating conditions, designing experiments, and performing data analysis to drive continuous, data-driven improvements across the stack.

• Serve as the DFX/reliability champion and evangelist to align the broader industry ecosystem with OpenAI’s requirements and roadmap.

Qualifications

• BS with 15+ years, MS with 10+ years, or PhD with 3+ years of relevant industry experience focused on reliability across the chip/platform stack.

• Hands-on experience with RTL design and DFT is required; physical implementation and/or silicon ATE experience is preferred.

• Detailed understanding of ML chip and platform architecture and ML workload characteristics is required.

• Strong fundamentals in reliability modeling, with hands-on skills in empirical data analysis.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

Microsoft AI are looking for a talented Member of Technical Staff, Software Co-Design AI HPC Systems at their Zürich office. This role sits at the boundary between exploration and production. You will work closely with internal infrastructure, hardware, compiler, and product teams, as well as external partners across the hardware and systems ecosystem.

About the Role

Our team's mission is to architect, co-design, and productionize next-generation AI systems at datacenter scale. We operate at the intersection of models, systems software, networking, storage, and AI hardware, optimizing end-to-end performance, efficiency, reliability, and cost. Our work spans today's frontier AI workloads and directly shapes the next generation of accelerators, system architectures, and large-scale AI platforms. We pursue this mission through deep hardware–software co-design, combining rigorous systems thinking with hands-on engineering.

Accountabilities

• Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks.
• Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements.

The Candidate we're looking for

Experience:

• Minimum 5 years of experience in software engineering, systems software, or a related field.

Technical skills:

• Proficiency in C++, Python, and/or other programming languages.
• Experience with AI frameworks, such as TensorFlow or PyTorch.
• Familiarity with hardware design and development.

Personal attributes:

• Strong problem-solving skills and attention to detail.
• Excellent communication and collaboration skills.

Benefits

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

XML job scraping automation by YubHub