{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/synthesis"},"x-facet":{"type":"skill","slug":"synthesis","display":"Synthesis","count":72},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. 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You will use Claude aggressively, creatively, and daily, to help you surface insights about what Anthropic is doing with regard to these problem areas.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Research how Anthropic&#39;s teams are working on the Institute&#39;s challenges and synthesize findings from across the organization into a coherent picture.</li>\n<li>Partner with teams to help them surface their insights to the world, often working to act as the &#39;connective tissue&#39; between them and other teams to bring different insights together.</li>\n<li>Produce written analysis and memos about how Anthropic is approaching these problems,for both internal leadership and public audiences.</li>\n<li>Partner with relevant teams to develop and publish public outputs.</li>\n<li>Come up with creative ways to carry our work into the world: sometimes the most impactful way to talk about an issue is through a technical demonstration rather than a blog post or research paper (e.g, Golden Gate Claude, Project Vend, Robodog).</li>\n</ul>\n<p><strong>What We&#39;re Looking For</strong></p>\n<ul>\n<li>7+ years of experience in technical policy research, think tank work, or applied research in a domain relevant to the Institute&#39;s focus areas (AI, labor economics, national security, or emerging technology governance).</li>\n<li>Track record of publishing or producing work for external audiences,whether policy memos, research reports, white papers, or public-facing analysis.</li>\n<li>Comfort operating at the intersection of technical and policy audiences. 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However, we aren&#39;t able to successfully sponsor visas for every role and every candidate. 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We&#39;re building on frontier models that evolve constantly, serving customers from individual developers to the largest enterprises, across multiple surfaces (API, claude.ai, Claude Code).</p>\n<p>Customer signal arrives from everywhere , field conversations, support interactions, early access programs, in-product telemetry , and the opportunity is to make that signal a first-class, structured input to every product and research decision.</p>\n<p>You treat feedback loops as a product. You&#39;re obsessed with making it effortless for the field to share what they&#39;re hearing and for product teams to know what matters most.</p>\n<p>You build AI-enabled systems that do the first pass so humans can focus on judgment, not triage. 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Obsess over the submitter experience so that sharing feedback is faster than not sharing it.</li>\n</ul>\n<p><strong>AI-Enabled Synthesis &amp; Triage</strong></p>\n<ul>\n<li>Build Claude-powered pipelines that enrich, tag, cluster, and summarize unstructured feedback into trackable issues , doing the first-pass work so humans focus on verification and judgment.</li>\n</ul>\n<ul>\n<li>Design the human-in-the-loop model: Claude proposes, PMs and field teams correct, and the system learns from those corrections over time.</li>\n</ul>\n<ul>\n<li>Partner with Engineering and Research on tooling strategy, evals, and the closed-loop data that makes synthesis quality measurably improve.</li>\n</ul>\n<p><strong>Routing &amp; Closing the Loop</strong></p>\n<ul>\n<li>Establish clear routing so the right feedback reaches the right product or research owner at the right time , including the path from product signal back into model training priorities.</li>\n</ul>\n<ul>\n<li>Build the visibility layer that gives GTM and Support a clear line of sight from customer input to roadmap outcome, so they can close the loop with customers confidently and in real time.</li>\n</ul>\n<p><strong>Voice of the Customer Programs</strong></p>\n<ul>\n<li>Partner deeply with GTM, Customer Success, and Sales to design and run structured voice of the customer programs , customer advisory boards, early access programs, design partner cohorts , that generate high-signal feedback by design.</li>\n</ul>\n<ul>\n<li>Define what &#39;high-signal&#39; means: feedback tied to specific use cases, blocker severity, revenue context, and customer segments so product teams can make confident tradeoffs.</li>\n</ul>\n<p><strong>Continuous Improvement</strong></p>\n<ul>\n<li>Define and track success metrics for feedback loop health , time-to-triage, signal quality, roadmap influence, field satisfaction , and use them to identify bottlenecks.</li>\n</ul>\n<ul>\n<li>Run regular retros with Product and GTM partners and feed learnings back into process and tooling improvements. Scale what works through documentation and enablement.</li>\n</ul>\n<p><strong>You may be a good fit if you:</strong></p>\n<ul>\n<li>Have 7+ years in product operations, customer insights, voice of the customer programs, or related roles in fast-paced tech companies.</li>\n</ul>\n<ul>\n<li>Have personally shipped AI-enabled processes and systems , you&#39;ve written the prompts, built the evals, and iterated on production LLM workflows yourself.</li>\n</ul>\n<ul>\n<li>Have owned a customer feedback program end-to-end , intake, synthesis, routing, and closing the loop , that product teams actually used to make decisions.</li>\n</ul>\n<ul>\n<li>Have operated at earlier-stage and scaling companies (Series B-D or equivalent) where you built things that didn&#39;t exist yet, shipped v1s in weeks not quarters, and iterated in public.</li>\n</ul>\n<ul>\n<li>Have operated in horizontal, cross-org roles before , you know how to build shared infrastructure that many teams depend on, drive adoption through influence rather than mandate, and earn trust across functions that don&#39;t report to you.</li>\n</ul>\n<ul>\n<li>Are comfortable with ambiguity and can create structure where none exists , you&#39;ve built the v1 of a system and iterated it into something teams rely on.</li>\n</ul>\n<ul>\n<li>Are service-oriented and obsessed with making it easy for others to do great work.</li>\n</ul>\n<p><strong>Strong candidates may also have experience with:</strong></p>\n<ul>\n<li>Building AI-native workflows end-to-end , prompt design, evals, closed-loop improvement , and pushing the boundaries of what automation can own.</li>\n</ul>\n<ul>\n<li>Product Management, Customer Success Operations, or Research Operations.</li>\n</ul>\n<ul>\n<li>Feedback tooling ecosystems (Productboard, Dovetail, or homegrown equivalents) and the tradeoffs between buy vs. build.</li>\n</ul>\n<ul>\n<li>Treating process as a product with users, metrics, and continuous iteration.</li>\n</ul>\n<ul>\n<li>Track record of building and scaling operations programs from zero to one.</li>\n</ul>\n<p>Annual compensation range for this role is $260,000-$325,000 USD</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_47588e09-b9f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://www.anthropic.co/","logo":"https://logos.yubhub.co/anthropic.co.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/5179882008","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$260,000-$325,000 USD","x-skills-required":["AI-enabled processes","Customer insights","Voice of the customer programs","Product operations","Customer feedback","Synthesis and triage","Routing and closing the loop","Continuous improvement","Metrics tracking","Process management"],"x-skills-preferred":["Prompt design","Evals","Closed-loop improvement","Automation","Product management","Customer success operations","Research operations","Feedback tooling ecosystems","Process as a product","Metrics-driven approach"],"datePosted":"2026-04-18T15:44:07.529Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA | New York City, NY"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"AI-enabled processes, Customer insights, Voice of the customer programs, Product operations, Customer feedback, Synthesis and triage, Routing and closing the loop, Continuous improvement, Metrics tracking, Process management, Prompt design, Evals, Closed-loop improvement, Automation, Product management, Customer success operations, Research operations, Feedback tooling ecosystems, Process as a product, Metrics-driven approach","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":260000,"maxValue":325000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_404f2fc5-74b"},"title":"Talent Acquisition Specialist (12 month FTC)","description":"<p>About Us</p>\n<p>Artificial Intelligence could be one of humanity&#39;s most useful inventions. At Google DeepMind, we&#39;re a dedicated scientific community, committed to building AI responsibly to benefit humanity.</p>\n<p>The Role</p>\n<p>This role provides support for initiatives across the global TA function supporting Research hiring. You&#39;ll focus on our goal of attracting and securing world-class talent for the business in partnership with Recruitment and a range of stakeholders across the business.</p>\n<p>Responsibilities</p>\n<ul>\n<li>Identification and engagement of global Research talent through utilization of AI tools and in collaboration with our own leading researchers.</li>\n<li>Support with program planning of initiatives designed to engage new talent</li>\n<li>Identify talent maps and key competitor insights, specifically focused on GDM&#39;s top competing AI labs.</li>\n<li>Proactive candidate outreach to meet our recruitment objectives.</li>\n<li>Partner with the TA Leader to provide relevant talent insights and market intel. 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For more information on how we handle your data, please see our Applicant and Candidate Privacy Policy</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_404f2fc5-74b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Google DeepMind","sameAs":"https://deepmind.com/","logo":"https://logos.yubhub.co/deepmind.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/deepmind/jobs/7786257","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$111,000 USD - $159,000 USD + bonus + benefits","x-skills-required":["AI","talent acquisition","recruitment","hiring","candidate outreach","market intel","data analysis","synthesis","insights"],"x-skills-preferred":["Google Cloud","machine learning","natural language processing","data science"],"datePosted":"2026-04-18T15:41:10.163Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mountain View, California, US"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"AI, talent acquisition, recruitment, hiring, candidate outreach, market intel, data analysis, synthesis, insights, Google Cloud, machine learning, natural language processing, data science","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":111000,"maxValue":159000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e773fe15-1bb"},"title":"Finance Expert - Macro Research Analyst","description":"<p>As a Macro Research Analyst at xAI, you will play a critical role in analysing global economic forces and translating complex macroeconomic dynamics into actionable insights.</p>\n<p>You will track and interpret key economic indicators across regions, assess the implications of monetary and fiscal policy decisions, and evaluate how macro trends shape financial markets and risk conditions.</p>\n<p>This role sits at the intersection of economics, markets, and strategic decision-making.</p>\n<p>You will build forecasts and scenario analyses to understand how shifts in growth, inflation, interest rates, currencies, commodities, and geopolitics may affect asset prices and broader market regimes.</p>\n<p>Your work will inform top-down investment views and risk assessments, supporting global macro strategies driven by economic fundamentals rather than individual company analysis.</p>\n<p>The ideal candidate is intellectually curious, analytically rigorous, and comfortable working in a fast-moving, high-ownership environment.</p>\n<p>Consistent with xAI&#39;s flat organisational structure, you are expected to be hands-on, proactive, and able to communicate ideas clearly and concisely to a highly technical and motivated team.</p>\n<p>As a Macro Research Analyst, you will contribute directly to this mission by helping the organisation understand large-scale economic systems, feedback loops, and regime shifts that shape global outcomes.</p>\n<p>You will structure, analyse, and interpret macroeconomic data across countries and regions, transforming noisy and often incomplete information into coherent economic narratives and testable hypotheses.</p>\n<p>Your research will help identify causal relationships, constraints, and second-order effects within complex economic systems,insights that are essential for training, evaluating, and applying advanced AI models to real-world economic and financial questions.</p>\n<p>By developing forecasts, scenarios, and risk assessments, you will support xAI&#39;s efforts to reason about uncertainty, stress-test assumptions, and evaluate how shocks propagate through global markets and institutions.</p>\n<p>Clear communication of your findings will ensure that economic insights are effectively shared across teams, reinforcing xAI&#39;s emphasis on rigorous thinking, transparency, and collaborative problem-solving.</p>\n<p>In this role, macroeconomic research is not an end in itself, but a tool for advancing deeper understanding.</p>\n<p>Your work will help xAI build systems that reason more accurately about economic behaviour, policy trade-offs, and global dynamics,bringing us closer to AI that can meaningfully assist human decision-making at scale.</p>\n<p>The Macro Research Analyst will have broad responsibility for analysing global macroeconomic conditions and their implications for financial markets and strategic decision-making.</p>\n<p>The scope of the role spans data analysis, economic modelling, and synthesis of macroeconomic developments across multiple regions and asset classes.</p>\n<p>The role includes management of ongoing monitoring frameworks for key economic indicators, policy developments, and geopolitical risks.</p>\n<p>The analyst will be expected to independently identify emerging themes, develop forward-looking scenarios, and assess how macroeconomic shifts may alter market dynamics, risk exposures, and opportunity sets.</p>\n<p>The position requires close collaboration with internal stakeholders, with an emphasis on clear, concise communication of complex economic concepts.</p>\n<p>Given xAI&#39;s flat organisational structure, the analyst will operate with a high degree of autonomy and accountability, contributing directly to research outputs and strategic discussions rather than functioning in a narrow support capacity.</p>\n<p>The scope of the role is intentionally flexible, allowing a high-performing analyst to expand their responsibilities over time by taking ownership of new research areas, developing novel analytical frameworks, and influencing how macroeconomic intelligence is integrated into xAI&#39;s broader mission.</p>\n<p>Responsibilities:</p>\n<p>Monitor and interpret data such as GDP growth, inflation, unemployment rates, interest rates, fiscal/monetary policy, currency movements, commodity prices, and geopolitical events across countries or regions.</p>\n<p>Build economic forecasts, scenario analysis, and models to predict how macro forces will affect markets (e.g., how a central bank rate hike might impact equities, bonds, or currencies).</p>\n<p>Provide research reports, trade ideas, and recommendations to portfolio managers, traders, or clients. This often informs &#39;global macro&#39; investment strategies, where decisions are driven primarily by top-down economic views rather than individual company fundamentals.</p>\n<p>Identify potential risks (e.g., recessions, currency crises, trade wars) and opportunities arising from economic shifts.</p>\n<p>Basic Qualifications:</p>\n<p>Strong academic background in economics, finance, mathematics, statistics, or a related quantitative field.</p>\n<p>Demonstrated experience in macroeconomic research, global macro investing, economic policy analysis, or a closely related role.</p>\n<p>Deep understanding of macroeconomic indicators and frameworks, including growth, inflation, labor markets, monetary and fiscal policy, exchange rates, commodities, and geopolitical dynamics.</p>\n<p>Experience building and interpreting economic models, forecasts, and scenario analyses to assess market and policy outcomes.</p>\n<p>Ability to synthesise large and complex data sets into clear, structured insights and actionable conclusions.</p>\n<p>Strong written and verbal communication skills, with the ability to explain complex economic concepts concisely to both technical and non-technical audiences.</p>\n<p>High level of intellectual curiosity and comfort working with uncertainty, incomplete information, and competing hypotheses.</p>\n<p>Self-directed, detail-oriented, and capable of operating effectively in a flat organisational structure with minimal oversight.</p>\n<p>Proven ability to prioritise effectively, manage multiple research streams, and deliver high-quality work under time constraints.</p>\n<p>Preferred Skills and Experience:</p>\n<p>3–7 years of experience post-doc.</p>\n<p>At least three publications in reputable economics journals (AER, QRE, JPE, Econometrica, etc.) or outlets (The Economist, The Wall Street Journal, Financial Times, etc.).</p>\n<p>Prior experience at a global macro hedge fund, asset manager, central bank, international financial institution, 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macroeconomic developments, financial markets, strategic decision-making, economic indicators, fiscal/monetary policy, currency movements, commodity prices, geopolitical events, forecasting, scenario analysis, model building, research reports, trade ideas, recommendations, portfolio management, trading, clients, global macro investment strategies, top-down economic views, individual company fundamentals, risk assessment, opportunity identification, emerging themes, forward-looking scenarios, market dynamics, risk exposures, opportunity sets, collaboration, communication, complex economic concepts, autonomy, accountability, research outputs, strategic discussions, flat organisational structure, macroeconomic intelligence, broad mission, Python, R, MATLAB, quantitative environments, large economic and financial datasets, repeatable research pipelines, tail risks, regime shifts, non-linear dynamics, macroeconomic systems, AI-driven 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As a Director of UX, you will manage a team of UX/UI designers while also being deeply hands-on, actively designing, prototyping, and conducting research alongside your team.</p>\n<p>This role requires a design leader who has extensive experience designing for mobile apps and responsive web products, bringing consistency, craft, and clarity across platforms. You must be comfortable alternating between high-level UX strategy, pixel-level detail, and customer discovery. You’ll partner with Product, Engineering, Marketing, and Data Science to deliver intuitive, artist-first experiences that drive growth, retention, and label partner success.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Define and articulate a multi-platform UX strategy spanning iOS, Android, and web.</li>\n<li>Establish a unified design language and systems that scale across mobile and desktop experiences.</li>\n<li>Champion simplicity, accessibility, and consistency across all surfaces.</li>\n</ul>\n<p>Hands-On Design Execution (Player/Coach):</p>\n<ul>\n<li>Deliver high-quality designs and prototypes for mobile apps and web interfaces, demonstrating mastery of platform-specific interaction patterns.</li>\n<li>Lead critical product surfaces including onboarding, distribution tools, subscription areas, analytics, payments, and artist monetization features.</li>\n<li>Collaborate directly with engineers to ensure designs are technically feasible and implemented with high fidelity across platforms.</li>\n<li>Coach designers on mobile UI patterns, responsive design, gesture-based interaction, and layout systems.</li>\n</ul>\n<p>User Research &amp; Customer Insight:</p>\n<ul>\n<li>Conduct user interviews, usability tests, concept evaluations, and surveys across mobile and web contexts.</li>\n<li>Build a deep understanding of how artists and label partners use our products across devices.</li>\n<li>Turn insights into product opportunities, UX improvements, and roadmap guidance.</li>\n<li>Evangelize research findings across executives and cross-functional teams.</li>\n</ul>\n<p>Team Leadership &amp; Operations:</p>\n<ul>\n<li>Manage, mentor, and develop a small but high-impact UX/UI design team.</li>\n<li>Establish design critique rituals, quality standards, and platform-specific guidelines for mobile and web.</li>\n<li>Implement design ops practices to streamline workflows, improve velocity, and reduce design debt.</li>\n<li>Build career paths, growth plans, and structures for scaling the UX function.</li>\n</ul>\n<p>Cross-Functional Partnership:</p>\n<ul>\n<li>Collaborate tightly with Product and Engineering to shape requirements, define success metrics, and plan releases across mobile and web.</li>\n<li>Work with Data Science, Artist Relations, and Marketing to create culturally resonant, data-informed experiences.</li>\n<li>Influence roadmap and prioritization using clear UX rationale and customer insights.</li>\n</ul>\n<p>Knowledge, Skills and Abilities:</p>\n<ul>\n<li>Strong project management skills and ability to prioritize work to successfully balance several work streams at a time.</li>\n<li>Ability to pay meticulous attention to detail and possess a deeply pro-active, hands-on mentality.</li>\n<li>Possess deep appreciation and sensitivity towards people, culture, and values.</li>\n<li>Ability to execute on priorities with a strong sense of urgency, ownership, and accountability.</li>\n<li>Ability to handle confidential and sensitive information with tact, diplomacy, and discretion.</li>\n<li>Proactive collaborator among various stakeholders and peers.</li>\n<li>Personable, smart, passionate, and optimistic.</li>\n</ul>\n<p>Minimum Qualifications:</p>\n<ul>\n<li>8+ years of UX/UI or product design experience for consumer-facing mobile apps (iOS + Android) and responsive web products.</li>\n<li>3+ years managing designers or leading design teams.</li>\n<li>Strong portfolio showing high-quality cross-platform design work, including flows, visual systems, and interaction patterns.</li>\n<li>Demonstrated experience as a hands-on designer and player/coach.</li>\n<li>Expertise in user research, usability testing, customer discovery, and insight synthesis.</li>\n<li>Proficiency with Figma, prototyping tools, mobile design systems, and responsive layout frameworks.</li>\n<li>Exceptional communication and storytelling capabilities.</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Experience in creator platforms, music tech, digital media, or marketplace ecosystems.</li>\n<li>Familiarity with experimentation/analytics systems (A/B testing, funnels, behavioral data).</li>\n<li>History of partnering deeply with engineering teams to ship mobile and web features at scale.</li>\n<li>Ability to coach designers across mobile interaction patterns, responsive best practices, UX writing, visual craft, and systems thinking.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_aed62813-195","directApply":true,"hiringOrganization":{"@type":"Organization","name":"UnitedMasters","sameAs":"https://unitedmasters.com/","logo":"https://logos.yubhub.co/unitedmasters.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/unitedmasterstranslation/jobs/8324080002","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$210,000 - 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The ideal candidate will be able to operate as a proactive player-coach hybrid. Strategic enough to sit in on a pricing discussion or a legislative briefing and add real value. Tactical enough to make sure every follow-up actually happens. Willing to draft a policy memo at 9am and clean up CRM data at 2pm. The through-line is judgment, ownership, and the ability to context-switch throughout the day.</p>\n<p>To facilitate face-to-face work and build internal trust with the CEO, preference will be given to candidates located in the NY metro area. Remote candidates willing to travel frequently will be considered, but local is strongly preferred.</p>\n<p><strong>Deal &amp; Pipeline Support</strong> Deal &amp; Pipeline Support - Government sales cycles are long, complex, and unforgiving. You&#39;ll own CRM hygiene, prep the CEO for meetings (pulling background on agencies, legislators, and procurement officers), draft follow-up emails, and track where every opportunity stands. Nothing falls through the cracks between a conference handshake and an RFP response.</p>\n<p><strong>AI-Driven Process Improvement</strong> You&#39;ll have a standing mandate to find places where AI can create velocity. That might mean building a monitoring pipeline that auto-summarizes new state-level identity legislation, setting up AI-assisted meeting prep workflows that pull relevant context before every government call, or creating drafting tools that let the CEO review and ship content in a fraction of the time.</p>\n<p><strong>Strategic Research &amp; Synthesis</strong> In govtech and digital identity, the landscape shifts fast: new NIST frameworks, state-level legislative changes, competitor moves, procurement shifts. You&#39;ll proactively monitor these developments, synthesize them into digestible briefs, and flag what matters to the CEO.</p>\n<p><strong>Communications &amp; Content Leverage</strong> The CEO frequently represents the company as a thought leader and public face, speaking at conferences, writing policy memos, and briefing legislators. You&#39;ll draft, edit, and polish these outputs. Turn a rough voice memo into a polished one-pager. Prep speaker notes. Ghost-draft blog content that positions the company in the market.</p>\n<p><strong>Cross-Functional Gap-Filling</strong> Running a hiring process one week, managing event prep the next, jumping into a partner integration workstream after that. The willingness and ability to move fluidly across these contexts will be critical to success in this role.</p>\n<p><strong>Travel</strong> Based in the U.S. (NY metro preferred) and willing to travel as needed to meet with government clients and attend company events.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_eea6f8e0-44d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"SpruceID","sameAs":"https://spruceid.com/","logo":"https://logos.yubhub.co/spruceid.com.png"},"x-apply-url":"https://jobs.lever.co/sprucesystems/930d4d79-7ee8-44c6-8426-0e7827315023","x-work-arrangement":"hybrid","x-experience-level":"executive","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CRM hygiene","AI-driven process improvement","strategic research and synthesis","communications and content leverage","cross-functional gap-filling"],"x-skills-preferred":["government sales cycles","procurement cycles","NIST frameworks","state-level legislative changes","competitor moves"],"datePosted":"2026-04-17T13:01:46.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"New York"}},"employmentType":"FULL_TIME","occupationalCategory":"Operations","industry":"Technology","skills":"CRM hygiene, AI-driven process improvement, strategic research and synthesis, communications and content leverage, cross-functional gap-filling, government sales cycles, procurement cycles, NIST frameworks, state-level legislative changes, competitor moves"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_629d842b-6a4"},"title":"RTL/ Synthesis Digital Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Senior RTL/Synthesis Digital Design Engineer, you will be responsible for architecting and developing RTL for high-bandwidth PHY IP and test chips. You will define synthesis constraints, resolve STA and simulation issues, and collaborate with verification, controller, and lab teams.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Performing logical and physical synthesis, formal verification, and quality checks</li>\n<li>Analysing timing violations and generating reports</li>\n<li>Mentoring junior engineers and supporting digital flow development</li>\n</ul>\n<p>The ideal candidate will have a strong background in RTL design and synthesis, with expertise in industry tools such as VCS, Verdi, Spyglass, and Synopsys sign-off. You should also have good English communication skills and be able to work effectively in a team.</p>\n<p>At Synopsys, we value talented individuals who are passionate about technology and problem-solving. We offer a comprehensive benefits package, including health and wellness programs, time away, family support, and competitive compensation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_629d842b-6a4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/rtl-synthesis-digital-design-sr-engineer/44408/92715864528","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design and synthesis","Industry tools (VCS, Verdi, Spyglass, Synopsys sign-off)","Scripting skills (Perl, tcl, Python, Shell)","Good English communication skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:24:37.280Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and synthesis, Industry tools (VCS, Verdi, Spyglass, Synopsys sign-off), Scripting skills (Perl, tcl, Python, Shell), Good English communication skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d416110b-f79"},"title":"PNR Applications Engineer, Staff","description":"<p>We are seeking a PNR Applications Engineer, Staff to join our Customer Success Group business. The primary focus of this role is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Back end P&amp;R tools (Fusion Compiler, ICC2, Innovus)</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n</ul>\n<p>Requirements include:</p>\n<ul>\n<li>BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.</li>\n<li>Tool knowledge: front end Synthesis and back end PnR tools (Fusion Compiler, ICC2, Design Compiler, Genus),</li>\n<li>Tool knowledge: STA (Primetime, Tempus)</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d416110b-f79","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/pnr-applications-engineer-staff/44408/92664451888","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":"$129000-$193000","x-skills-required":["ASIC design","Industry-standard tools","RTL to GDSII full flow","Advanced Node & Design methodologies","Synopsys Back end tool","Clock Tree Synthesis methodologies","Back end P&R tools"],"x-skills-preferred":["Front end Synthesis","Back end PnR tools","STA (Primetime, Tempus)"],"datePosted":"2026-04-05T13:22:58.699Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, Industry-standard tools, RTL to GDSII full flow, Advanced Node & Design methodologies, Synopsys Back end tool, Clock Tree Synthesis methodologies, Back end P&R tools, Front end Synthesis, Back end PnR tools, STA (Primetime, Tempus)","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":129000,"maxValue":193000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c01e313a-c5a"},"title":"IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer","description":"<p>We&#39;re looking for an IP (PCIE/CXL/USB/DP) Subsystem Design Implementation Engineer to join our team.</p>\n<p>Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.</li>\n<li>Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 5+ years of experience in IP/ASIC/SOC design implementation.</li>\n<li>Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.</li>\n<li>Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.</li>\n<li>Good communication skills while interacting with internal teams and customers.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.</li>\n<li>Experience in DesignWare Core IPs or PHYs.</li>\n<li>Experience in TCL, Perl, Python, or other shell scripting.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Competitive salary and benefits package.</li>\n<li>Opportunities for professional growth and development.</li>\n<li>Collaborative and dynamic work environment.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c01e313a-c5a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/ip-pcie-cxl-usb-dp-subsystem-design-implementation-engineer/44408/92638132304","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP/ASIC/SOC design implementation","synthesis","timing optimization","SDC writing","CDC/RDC checking","PCIe","USB","Display Port","Ethernet","DDR"],"x-skills-preferred":["Design Compiler","Fusion Compiler","PrimeTime","Spyglass","VC Spyglass","DesignWare Core IPs","PHYs","TCL","Perl","Python","shell scripting"],"datePosted":"2026-04-05T13:22:43.150Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP/ASIC/SOC design implementation, synthesis, timing optimization, SDC writing, CDC/RDC checking, PCIe, USB, Display Port, Ethernet, DDR, Design Compiler, Fusion Compiler, PrimeTime, Spyglass, VC Spyglass, DesignWare Core IPs, PHYs, TCL, Perl, Python, shell scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7c858523-91f"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_106cfbf6-843"},"title":"Physical Design Specialist (PDS)","description":"<p>We&#39;re looking for a Physical Design Specialist (PDS) to join our team. As a PDS, you will support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p>Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro &amp; Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.</p>\n<p>You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</p>\n<p>As a member of our high-performing Customer Application Services team, you will collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Support customers in enjoying Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge.</li>\n<li>Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n<li>Collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</li>\n<li>Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.</li>\n<li>Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.</li>\n</ul>\n<p>Key Qualifications:</p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.</li>\n<li>Tool knowledge expected: Back end P&amp;R tools (Fusion Compiler, ICC2, Innovus)</li>\n<li>Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),</li>\n<li>Tool knowledge (preferred): STA (Primetime, Tempus)</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_106cfbf6-843","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-principal-engineer/44408/92840962656","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Place & Route (physical)","Synthesis (logical and physical)","STA experience and knowledge","Macro & Standard Cell Placement","Clock Tree Synthesis","Routing","Advanced Timing Optimization techniques","Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2)"],"x-skills-preferred":["RTL to GDSII full flow experience","Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis)","Clock Tree Synthesis methodologies like H-Tree, MS-CTS"],"datePosted":"2026-04-05T13:22:15.432Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge, Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques, Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2), RTL to GDSII full flow experience, Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis), Clock Tree Synthesis methodologies like H-Tree, MS-CTS"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7330a4d3-ca6"},"title":"Senior Technical Product Engineer","description":"<p>Engineer the Future with Us\\n\\nWe currently have 614 open roles\\n\\n## Innovation Starts Here\\n\\nFind Jobs For\\n\\nWhere?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.\\n\\n# Senior Technical Product Engineer\\n\\nSunnyvale, California, United States\\n\\nSave\\n\\nCategory: Product ManagementHire Type: Employee\\n\\n<strong>Job ID</strong> 15163<strong>Base Salary Range</strong> $192000-$288000<strong>Date posted</strong> 02/10/2026\\n\\n<strong>We Are:</strong>\\n\\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\\n\\n<strong>You Are:</strong>\\n\\nYou are an experienced and highly motivated engineer with a passion for semiconductor innovation and digital design solutions. You thrive in environments that challenge you to bridge customer needs with cutting-edge technology, and you excel at translating complex technical concepts into actionable product strategies. With a deep understanding of EDA tools,especially in areas like synthesis, RTL architecture, place and route and  ECO methodologies,you are eager to drive the development of next-generation solutions. You bring a strong analytical mindset, a collaborative spirit, and a customer-centric approach to every project. Your ability to engage directly with customers, understand their critical challenges, and translate those insights into high-value product features sets you apart. You are a thought leader, comfortable presenting at industry forums and representing Synopsys as a subject matter expert. You are adept at managing cross-functional teams, prioritizing product roadmaps, and ensuring releases meet the highest standards of quality and impact. Your enthusiasm for technology is matched by your commitment to inclusivity, mentorship, and continuous learning. If you are ready to lead transformative projects and be at the forefront of semiconductor innovation, Synopsys is the place for you.\\n\\n<strong>What You’ll Be Doing:</strong>\\n\\n- Engaging directly with customers to identify high-value problems, particularly around optimizing power, performance, and area (PPA), and achieving multi-physics closure in design.\\n\\n- Analyzing and interpreting market trends to inform the Synopsys SCA roadmap, with a focus on advanced nodes and GenAI/Agentic flows.\\n\\n- Collaborating with DRIs and field partners to pinpoint product gaps and evaluate new opportunities for tool enhancement and innovation.\\n\\n- Defining and prioritizing product roadmaps by crafting Market Requirements Documents (MRDs) and partnering with Product Engineers to develop Product Requirements Documents (PRDs).\\n\\n- Writing code prototypes for new features and products, serving as &quot;executable specifications&quot; to demonstrate functionality and requirements to development teams.\\n\\n- Managing release readiness, including defining criteria for Alpha, Beta, Limited Customer Availability (LCA), and General Availability (GA) stages.\\n\\n- Enabling partners and field teams with training, strategic campaigns, and benchmarks to ensure new products deliver on promised value.\\n\\n- Representing Synopsys as a subject matter expert at customer forums, including TRMs and MRMs, and driving thought leadership at industry conferences.\\n\\n<strong>The Impact You Will Have:</strong>\\n\\n- Accelerate the adoption of Synopsys solutions, driving improved PPA outcomes for customers.\\n\\n- Shape the direction of Synopsys’s product offerings by identifying and acting on emerging industry trends.\\n\\n- Build stronger customer relationships through direct engagement, enabling tailored solutions that address their most critical challenges.\\n\\n- Enhance Synopsys’s reputation as a technology leader by presenting at industry events and fostering thought leadership.\\n\\n- Streamline product development processes through executable specifications, ensuring clarity and alignment across teams.\\n\\n- Increase the commercial success of new products by ensuring release readiness and effective go-to-market strategies.\\n\\n- Elevate partner and sales enablement, empowering teams to communicate product value and drive adoption.\\n\\n<strong>What You’ll Need:</strong>\\n\\n- Deep technical expertise in EDA tools, especially in synthesis, RTL architecture, place and route and ECO methodologies.\\n\\n- Proven experience in product management, including roadmap prioritization, MRD/PRD development, and release readiness are a nice to have\\n\\n- Strong coding skills for prototyping features and creating executable specifications.\\n\\n- Ability to analyze market trends, customer feedback, and competitive landscapes to inform product strategy.\\n\\n- Experience collaborating with cross-functional teams (engineering, sales, marketing, partners) in a fast-paced environment.\\n\\n- Familiarity presenting at industry forums, conferences, and customer meetings as a subject matter expert.\\n\\n<strong>Who You Are:</strong>\\n\\n- Customer-centric, with a passion for solving complex technical challenges.\\n\\n- Analytical and strategic thinker, able to synthesize information and drive actionable decisions.\\n\\n- Collaborative leader, skilled at working across teams and building consensus.\\n\\n- Effective communicator, comfortable presenting to diverse audiences and stakeholders.\\n\\n- Adaptable, curious, and committed to continuous learning and improvement.\\n\\n- Inclusive and supportive, fostering a culture of mentorship and teamwork.\\n\\n<strong>The Team You’ll Be A Part Of:</strong>\\n\\nYou’ll join a passionate and innovative product management team at Synopsys, focused on delivering state-of-the-art solutions for semiconductor design, verification, and optimization. Our team works closely with engineering, sales, and marketing to ensure that our tools meet the evolving needs of our customers. Together, we drive product excellence, industry leadership, and customer success.\\n\\n<strong>Rewards and Benefits:</strong>\\n\\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\\n\\n<strong>#LI-SV1</strong></p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7330a4d3-ca6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/senior-technical-product-engineer/44408/91639673840","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$192000-$288000","x-skills-required":["eda tools","synthesis","rtl architecture","place and route","eco methodologies","product management","roadmap prioritization","mrp/prd development","release readiness","coding skills","market trends","customer feedback","competitive landscapes","cross-functional teams","presenting at industry forums"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:53.469Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale"}},"occupationalCategory":"product management","industry":"technology","skills":"eda tools, synthesis, rtl architecture, place and route, eco methodologies, product management, roadmap prioritization, mrp/prd development, release readiness, coding skills, market trends, customer feedback, competitive landscapes, cross-functional teams, presenting at industry forums","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":192000,"maxValue":288000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_44645300-ced"},"title":"Hardware Engineering, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a global leader in semiconductor design and verification solutions, we enable the world&#39;s most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.</p>\n<p>You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.</p>\n<p>You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.</p>\n<p>Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks.\nPerforming digital design validation and functional verification at both block and SoC levels.\nExecuting logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs.\nApplying DFT (Design-for-Test) expertise for comprehensive memory and logic testing.\nIdentifying and troubleshooting design timing and DFT functional issues to optimize chip performance.\nUtilizing and scripting in languages such as Tcl to automate design and verification workflows.\nDeveloping and maintaining technical collateral including test suites, protocol documentation, and debug guides.</p>\n<p>Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies.\nShape the evolution of embedded memory test and SLM architectures that power next-generation devices.\nDrive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products.\nEnhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support.\nContribute to the continuous improvement of Synopsys&#39; design and verification solutions, setting new industry benchmarks.\nMentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth.\nInfluence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization.\nSupport strategic decision-making by providing technical insights and market-driven recommendations.</p>\n<p>2-4 years of relevant experience in ASIC digital design and verification.\nProficiency in RTL simulation, logic synthesis, and timing verification tools.\nStrong understanding of DFT architectures.\nFamiliarity with debug tools such as Verdi and workflows for performance analysis.\nProgramming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl.\nExperience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.</p>\n<p>Analytical thinker with exceptional problem-solving skills.\nEffective communicator, able to collaborate across disciplines and with external partners.\nProactive, self-motivated, and adaptable in fast-paced environments.\nCommitted to quality, detail, and continuous learning.\nTeam player who values diversity, inclusion, and mentorship.\nCustomer-focused, dedicated to delivering timely and effective solutions.</p>\n<p>You&#39;ll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. 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partner who thrives in diverse, cross-functional teams.</p>\n<p>An excellent communicator, able to tailor messaging for both technical and non-technical audiences.</p>\n<p>Innovative and proactive, always seeking opportunities to improve processes and outcomes.</p>\n<p>Resilient and adaptable, comfortable with change and ambiguity.</p>\n<p>Committed to fostering an inclusive and empowering team culture.</p>\n<p>Join the Digital IP Subsystems Team at Synopsys,a high-performing group of architects, designers, and engineers focused on delivering world-class silicon IP and subsystem solutions.</p>\n<p>The team collaborates closely with hardware, software, verification, and product teams across the globe, driving innovation in next-generation SoCs for AI, automotive, 5G, IoT, and more.</p>\n<p>Together, we value creativity, technical excellence, and inclusion, empowering each team member to make a significant impact.</p>\n<p>We offer a comprehensive range of health, wellness, and financial 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At Synopsys, you&#39;ll be part of a global team driving the breakthroughs that power self-driving cars, AI, 5G, IoT, and more. We&#39;re looking for a collaborative, innovative leader to join our Digital IP Subsystems Team and help accelerate the Era of Smart Everything.</p>\n<p>As a Senior Manager of SOC Engineering, you will oversee and drive end-to-end RTL design, verification, architecture, and integration of advanced subsystems. You will lead teams in Bangalore/Hyderabad, manage customer communications, and ensure timely, high-quality delivery. You will guide your team through the full lifecycle: from requirements to release, ensuring excellence at every stage. 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You will collaborate with product, engineering, marketing, and other GTM teams to develop deep product and industry knowledge and drive complex deals.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Drive revenue growth, increase attach rates, and new client acquisition for a wide range of customers, including Enterprises and Platforms</li>\n<li>Create a strategic territory plan and lead outreach efforts to develop a robust, qualified pipeline</li>\n<li>Develop relationships with executive stakeholders and lead discussions with existing and prospective customers</li>\n<li>Deeply understand Stripe Payments, our Optimized Checkout Suite, and competitors, serving as both an internal and customer-facing expert on our product and the market</li>\n<li>Engage with Product and Engineering teams to synthesize and relay customer feedback to inform Stripe’s product roadmap</li>\n<li>Contribute to the development of go-to-market playbooks alongside product, marketing, sales, and technical services stakeholders</li>\n<li>Work collaboratively and cross-functionally across the organization to help shape Stripe’s products and solutions to meet customer needs</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>7+ years of customer-facing experience at a leading technology or payments company and a track record of top performance</li>\n<li>Experience building trusted advisor relationships with senior business leaders</li>\n<li>Proven ability to build strong collaborative working relationships with cross-functional business partners</li>\n<li>Self-starter capable of operating independently to drive meaningful business results</li>\n<li>Excellent verbal and written communication skills</li>\n<li>Ability to understand complex technical requirements and craft solutions across multiple stakeholders</li>\n<li>Proven experience to lead complex negotiations involving bespoke commercial agreements</li>\n<li>Thrives in a fast-paced environment and changing requirements</li>\n<li>True team player</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>3+ years of experience specifically selling payments or technology solutions to enterprise customers</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc0fc579-4db","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Stripe","sameAs":"https://stripe.com/","logo":"https://logos.yubhub.co/stripe.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/stripe/jobs/7455982","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["customer-facing experience","sales and product expertise","deep product and industry knowledge","complex deal driving","strategic territory planning","pipeline development","executive stakeholder relationships","customer feedback synthesis","go-to-market playbook development","cross-functional collaboration"],"x-skills-preferred":["payments or technology solutions","enterprise customer experience"],"datePosted":"2026-03-31T17:56:24.819Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Remote"}},"jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Sales","industry":"Finance","skills":"customer-facing experience, sales and product expertise, deep product and industry knowledge, complex deal driving, strategic territory planning, pipeline development, executive stakeholder relationships, customer feedback synthesis, go-to-market playbook development, cross-functional collaboration, payments or technology solutions, enterprise customer experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bea2e9d0-633"},"title":"Research Scientist, Multimodal Generative AI, Google DeepMind","description":"<p>Our team works on developing state-of-the-art methods for AI generative media models, with a particular focus on culturally-adapted image and video generation.</p>\n<p>At Google DeepMind, we&#39;ve built a unique culture and work environment where long-term ambitious research can flourish. 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This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_02d8b8e9-445","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-asic-rtl-design-engineer/44408/92577687840","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","Verilog/SystemVerilog","Simulation tools","Design flows","Linting","Static timing analysis","Formal checking","P&R-aware synthesis","Fusion Compiler","Version control systems","Scripting languages","Industry protocols","Ethernet","DDR","PCIe","USB","MIPI-UFS/Unipro","SD-MMC","AMBA"],"x-skills-preferred":[],"datePosted":"2026-03-10T12:10:55.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, Verilog/SystemVerilog, Simulation tools, Design flows, Linting, Static timing analysis, Formal checking, P&R-aware synthesis, Fusion Compiler, Version control systems, Scripting languages, Industry protocols, Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4b712e08-c1e"},"title":"Staff Engineer (Machine Learning)","description":"<p><strong>Job Description</strong></p>\n<p>At Synopsys, we&#39;re seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design &amp; Verification business. As a key member of this highly innovative team, you&#39;ll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.</li>\n<li>Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.</li>\n<li>Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.</li>\n<li>Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).</li>\n<li>Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.</li>\n<li>Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys&#39; product lines.</li>\n</ul>\n<p><strong>Impact:</strong></p>\n<ul>\n<li>Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.</li>\n<li>Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.</li>\n<li>Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys&#39; tools, driving industry-leading outcomes.</li>\n<li>Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.</li>\n<li>Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.</li>\n<li>Strengthen Synopsys&#39; position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor&#39;s, Master&#39;s, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.</li>\n<li>5+ years of experience in chip design, EDA, or related fields.</li>\n<li>Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).</li>\n<li>Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.</li>\n<li>Solid understanding of Unix/Linux environments and design flow automation.</li>\n<li>Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.</li>\n<li>Familiarity with low power design techniques, computer architecture, and machine learning principles.</li>\n</ul>\n<p><strong>Who We&#39;re Looking For:</strong></p>\n<ul>\n<li>A creative problem solver who approaches challenges with curiosity and resilience.</li>\n<li>An effective communicator who collaborates well with multidisciplinary teams.</li>\n<li>Detail-oriented with a passion for quality and continuous improvement.</li>\n<li>Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.</li>\n<li>Committed to learning, growth, and sharing knowledge with others.</li>\n</ul>\n<p><strong>The Team You&#39;ll Be A Part Of:</strong></p>\n<p>You&#39;ll join the Machine Learning Center of Excellence (ML CoE) within Synopsys&#39; Silicon Design &amp; Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you&#39;ll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4b712e08-c1e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/dublin/staff-engineer-machine-learning/44408/92577691360","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["machine learning","chip design","EDA","Perl","Python","Tcl","shell scripting","Unix/Linux environments","design flow automation","RTL design","synthesis","place and route","verification","ATPG","custom-circuit design","signoff flows","low power design techniques","computer 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efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Date posted</strong>: 03/09/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect.</p>\n<p>Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.</p>\n<p>You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.</p>\n<p>With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.</p>\n<p>Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Lead and Drive all aspects of complete IP Design execution from start to end.</li>\n</ul>\n<ul>\n<li>Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.</li>\n</ul>\n<ul>\n<li>Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.</li>\n</ul>\n<ul>\n<li>Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.</li>\n</ul>\n<ul>\n<li>Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.</li>\n</ul>\n<ul>\n<li>Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.</li>\n</ul>\n<ul>\n<li>Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.</li>\n</ul>\n<ul>\n<li>Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.</li>\n</ul>\n<ul>\n<li>Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.</li>\n</ul>\n<ul>\n<li>Enabling customers to achieve faster time-to-market and superior silicon performance.</li>\n</ul>\n<ul>\n<li>Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.</li>\n</ul>\n<ul>\n<li>Driving continuous improvement in design methodologies, enhancing efficiency and product quality.</li>\n</ul>\n<ul>\n<li>Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.</li>\n</ul>\n<ul>\n<li>10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.</li>\n</ul>\n<ul>\n<li>Past experience of leading IP deign projects, team.</li>\n</ul>\n<ul>\n<li>In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.</li>\n</ul>\n<ul>\n<li>Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.</li>\n</ul>\n<ul>\n<li>Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).</li>\n</ul>\n<ul>\n<li>Familiarity with scripting languages such as Perl or Shell—an advantage.</li>\n</ul>\n<ul>\n<li>Demonstrated ability to technically lead or mentor small teams of engineers.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative team player who thrives in a multi-site, multicultural environment.</li>\n</ul>\n<ul>\n<li>An effective communicator, able to translate complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>A proactive problem-solver with strong analytical and troubleshooting skills.</li>\n</ul>\n<ul>\n<li>Self-motivated, showing high initiative and ownership of responsibilities.</li>\n</ul>\n<ul>\n<li>Adaptable and eager to learn, always seeking opportunities for personal and professional growth.</li>\n</ul>\n<ul>\n<li>Committed to fostering a positive, inclusive, and innovative team culture.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join the R&amp;D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.</p>\n<p>As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.</p>\n<p>The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work.</p>\n<p>Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world.</p>\n<p>We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.</p>\n<p>We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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You will develop and deploy in-house tools and workflows to support engineering business units across NVIDIA. You will take ownership of tools that verify common design blocks used in all products at NVIDIA. You will act as a &#39;DevOps&#39; engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users. You will build new workflows and methodologies to ensure smooth integration into various IP development environments.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.</li>\n<li>Take ownership of tools that verify common design blocks used in all products at NVIDIA.</li>\n<li>Act as a &#39;DevOps&#39; engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.</li>\n<li>Build new workflows and methodologies to ensure smooth integration into various IP development environments.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering or Computer Engineering (or equivalent experience).</li>\n<li>3+ years of proven experience preferred.</li>\n<li>Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.</li>\n<li>Proficiency in scripting using modern Python and/or Perl.</li>\n<li>Experience with Unix/Linux shell scripting and Makefiles.</li>\n<li>Strong ability to collaborate with multi-functional teams and effectively communicate technical details.</li>\n</ul>\n<p>Preferred qualifications:</p>\n<ul>\n<li>Prior experience in ASIC verification.</li>\n<li>Knowledge of Clocks/Resets design and verification.</li>\n<li>Exposure to CDC related design/verification flows.</li>\n<li>Exposure to backend flows (Synthesis, Timing, etc).</li>\n</ul>\n<p>NVIDIA is widely considered to be one of the technology world&#39;s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of constant innovation and creating the highest performance products in the industry? If so, we want to hear from you.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_03c25570-d79","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-TX-Austin/ASIC-Design-Engineer--Hardware-Tools-and-Methodology-Development_JR2008177","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Design","Hardware Tools","Methodology Development","Verilog","Python","Perl","Unix/Linux shell scripting","Makefiles"],"x-skills-preferred":["ASIC verification","Clocks/Resets design and verification","CDC related design/verification flows","Backend flows (Synthesis, Timing, etc)"],"datePosted":"2026-03-09T20:46:52.411Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"US, TX, Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Design, Hardware Tools, Methodology Development, Verilog, Python, Perl, Unix/Linux shell scripting, Makefiles, ASIC verification, Clocks/Resets design and verification, CDC related design/verification flows, Backend flows (Synthesis, Timing, etc)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1bdc3caf-792"},"title":"Governance, Risk, and Compliance (GRC) SME - Senior Consultant","description":"<p>Do you want to boost your career and collaborate with expert, talented colleagues to solve and deliver against our clients&#39; most important challenges? We are growing and are looking for people to join our team. You&#39;ll be part of an entrepreneurial, high-growth environment of 300,000 employees. Our dynamic organization allows you to work across functional business pillars, contributing your ideas, experiences, diverse thinking, and a strong mindset. Are you ready?</p>\n<p>We are looking for a highly skilled Cyber GRC (Governance, Risk, and Compliance) Senior Consultant to help organizations strengthen their cybersecurity posture, manage cyber risks, and ensure regulatory compliance. The ideal candidate will have deep expertise in cybersecurity frameworks, risk management, regulatory compliance, and security governance.</p>\n<p>As a Cyber GRC Senior Consultant, you will collaborate with client security, IT, and compliance teams to direct and oversee the development and implementation of cybersecurity policies, conduct risk assessments, and ensure adherence to global security standards and regulations.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<p>Work on global projects with a truly global team, with the support of over 330,000 technical staff from our parent organization.</p>\n<p>Contribute to the development of consulting go to market offerings and innovative solutions targeted at the C-Suite executive community that help them to understand and mitigate their cyber risks.</p>\n<p>Direct and lead NIST CSF risk assessments</p>\n<p>Oversee the design of innovative new services to lead the market incorporating AI and ML where it brings value.</p>\n<p>Support presales, sales, and account management pursuits from a subject matter expert perspective.</p>\n<p><strong>Requirements</strong></p>\n<p>You will have already achieved strong career progression to date, and experience working with recognized consulting brands and large commercial sector clients. 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We are looking for team members who strive to make an impact and are eager to learn. If this sounds like you and you feel you have the skills and experience required, then please apply now._</p>\n<p><strong>About your team</strong></p>\n<p>At the Tech Transformation practice, we help CIOs overcome their biggest challenges such as geopolitical and macroeconomic uncertainty, cybersecurity, digital transformation, and budget constraints; enabling them to leverage technology to deliver value to their business. We have a team of business analysts, enterprise architects and cybersecurity specialists with business, operational, strategic, analytical and innovation skills. that come together to drive business IT alignment, Transform IT governance, IT Cost containment, operating efficiency improvements, Innovation enablement and cybersecurity risk, governance, and compliance.</p>\n<p><strong>About Infosys Consulting</strong></p>\n<p>Be part of a globally renowned management consulting firm on the front-line of industry disruption and at the cutting edge of technology. We work with market leading brands across sectors. Our culture is inclusive and entrepreneurial. Being a mid-size consultancy within the scale of Infosys gives us the global reach to partner with our clients throughout their transformation journey.</p>\n<p>Our core values, IC-LIFE, form a common code that helps us move forward. IC-LIFE stands for Inclusion, Equity and Diversity, Client, Leadership, Integrity, Fairness, and Excellence. To learn more about Infosys Consulting and our values, please visit our careers page.</p>\n<p>Within Europe, we are recognized as one of the UK’s top firms by the Financial Times and Forbes due to our client innovations, our cultural diversity and dedicated training and career paths. Infosys is on the Germany’s top employers list for 2023. Management Consulting Magazine named us on their list of Best Firms to Work for. Furthermore, Infosys has been recognized by the Top Employers Institute, a global certification company, for its exceptional standards in employee conditions across Europe for five years in a row.</p>\n<p>We offer industry-leading compensation and benefits, along with top training and development opportunities so that you can grow your career and achieve your personal goals. Curious to learn more? We’d love to hear from you.... Apply today!</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1bdc3caf-792","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Infosys Consulting - Europe","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/kpLfuJ6MMnQF6UP1PbZm31/remote-governance%2C-risk%2C-and-compliance-(grc)-sme---senior-consultant-in-poland-at-infosys-consulting---europe","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["cybersecurity frameworks","risk management","regulatory compliance","security governance","NIST CSF","cyber due diligence assessments","third-party and supply chain cyber risk management","incident response plan review","crisis management exercises","accreditation such as CISSP, CISM, CISA, GSLC, GSTRT, GCPM","target operating models","RACI matrices","cybersecurity roadmaps","post-incident reviews","cyber threat intelligence reports","cybersecurity risk assessments","identity and access management","privileged access management"],"x-skills-preferred":["stakeholder management","problem-solving","resilience","data and information gathering","data and information validation","data and information synthesis","data and information documentation","data and information communication","interpersonal skills","written communication skills","verbal communication skills"],"datePosted":"2026-03-09T16:53:00.785Z","jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"IT","industry":"Consulting","skills":"cybersecurity frameworks, risk management, regulatory compliance, security governance, NIST CSF, cyber due diligence assessments, third-party and supply chain cyber risk management, incident response plan review, crisis management exercises, accreditation such as CISSP, CISM, CISA, GSLC, GSTRT, GCPM, target operating models, RACI matrices, cybersecurity roadmaps, post-incident reviews, cyber threat intelligence reports, cybersecurity risk assessments, identity and access management, privileged access management, stakeholder management, problem-solving, resilience, data and information gathering, data and information validation, data and information synthesis, data and information documentation, data and information communication, interpersonal skills, written communication skills, verbal communication skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_977f980d-bc3"},"title":"VP, Product Manager","description":"<p>About this role</p>\n<p>BlackRock is the world&#39;s leading asset management firm and Aladdin is the central nervous system for investment professionals to see their whole portfolio, understand risk exposure, and act with precision. It is a $1BN+ technology business that has significant growth aspirations over the next five years. Being a part of BlackRock means being a part of a community of smart, results-oriented people who are pursuing some of the world&#39;s most sophisticated financial challenges. And our founder-led culture has maintained its results-oriented feel — we work hard, we work as a team, and we work with purpose. Being a member of Aladdin Product means working with the best in the industry to build innovative products that shape financial markets.</p>\n<p>Sitting at the intersection of business and technology, the Aladdin Product Management team works closely with developers, researchers, and other stakeholders to innovate, conceptualize, design and pilot new capabilities across the investment lifecycle. As a Product Manager, you will have a positive impact on developing the product vision and leading day to day execution of the roadmap. There are many strategic areas that need exploration, evaluation, and prioritization, while in parallel ensuring that the tactical needs for continuing to deliver the product are met.</p>\n<p>As a trusted product expert, you will contribute to delivering key functionality to our asset servicer client base.</p>\n<p>By connecting market trends and our client needs with product engineering teams, you will have the opportunity to help shape and execute the future capabilities and growth of our Core Operating Platform capabilities.</p>\n<p>We are looking for a motivated product manager / owner to bring marketplace and asset servicer knowledge to our Private Markets Asset Servicer focused product team. This individual will help us improve our current positioning with Asset Servicers, while defining the right trajectory to accelerate growth in the complex Fund Accounting landscape.</p>\n<p>Strong candidates will bring their hands on experience working in asset servicing for alternative investments. You will be aware / research the competitive landscape and influence our technical and commercial decisions. You will also lead new product initiatives, coordinate engagement with users, oversee product roadmaps, and ensure unparalleled execution to deliver winning products. Success in this product vertical will both improve eFront Private Market solutions and Aladdin’s overall value offering and facilitate new growth opportunities, ultimately contributing to bold Aladdin growth targets in the Private Markets space.</p>\n<p>This role is also expected to contribute to Aladdin’s AI-enabled future—identifying where AI can improve user workflows (e.g., insight generation, explanation, scenario exploration, automation of repetitive analysis, natural-language interfaces), and where it must be applied thoughtfully with transparency, controls, and measurable value.</p>\n<p>You are:</p>\n<ul>\n<li><p>Passionate about building technical solutions in partnership with engineering teams</p>\n</li>\n<li><p>A self-starter who enjoys solving complex problems that deepen our understanding of end users</p>\n</li>\n<li><p>Curious to learn new skills and willing to embrace work outside of your comfort zone</p>\n</li>\n<li><p>AI-curious and AI-practical: you actively use AI tools to accelerate product discovery, writing, analysis, and experimentation—and you can separate “cool demos” from durable product value</p>\n</li>\n<li><p>Comfortable challenging the status quo and using your entrepreneurial spirit to create new solutions</p>\n</li>\n<li><p>A team player who is energized by working in a fast-paced environment</p>\n</li>\n</ul>\n<p>We are:</p>\n<ul>\n<li><p>Passionate about building innovative solutions that meet the needs of our clients</p>\n</li>\n<li><p>Comfortable challenging the status quo</p>\n</li>\n<li><p>Curious about financial markets and the technology ecosystem</p>\n</li>\n<li><p>Building AI-enabled product capabilities responsibly—prioritizing measurable outcomes, strong model/data governance, and a high bar for client trust</p>\n</li>\n<li><p>Results-oriented &amp; metrics-driven</p>\n</li>\n<li><p>Committed to fostering a purpose-driven culture and working horizontally to break down silos</p>\n</li>\n</ul>\n<p>Skills / Qualifications:</p>\n<ul>\n<li><p>5+ years of experience in product management / business analysis / client service that includes building and launching technology in a B2B or B2C market</p>\n</li>\n<li><p>Hands-on comfort using AI tools in daily product work (e.g., prompt-based research, summarization, synthesis, draft specifications, competitive scans, workflow mapping, data exploration support) with appropriate judgment and confidentiality</p>\n</li>\n<li><p>Dedicated interest in understanding, detailing, and mastering related workflows</p>\n</li>\n<li><p>Familiarity with AI product patterns and risks: understanding of model limitations (hallucinations, bias, drift), evaluation approaches, and product mechanisms to improve reliability (human-in-the-loop, citations/grounding, guardrails, feedback loops)</p>\n</li>\n<li><p>Excellent written and verbal communication skills with the ability to present complex information clearly and concisely</p>\n</li>\n<li><p>Bias for action and willingness to take risks</p>\n</li>\n<li><p>Strong analytical and problem-solving skills</p>\n</li>\n<li><p>Ability to make data-driven decisions and deliver results quickly</p>\n</li>\n<li><p>Preference for and demonstrated success in a team-oriented environment</p>\n</li>\n<li><p>BA/BS degree in Computer Science, Engineering, Economics, Finance, or equivalent practical experience</p>\n</li>\n</ul>\n<p>Primary Responsibilities:</p>\n<ul>\n<li><p>Partner with teams across Aladdin to drive forward strategic product decisions that accelerate the Aladdin offering</p>\n</li>\n<li><p>Define and document detailed product requirements and design product specifications</p>\n</li>\n<li><p>Attend and help manage key agile development rituals such as stand-ups, planning, demos, and retrospectives</p>\n</li>\n<li><p>Develop, prioritize, and maintain roadmaps, provide quarterly updates on deliverables and create content for management communications</p>\n</li>\n<li><p>Work with team leadership to maintain Aha! boards across the program (maintaining and managing the product backlog)</p>\n</li>\n<li><p>Keep abreast of the competitive landscape and new opportunities for partnership</p>\n</li>\n<li><p>Become a subject matter expert and provide technical/industry expertise to both sales and clients directly on how to leverage the Aladdin offering</p>\n</li>\n</ul>\n<p>Our benefits</p>\n<p>To help you stay energized, engaged and inspired, we offer a wide range of employee benefits including: retirement investment and tools designed to help you in building a sound financial future; access to education reimbursement; comprehensive resources to support your physical health and emotional well-being; family support programs; and Flexible Time Off (FTO) so you can relax, recharge and be there for the people you care about.</p>\n<p>Our hybrid work model</p>\n<p>BlackRock’s hybrid work model is designed to enable a culture of collaboration and apprenticeship that enriches the experience of our employees, while supporting flexibility for all. Employees are currently required to work at least 4 days in the office per week, with the flexibility to work from home 1 day a week. Some business groups may require more time in the office due to their roles and responsibilities. We remain focused on increasing the impactful moments that arise when we work together in person – aligned with our commitment to performance and innovation. As a new joiner, you can count on this hybrid model to accelerate your learning and onboarding experience here at BlackRock.</p>\n<p>About BlackRock</p>\n<p>At BlackRock, we are all connected by one mission: to help more and more people experience financial well-being. Our clients, and the people they serve, are saving for retirement, paying for their children’s educations, buying homes and starting businesses. Their investments also help to strengthen the global economy: support businesses small and large; finance infrastructure projects that improve the quality of life for millions of people; and create jobs that enable people to build better futures for themselves and their families.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_977f980d-bc3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"BlackRock","sameAs":"https://jobs.workable.com","logo":"https://logos.yubhub.co/view.com.png"},"x-apply-url":"https://jobs.workable.com/view/3ti1V7U2TerrjdrK5bdjt4/vp%2C-product-manager-in-london-at-blackrock","x-work-arrangement":"hybrid","x-experience-level":"executive","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["product management","business analysis","client service","AI tools","data exploration","workflow mapping","competitive scans","draft specifications","prompt-based research","summarization","synthesis","strong analytical and problem-solving skills","ability to make data-driven decisions","deliver results quickly","team-oriented environment","BA/BS degree in Computer Science, Engineering, Economics, Finance, or equivalent practical experience"],"x-skills-preferred":["AI-curious and AI-practical","comfortable challenging the status quo","curious about financial markets and the technology ecosystem","results-oriented & metrics-driven","committed to fostering a purpose-driven culture"],"datePosted":"2026-03-09T16:39:11.283Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"London"}},"employmentType":"FULL_TIME","occupationalCategory":"Finance","industry":"Finance","skills":"product management, business analysis, client service, AI tools, data exploration, workflow mapping, competitive scans, draft specifications, prompt-based research, summarization, synthesis, strong analytical and problem-solving skills, ability to make data-driven decisions, deliver results quickly, team-oriented environment, BA/BS degree in Computer Science, Engineering, Economics, Finance, or equivalent practical experience, AI-curious and AI-practical, comfortable challenging the status quo, curious about financial markets and the technology ecosystem, results-oriented & metrics-driven, committed to fostering a purpose-driven culture"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9a8cc13a-0a3"},"title":"Staff Applications Engineer, Digital Implementation","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15411</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff Applications Engineer, Digital Implementation</li>\n</ul>\n<ul>\n<li>Staff AE – RTL-to-GDS Solutions</li>\n</ul>\n<ul>\n<li>Senior Digital Design Flow Engineer</li>\n</ul>\n<ul>\n<li>Customer Success Engineer – Physical Design</li>\n</ul>\n<ul>\n<li>Staff Field Applications Engineer – EDA</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an experienced engineering professional with a passion for digital design flows and a drive to see customers succeed. You thrive at the intersection of deep technical problem-solving and collaborative partnership, always eager to tackle challenges that span RTL handoff to physical signoff. Your expertise in RTL-to-GDS flows allows you to confidently lead technical engagements, while your curiosity and commitment to learning keep you at the forefront of evolving methodologies and tools.</p>\n<p>You are self-driven, organized, and able to independently manage complex projects, always maintaining a strong sense of ownership over deliverables. You communicate clearly and effectively, whether you are guiding customers through best practices, collaborating with R&amp;D, or translating customer requirements into actionable feature requests. Your analytical skills help you quickly understand diverse customer scenarios, and your adaptability enables you to develop innovative solutions for unique challenges.</p>\n<p>You value teamwork and are motivated by the opportunity to influence both customer success and product evolution. You believe in continuous improvement, for yourself and for the solutions you support. If you are eager to make a tangible impact on the next generation of digital design, we invite you to join us.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Serve as the primary technical advisor for customers implementing Synopsys’ RTL-to-GDS (R2G) solution, including synthesis, physical implementation, and signoff flows.</li>\n</ul>\n<ul>\n<li>Lead customer onboarding, technical evaluations, benchmarking, and full production deployments across advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Analyze complex customer challenges and deliver tailored solutions using deep expertise in digital implementation flows.</li>\n</ul>\n<ul>\n<li>Develop and optimize RTL-to-GDS methodologies, including floorplanning, placement, clock tree synthesis, routing, and signoff correlation.</li>\n</ul>\n<ul>\n<li>Collaborate with global Applications Engineering, R&amp;D, and Product Management teams to enhance methodologies and influence tool development.</li>\n</ul>\n<ul>\n<li>Provide technical guidance and best practices to customers while ensuring successful project delivery and adoption of Synopsys tools.</li>\n</ul>\n<ul>\n<li>Troubleshoot and triage tool issues, provide reproducible testcases, and advocate for customer-driven enhancements.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive successful adoption and expansion of Synopsys’ digital implementation toolchain across key customer accounts.</li>\n</ul>\n<ul>\n<li>Enable customers to achieve optimal PPA (Power, Performance, Area) and signoff closure on complex projects.</li>\n</ul>\n<ul>\n<li>Serve as the voice of the customer, directly influencing tool enhancements and product roadmap evolution.</li>\n</ul>\n<ul>\n<li>Accelerate customer productivity and innovation by delivering robust methodologies and automation solutions.</li>\n</ul>\n<ul>\n<li>Foster long-term, trusted relationships with customers, contributing to Synopsys’ industry leadership and growth.</li>\n</ul>\n<ul>\n<li>Enhance cross-functional collaboration within Synopsys, driving continuous improvement in product quality and support.</li>\n</ul>\n<ul>\n<li>Champion best practices and knowledge sharing within the Applications Engineering community.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Proven expertise in RTL-to-GDS flows, including digital synthesis (Design Compiler/Fusion Compiler), physical implementation (ICC2/Fusion Compiler), and static timing analysis (PrimeTime).</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced node design, floorplanning, PPA optimization, and signoff-driven closure.</li>\n</ul>\n<ul>\n<li>Strong proficiency in scripting languages (Tcl, Python, Perl) for flow automation and customization.</li>\n</ul>\n<ul>\n<li>Ability to independently own technical deliverables, lead customer evaluations, and drive production deployments.</li>\n</ul>\n<ul>\n<li>Deep understanding of digital design methodologies, process technology challenges, and EDA tool ecosystems.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical and methodical, able to evaluate diverse customer scenarios and devise effective solutions.</li>\n</ul>\n<ul>\n<li>Exceptional communicator, comfortable engaging with both internal teams and external partners.</li>\n</ul>\n<ul>\n<li>Self-motivated and accountable, thriving with moderate supervision and a high degree of autonomy.</li>\n</ul>\n<ul>\n<li>Collaborative team player, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Customer-focused, energetic, and adaptable to fast-paced, evolving environments.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic, globally distributed Applications Engineering team at Synopsys, dedicated to driving customer success in digital implementation. Our team works closely with R&amp;D, Product Management, and field engineers to deliver innovative solutions, optimize design flows, and influence product direction. We foster a culture of collaboration, continuous learning, and knowledge sharing, empowering each other to solve complex challenges and achieve excellence for our customers.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p>Back to nav</p>\n<p>Get an idea of what your daily routine **around the office*</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9a8cc13a-0a3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/penang/staff-applications-engineer-digital-implementation/44408/92092150640","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDS flows","digital synthesis","physical implementation","static timing analysis","advanced node design","floorplanning","PPA optimization","signoff-driven closure","scripting languages","Tcl","Python","Perl","EDA tool ecosystems"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:20.254Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Penang, Malaysia"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDS flows, digital synthesis, physical implementation, static timing analysis, advanced node design, floorplanning, PPA optimization, signoff-driven closure, scripting languages, Tcl, Python, Perl, EDA tool ecosystems"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4b33752-a69"},"title":"Application Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.</p>\n<p>You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.</p>\n<p>You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.</p>\n<p>You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.</p>\n<p>The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.</p>\n<p>You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&amp;D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys&#39; reputation as a trusted partner and thought leader in the semiconductor industry.</p>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.</li>\n<li>Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).</li>\n<li>Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place &amp; Route, and timing analysis.</li>\n<li>Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.</li>\n<li>Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.</li>\n<li>Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.</li>\n<li>Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Excellent communicator able to build trust and rapport with diverse stakeholders.</li>\n<li>Analytical thinker with strong troubleshooting and debugging skills.</li>\n<li>Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.</li>\n<li>Highly collaborative team player who thrives in fast-paced, multicultural environments.</li>\n<li>Self-motivated, innovative, and passionate about continuous learning and process improvement.</li>\n<li>Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will join a dynamic, expert team within the Silicon Design &amp; Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&amp;D, and field teams to deliver transformative solutions and advance industry-leading technologies.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4b33752-a69","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-staff-engineer/44408/92113189648","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Implementation Methodologies","Physical Design","Synopsys tools","RTL to GDS flows","Synthesis","Place & Route","Timing analysis","Scripting (TCL, Python, Unix, Perl)","Automation","Tool integration","Debugging"],"x-skills-preferred":["STA","Low Power Flows","Design Planning","Customer-facing roles"],"datePosted":"2026-03-09T11:05:14.988Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Implementation Methodologies, Physical Design, Synopsys tools, RTL to GDS flows, Synthesis, Place & Route, Timing analysis, Scripting (TCL, Python, Unix, Perl), Automation, Tool integration, Debugging, STA, Low Power Flows, Design Planning, Customer-facing roles"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fa7e7d4f-643"},"title":"ASIC Digital Design, Staff","description":"<p>You are a seasoned engineer who thrives in dynamic, collaborative environments and is passionate about digital ASIC design. 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The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&amp;D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.</li>\n</ul>\n<ul>\n<li>Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.</li>\n</ul>\n<ul>\n<li>Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with customers, R&amp;D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.</li>\n</ul>\n<ul>\n<li>Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.</li>\n</ul>\n<ul>\n<li>Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.</li>\n</ul>\n<ul>\n<li>Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&amp;D on new feature development.</li>\n</ul>\n<ul>\n<li>Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.</li>\n</ul>\n<ul>\n<li>Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.</li>\n</ul>\n<ul>\n<li>Elevate the technical capabilities of the application engineering team through mentorship and cross-training.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.</li>\n</ul>\n<ul>\n<li>Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&amp;R tools (Fusion Compiler, ICC2, or similar).</li>\n</ul>\n<ul>\n<li>Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.</li>\n</ul>\n<ul>\n<li>Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.</li>\n</ul>\n<ul>\n<li>Outstanding verbal and written communication, presentation, and customer interaction skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.</li>\n</ul>\n<ul>\n<li>Analytical thinker with a problem-solving mindset and a passion for continuous improvement.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in the face of evolving customer requirements and technology landscapes.</li>\n</ul>\n<ul>\n<li>Strong organizational skills, able to manage multiple projects and priorities with poise.</li>\n</ul>\n<ul>\n<li>Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&amp;D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_82b664ed-78c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/staff-application-engineer-backend/44408/92463617216","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDSII flows","industry-leading EDA tools","physical synthesis","timing closure","clock tree synthesis (CTS)","routing at advanced technology nodes","Tcl and Python scripting","backend P&R tools","Fusion Compiler","ICC2"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:22:03.259Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDSII flows, industry-leading EDA tools, physical synthesis, timing closure, clock tree synthesis (CTS), routing at advanced technology nodes, Tcl and Python scripting, backend P&R tools, Fusion Compiler, ICC2"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c11a08e0-9f9"},"title":"Technical Sound Designer","description":"<p>As a Technical Sound Designer at iRacing.com, you will be part of a team responsible for creating sonic engine models from processing raw audio data to implementation. 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Co-design Engineer (junior)</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. 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In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong><strong>About the Team</strong></strong></p>\n<p>OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.</p>\n<p><strong><strong>About the Role</strong></strong></p>\n<p>We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_568dcff2-ed1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/77b815de-b7c5-4b87-8582-e8c752aea849","x-work-arrangement":"hybrid","x-experience-level":"junior","x-job-type":"full-time","x-salary-range":"$225K – $445K • Offers Equity","x-skills-required":["RTL","Verilog","SystemVerilog","Computer Architecture","AI/ML Hardware–Software Co-design","Workload Analysis","Dataflow Mapping","Accelerator Algorithm Optimization","Hardware Design Models","Architectural Simulators","Industry-standard Design Tools","Lint","CDC/RDC","Synthesis","STA","Methodologies"],"x-skills-preferred":[],"datePosted":"2026-03-06T18:39:06.360Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL, Verilog, SystemVerilog, Computer Architecture, AI/ML Hardware–Software Co-design, Workload Analysis, Dataflow Mapping, Accelerator Algorithm Optimization, Hardware Design Models, Architectural Simulators, Industry-standard Design Tools, Lint, CDC/RDC, Synthesis, STA, Methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":225000,"maxValue":445000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_27dc0990-2c7"},"title":"AI Deployment Manager","description":"<p><strong>AI Deployment Manager - NYC</strong></p>\n<p><strong>Location</strong></p>\n<p>New York City</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>Hybrid</p>\n<p><strong>Department</strong></p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$162K – $230K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. 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We specialize in technical enablement and adoption, guiding customers through how to effectively use OpenAI’s products across teams, workflows, and stages of maturity.</p>\n<p>Our work spans structured workshops, technical enablement, and adoption programs that help customers move from initial exposure to confident, scalable use. We work closely with Sales, AI Success Engineers, Solutions Engineering, and Product to ensure customers are not only enabled, but set up for long-term success as OpenAI’s platform evolves.</p>\n<p>Our customers range from fast-growing digital natives to the largest global enterprises, government agencies, and educational institutions. Every engagement is an opportunity to ensure that AI benefits the way people work, build, and innovate. This role sits at the centre of that mission.</p>\n<p><strong>About the Role</strong></p>\n<p>The AI Deployment Manager role is a specialist post-sales enablement role focused on delivering high-impact enablement and adoption services across OpenAI’s product suite. This role is responsible for designing and delivering technical enablement experiences that support a repeatable adoption framework– driving sustained activation, expanding breadth and depth of usage, and measurable business value across OpenAI’s product suite, including ChatGPT Enterprise, Codex, Agents, and the API. This includes helping customers understand and correctly apply the deployment harnesses, evaluation layers, and operational controls required for reliable use.</p>\n<p>This role blends deep technical fluency, instructional design, and customer advisory. You will lead live trainings, workshops, and adoption interventions for audiences ranging from hands-on builders to executive leaders, helping customers understand not just what OpenAI’s products can do, but how to use them effectively in real-world contexts.</p>\n<p>Success in this role means accelerating customer confidence, increasing product adoption, supporting successful launches of new product capabilities, and helping customers translate technical features into tangible outcomes.</p>\n<p>This role is based in NYC office. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Own the technical enablement of OpenAI products, including ChatGPT Enterprise, Codex, Agents, and API capabilities, helping define effective enablement patterns that support adoption across customer segments.</li>\n</ul>\n<ul>\n<li>Lead customer training and enablement across the full customer lifecycle, from initial onboarding through expansion, optimization, and long-term adoption.</li>\n</ul>\n<ul>\n<li>Design and deliver high-impact training engagements, including onboarding sessions, advanced capability trainings, executive briefings, hackathons, and hands-on workshops for audiences ranging from senior leaders to working teams.</li>\n</ul>\n<ul>\n<li>Drive customer activation, sustained usage, and measurable business value through structured enablement and deployment programs designed for durable adoption at scale.</li>\n</ul>\n<ul>\n<li>Partner closely with Sales, AI Success Engineers, Solutions Engineering, and Product teams to ensure seamless handoff from pre- to post-sale and consistent customer experience.</li>\n</ul>\n<ul>\n<li>Develop and refine reusable training assets, playbooks, and best practices based on patterns observed across customers and regions.</li>\n</ul>\n<ul>\n<li>Gather customer feedback from training and enablement engagements, synthesize themes across accounts, and relay insights to internal stakeholders to inform product and program improvements.</li>\n</ul>\n<p><strong>You’ll thrive in this role if you:</strong></p>\n<ul>\n<li>Have 4+ years of experience in customer-facing or instructional roles, engaging C-level and senior technical audiences in complex enterprise environments.</li>\n</ul>\n<ul>\n<li>Possess</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_27dc0990-2c7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/b41e93a7-c60b-45bc-943e-6e8c8bb9a7f0","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$162K – $230K","x-skills-required":["AI Deployment","Technical Enablement","Adoption Services","ChatGPT Enterprise","Codex","Agents","API","Instructional Design","Customer Advisory","Live Trainings","Workshops","Adoption Interventions","Hands-on Builders","Executive Leaders","Technical Fluency","Customer Feedback","Synthesis","Insights","Product Improvements"],"x-skills-preferred":["Project Management","Communication","Collaboration","Problem-Solving","Analytical Skills","Data Analysis","Business Acumen"],"datePosted":"2026-03-06T18:34:26.024Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"New York City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"AI Deployment, Technical Enablement, Adoption Services, ChatGPT Enterprise, Codex, Agents, API, Instructional Design, Customer Advisory, Live Trainings, Workshops, Adoption Interventions, Hands-on Builders, Executive Leaders, Technical Fluency, Customer Feedback, Synthesis, Insights, Product Improvements, Project Management, Communication, Collaboration, Problem-Solving, Analytical Skills, Data Analysis, Business Acumen","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":162000,"maxValue":230000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a426da4b-6d6"},"title":"Technical Program Manager, Trustworthy AI","description":"<p><strong>Technical Program Manager, Trustworthy AI</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Technical Program Management</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$207K – $335K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. 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This includes enabling third party assessments for OpenAI’s flagship launches, piloting new assurance mechanisms like safety compliance reviews, and incorporating independent expert input as evidence for critical safety decisions. This role requires a blend of partnership management, cross functional coordination, an understanding of AI safety research and evaluations, and strong communication skills to synthesize findings and translate into decision relevant actions.</p>\n<p><strong>About the Role</strong></p>\n<p>As a Technical Program Manager on the Trustworthy AI team, you will drive interdisciplinary programs in collaboration with external partners. This includes strategizing and executing on the vision for strategic research partnerships, and growing and managing our external assurance programs which include third party assessments and enabling independent academic research.</p>\n<p>We’re looking for people who have experience running strategic academic collaborations and program management with technical and research teams. You will work with researchers/engineers both internal to OpenAI and as a part of the external community to initiate new projects, set ambitious goals and milestones, and drive execution across multiple teams.</p>\n<p>This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Create strategic research partnerships</li>\n</ul>\n<ul>\n<li>Proactively identify new partners for external assurances such as high quality third party evaluators and academic research labs</li>\n</ul>\n<ul>\n<li>Create feedback mechanisms for translating external research into actionable product and policy recommendations</li>\n</ul>\n<ul>\n<li>Communicate progress, status and risk effectively to stakeholders internally and externally</li>\n</ul>\n<ul>\n<li>Drive tool and process improvements to improve efficiency</li>\n</ul>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Have an understanding of AI evaluations and measurements and ability to engage with technical teams on AI evaluations</li>\n</ul>\n<ul>\n<li>Have experience working with and managing stakeholders external to an organization, especially academic researchers</li>\n</ul>\n<ul>\n<li>Can create executive summaries and synthesis of technical and social science research</li>\n</ul>\n<ul>\n<li>Have worked cross functionally across product, research, and engineering teams</li>\n</ul>\n<ul>\n<li>Have an understanding and interest in frontier AI safety and policy</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a426da4b-6d6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/2ce31dca-6a6b-4bc3-abab-9b7ed5ba92d5","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$207K – $335K • Offers Equity","x-skills-required":["Technical Program Management","Strategic Research Partnerships","External Assurance Programs","AI Safety Research and Evaluations","Cross Functional Coordination","Communication Skills"],"x-skills-preferred":["AI Evaluations and Measurements","Academic Research","Executive Summaries and Synthesis of Technical and Social Science Research","Cross Functional Collaboration","Frontier AI Safety and Policy"],"datePosted":"2026-03-06T18:32:21.605Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Technical Program Management, Strategic Research Partnerships, External Assurance Programs, AI Safety Research and Evaluations, Cross Functional Coordination, Communication Skills, AI Evaluations and Measurements, Academic Research, Executive Summaries and Synthesis of Technical and Social Science Research, Cross Functional Collaboration, Frontier AI Safety and Policy","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":207000,"maxValue":335000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d3a39f4c-d95"},"title":"Software Engineer, Inference - Multi Modal","description":"<p><strong>Software Engineer, Inference - Multi Modal</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$295K – $555K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. 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Our work ensures these models are available, performant, and scalable in production, and we partner closely with Research to bring the next generation of models into the world. We&#39;re a small, fast-moving team of engineers focused on delivering a world-class developer experience while pushing the boundaries of what AI can do.</p>\n<p>We’re expanding into multimodal inference, building the infrastructure needed to serve models that handle image, audio, and other non-text modalities. These workloads are inherently more heterogeneous and experimental, involving diverse model sizes and interactions, more complex input/output formats, and tighter coordination with product and research.</p>\n<p><strong>About the Role</strong></p>\n<p>We’re looking for a software engineer to help us serve OpenAI’s multimodal models at scale. You’ll be part of a small team responsible for building reliable, high-performance infrastructure for serving real-time audio, image, and other MM workloads in production.</p>\n<p>This work is inherently cross-functional: you’ll collaborate directly with researchers training these models and with product teams defining new modalities of interaction. You&#39;ll build and optimize the systems that let users generate speech, understand images, and interact with models in ways far beyond text.</p>\n<p><strong>In this role, you will:</strong></p>\n<ul>\n<li>Design and implement inference infrastructure for large-scale multimodal models.</li>\n</ul>\n<ul>\n<li>Optimize systems for high-throughput, low-latency delivery of image and audio inputs and outputs.</li>\n</ul>\n<ul>\n<li>Enable experimental research workflows to transition into reliable production services.</li>\n</ul>\n<ul>\n<li>Collaborate closely with researchers, infra teams, and product engineers to deploy state-of-the-art capabilities.</li>\n</ul>\n<ul>\n<li>Contribute to system-level improvements including GPU utilization, tensor parallelism, and hardware abstraction layers.</li>\n</ul>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Have experience building and scaling inference systems for LLMs or multimodal models.</li>\n</ul>\n<ul>\n<li>Have worked with GPU-based ML workloads and understand the performance dynamics of large models, especially with complex data like images or audio.</li>\n</ul>\n<ul>\n<li>Enjoy experimental, fast-evolving work and collaborating closely with research.</li>\n</ul>\n<ul>\n<li>Are comfortable dealing with systems that span networking, distributed compute, and high-throughput data handling.</li>\n</ul>\n<ul>\n<li>Have familiarity with inference tooling like vLLM, TensorRT-LLM, or custom model parallel systems.</li>\n</ul>\n<ul>\n<li>Own problems end-to-end and are excited to operate in ambiguous, fast-moving spaces.</li>\n</ul>\n<p><strong>Nice to Have:</strong></p>\n<ul>\n<li>Experience working with image generation or audio synthesis models in production.</li>\n</ul>\n<ul>\n<li>Exposure to distributed ML training or system-efficient model design.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d3a39f4c-d95","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/4d14449e-5e7f-45d4-b103-8776a6c87086","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$295K – $555K • Offers Equity","x-skills-required":["Software Engineer","Inference Infrastructure","GPU-based ML Workloads","Tensor Parallelism","Hardware Abstraction Layers","vLLM","TensorRT-LLM","Custom Model Parallel Systems"],"x-skills-preferred":["Image Generation","Audio Synthesis","Distributed ML Training","System-Efficient Model Design"],"datePosted":"2026-03-06T18:31:07.882Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Software Engineer, Inference Infrastructure, GPU-based ML Workloads, Tensor Parallelism, Hardware Abstraction Layers, vLLM, TensorRT-LLM, Custom Model Parallel Systems, Image Generation, Audio Synthesis, Distributed ML Training, System-Efficient Model Design","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":295000,"maxValue":555000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d094148d-0e0"},"title":"RTL & Codesign Engineer","description":"<p><strong>Job Posting</strong></p>\n<p><strong>RTL &amp; Codesign Engineer</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Scaling</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$225K – $445K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. 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We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.</p>\n<p><strong><strong>In this role you will:</strong></strong></p>\n<ul>\n<li>Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems</li>\n</ul>\n<ul>\n<li>Contribute to architectural studies including performance modeling and feasibility analysis.</li>\n</ul>\n<ul>\n<li>Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.</li>\n</ul>\n<ul>\n<li>Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.</li>\n</ul>\n<ul>\n<li>Build and review performance and functional models to validate design intent.</li>\n</ul>\n<ul>\n<li>Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.</li>\n</ul>\n<p><strong><strong>You Might Thrive In This Role If You Have:</strong></strong></p>\n<ul>\n<li>Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.</li>\n</ul>\n<ul>\n<li>Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.</li>\n</ul>\n<ul>\n<li>Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.</li>\n</ul>\n<ul>\n<li>Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.</li>\n</ul>\n<ul>\n<li>Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.</li>\n</ul>\n<ul>\n<li>Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.</li>\n</ul>\n<ul>\n<li>Passion for building industry-leading massive-scale hardware systems.</li>\n</ul>\n<p>_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._</p>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. 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The successful candidate will be responsible for providing technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems</li>\n<li>Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s and/or masters with a minimum 10+yrs of Industry experience or equivalent</li>\n<li>At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)</li>\n<li>Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure</li>\n<li>Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2e9367c2-7d7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/herzliya/serdes-ip-s-applications-engineering-sr-staff-engineer/44408/92304383936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["IP design","ASIC/SoC integration","customer-facing engineering roles","ASIC design flows","simulation/verification","RTL synthesis","floorplanning","physical design","timing closure","High Speed SerDes IPs","PCIe","ETH","USB"],"x-skills-preferred":[],"datePosted":"2026-03-06T07:38:03.021Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Herzliya, Tel Aviv, Israel"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"IP design, ASIC/SoC integration, customer-facing engineering roles, ASIC design flows, simulation/verification, RTL synthesis, floorplanning, physical design, timing closure, High Speed SerDes IPs, PCIe, ETH, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6c57cc00-ceb"},"title":"R&D Engineering, Staff Engineer OPC","description":"<p>We are seeking a Staff Engineer OPC to join our R&amp;D team. As a Staff Engineer OPC, you will be responsible for collaborating directly with customers and internal R&amp;D teams to understand and address technical challenges in mask synthesis and lithography.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Collaborating directly with customers and internal R&amp;D teams to understand and address technical challenges in mask synthesis and lithography.</li>\n<li>Translating customer requirements into comprehensive Product Requirement Documents (PRDs), shaping product direction and roadmap.</li>\n<li>Reviewing and approving functional specifications to ensure alignment with customer needs and technical feasibility.</li>\n<li>Conducting early-stage testing of new features and functionalities during development cycles, providing critical feedback for product refinement.</li>\n<li>Prototyping advanced OPC/RET solutions and partnering with R&amp;D to drive their transition into robust, production-ready tools.</li>\n<li>Supporting field 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In this role, you will be responsible for supporting the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</li>\n<li>In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_04934540-478","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-principal-engineer/44408/90265976416","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Design Implementation experience","RTL to GDSII full flow experience","Strong interest and understanding of Advanced Node & Design methodologies","In-depth Synopsys Back end tool experience","Knowledge of several Clock Tree Synthesis methodologies","Excellent verbal and written presentation/communication skills","Customer sensitivity"],"x-skills-preferred":["BSEE or equivalent","Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)","Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus)","Tool knowledge (preferred): STA (Primetime, Tempus)"],"datePosted":"2026-03-06T07:29:04.274Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Design Implementation experience, RTL to GDSII full flow experience, Strong interest and understanding of Advanced Node & Design methodologies, In-depth Synopsys Back end tool experience, Knowledge of several Clock Tree Synthesis methodologies, Excellent verbal and written presentation/communication skills, Customer sensitivity, BSEE or equivalent, Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus), Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus), Tool knowledge (preferred): STA (Primetime, Tempus)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_19f57d9e-523"},"title":"Staff EDA Applications Engineer","description":"<p>We are seeking a highly skilled Staff EDA Applications Engineer to join our team in Bengaluru, India. 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This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.</p>\n<ul>\n<li>Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.</li>\n</ul>\n<ul>\n<li>Drive flow development and optimization to improve design quality and predictability.</li>\n</ul>\n<ul>\n<li>Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).</li>\n</ul>\n<ul>\n<li>Contribute to the adoption and integration of advanced technologies and tool features in design implementation.</li>\n</ul>\n<ul>\n<li>Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.</li>\n</ul>\n<ul>\n<li>Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why this matters</strong></p>\n<p>Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.</p>\n<p>Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.</p>\n<p>Enhance the predictability and simplicity of implementation processes for complex interface IPs.</p>\n<p>Accelerate the adoption of next-generation design technologies and tools across the industry.</p>\n<p>Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.</p>\n<p>Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.</p>\n<p><strong>What you’ll need</strong></p>\n<ul>\n<li><strong>Minimum 7years</strong> of experience in physical design, with a focus on high-performance and low-power methodologies.</li>\n</ul>\n<ul>\n<li>Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.</li>\n</ul>\n<ul>\n<li>Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.</li>\n</ul>\n<ul>\n<li>Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.</li>\n</ul>\n<ul>\n<li>Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.</li>\n</ul>\n<p><strong>Why you’ll love this role</strong></p>\n<ul>\n<li>Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.</li>\n</ul>\n<ul>\n<li>Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.</li>\n</ul>\n<ul>\n<li>Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.</li>\n</ul>\n<ul>\n<li>Participate in professional development opportunities to enhance your skills and expertise.</li>\n</ul>\n<ul>\n<li>Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n</ul>\n<ul>\n<li>Time Away</li>\n</ul>\n<ul>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n</ul>\n<ul>\n<li>Family Support</li>\n</ul>\n<ul>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n</ul>\n<ul>\n<li>ESPP</li>\n</ul>\n<ul>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n</ul>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<ul>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n</ul>\n<ul>\n<li>Compensation</li>\n</ul>\n<ul>\n<li>Competitive salaries.</li>\n</ul>\n<ul>\n<li>Awards</li>\n</ul>\n<ul>\n<li>We&#39;re proud to receive several recognitions.</li>\n</ul>\n<ul>\n<li>Explore the Possibilities with Synopsys</li>\n</ul>\n<ul>\n<li>Search Synopsys Careers</li>\n</ul>\n<ul>\n<li>Join our Talent Community</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_509e3a3b-0fb"},"title":"ASIC Physical Design, Sr Staff","description":"<p>Opening. This role is a key member of the Interface IP Design Methodology team, working with global teams to define best practice ASIC design standards and flows. The team is responsible for next-generation SerDes and Memory interface controllers, PHYs, and subsystems.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys&#39; best in class tools and technologies.</p>\n<p>Work with leading edge designs and teams to drive the industry best PPA for IP designs.</p>\n<p>Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place &amp; route, timing and power (incl. EM/IR) optimization and analysis.</p>\n<p>Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.</p>\n<p>Work as a liaison between EDAG tool and IP design teams.</p>\n<p>Continuously improve and refine design processes to enhance efficiency and performance.</p>\n<p><strong>What you need</strong></p>\n<p>BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.</p>\n<p>Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.</p>\n<p>Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place &amp; Route tools.</p>\n<p>Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.</p>\n<p>Good analysis, debugging, and problem-solving skills.</p>\n<p>Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.</p>\n<p>Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.</p>\n<p>Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_509e3a3b-0fb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-staff/44408/91568840304","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BS or MS in EE","10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs","Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions","Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools","Ability to facilitate cross-functional collaboration","Good analysis, debugging, and problem-solving skills","Solid written and verbal communication skills"],"x-skills-preferred":["Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools)","Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"],"datePosted":"2026-02-11T16:09:21.948Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BS or MS in EE, 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs, Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions, Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools, Ability to facilitate cross-functional collaboration, Good analysis, debugging, and problem-solving skills, Solid written and verbal communication skills, Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools), Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2a30b6e4-ca4"},"title":"ASIC Verification, Principal Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<ul>\n<li>Designing, implementing and optimizing verification environments to ensure the correctness of Interface IP protocols.</li>\n<li>Creating, executing and tracking against detailed test plans to verify complex ASIC designs.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).</li>\n<li>Proficiency in System Verilog, SVA and UVM methodologies.</li>\n<li>Strong understanding of digital design and verification concepts.</li>\n<li>Familiarity with wider digital ASIC and IP development flow, including RTL design through synthesis.</li>\n<li>Experience with simulation tools such as VCS, Model Sim, or similar.</li>\n<li>Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.</li>\n<li>Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2a30b6e4-ca4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/reading/asic-verification-principal-engineer/44408/91539646624","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC digital verification","Interface IP protocols","System Verilog","SVA","UVM methodologies","Digital design and verification concepts","Simulation tools","Analytical and problem-solving skills","Communication skills"],"x-skills-preferred":["RTL design through synthesis","VCS, Model Sim, or similar"],"datePosted":"2026-02-11T16:09:03.098Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Reading, United Kingdom"}},"jobLocationType":"TELECOMMUTE","employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital verification, Interface IP protocols, System Verilog, SVA, UVM methodologies, Digital design and verification concepts, Simulation tools, Analytical and problem-solving skills, Communication skills, RTL design through synthesis, VCS, Model Sim, or similar"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2979db56-dec"},"title":"SOC Engineering, Staff Engineer (Physical Design)","description":"<p>Opening. Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for independently owning and driving full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</p>\n<ul>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n</ul>\n<ul>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n</ul>\n<ul>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n</ul>\n<ul>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimization, STA, EMIR, and physical verification.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2979db56-dec","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/soc-engineering-staff-engineer-physical-design/44408/91188492080","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","CTS","timing optimization","STA","EMIR","physical verification"],"x-skills-preferred":["Python","PERL","TCL"],"datePosted":"2026-02-04T16:17:00.859Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, CTS, timing optimization, STA, EMIR, physical verification, Python, PERL, TCL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_170d1e0b-679"},"title":"ASIC Digital Design, Manager","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<ul>\n<li>Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.</li>\n<li>Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>MSEE (preferred) or equivalent with a minimum of 5 years&#39; experience in digital design and verification.</li>\n<li>Proven proficiency in Verilog or VHDL for ASIC development.</li>\n<li>Experience with code quality metrics and coverage-driven verification methodologies.</li>\n<li>In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies.</li>\n<li>Strong understanding of CDC, synthesis, and power optimization techniques.</li>\n<li>Hands-on experience with simulation tools and collaborative debugging in verification environments.</li>\n<li>Ability to develop system-level specifications for complex digital and analog systems.</li>\n</ul>\n<p><strong>What you&#39;ll be doing:</strong></p>\n<ul>\n<li>Leading digital design and verification activities for advanced SERDES products, including Backplane Ethernet, PCIe, SATA, and USB 2/3.</li>\n<li>Analyzing and interpreting digital and analog specifications, ensuring seamless integration in mixed-signal environments.</li>\n<li>Driving the creation, execution, and tracking of comprehensive test plans, including functional, assertion, and code coverage metrics.</li>\n<li>Overseeing design flows for clock domain crossing (CDC), synthesis, design-for-test (DFT), and low-power methodologies.</li>\n<li>Collaborating closely with verification teams to debug issues, analyze failure cases, and run gate-level simulations.</li>\n<li>Coordinating with cross-functional teams and providing technical leadership throughout the product lifecycle, from specification development to performance testing of test chips.</li>\n<li>Mentoring and developing junior engineers, fostering a culture of continuous learning and innovation.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the delivery of industry-leading mixed-signal ASIC solutions, enabling next-generation connectivity standards.</li>\n<li>Enhance the quality and reliability of high-speed SERDES products through rigorous design and verification practices.</li>\n<li>Drive process improvements that elevate team productivity and product performance.</li>\n<li>Champion best practices in digital and mixed-signal design, setting new benchmarks for quality and efficiency.</li>\n<li>Foster a collaborative and innovative team environment, empowering engineers to reach their full potential.</li>\n<li>Strengthen Synopsys&#39; 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