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<source>
  <jobs>
    <job>
      <externalid>980acb3a-e35</externalid>
      <Title>Principal ASIC Digital Design Engineer</Title>
      <Description><![CDATA[<p>As a Principal ASIC Digital Design Engineer, you will be responsible for designing and verifying advanced digital circuits for PAM-based SerDes PHY IP. Your expertise in high-speed serializer and data recovery circuits will position you as a key contributor to the next generation of PAM-based SerDes products.</p>
<p><strong>What you&#39;ll do</strong></p>
<ul>
<li>Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.</li>
<li>Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.</li>
</ul>
<p><strong>What you need</strong></p>
<ul>
<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.</li>
<li>Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required</li>
<li>Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows</li>
</ul>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>Verilog, VCS, digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows, RTL coding, modeling of analog blocks, writing complex system-level test-benches in Verilog, defining synthesis design constraints, resolving STA issues, gate-level simulation failures, Clock/Reset domain crossing design constraints, evaluating violations using CDC/RDC tools</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and IP solutions. The company&apos;s technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. Synopsys&apos; solutions empower the creation of high-performance silicon chips and software content.</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/mississauga/asic-digital-design-principal-engineer-14687/44408/91568840256</Applyto>
      <Location>Mississauga, Ontario, Canada</Location>
      <Country></Country>
      <Postedate>2026-03-06</Postedate>
    </job>
    <job>
      <externalid>0b31f810-480</externalid>
      <Title>ASIC Digital Design, Sr Engineer</Title>
      <Description><![CDATA[<p>Opening.</p>
<p><strong>What you&#39;ll do</strong></p>
<p>You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.</p>
<ul>
<li>Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.</li>
<li>Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.</li>
</ul>
<p><strong>What you need</strong></p>
<ul>
<li>B.E/B.Tech/M.Tech in Electronics &amp; Communication Engineering, Electrical Engineering, or related field.</li>
<li>3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).</li>
<li>Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).</li>
<li>Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.</li>
<li>Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.</li>
<li>Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.</li>
</ul>
<p style="margin-top:24px;font-size:13px;color:#666;">XML job scraping automation by <a href="https://yubhub.co">YubHub</a></p>]]></Description>
      <Jobtype>full-time</Jobtype>
      <Experiencelevel>senior</Experiencelevel>
      <Workarrangement>onsite</Workarrangement>
      <Salaryrange></Salaryrange>
      <Skills>HDL coding (Verilog), Synthesis constraints, Static Timing Analysis (STA), Linting and verification tools, Scripting languages (Perl, Shell, Python, TCL), High-speed SERDES protocols, RTL implementation</Skills>
      <Category>Engineering</Category>
      <Industry>Technology</Industry>
      <Employername>Synopsys</Employername>
      <Employerlogo>https://logos.yubhub.co/careers.synopsys.com.png</Employerlogo>
      <Employerdescription>Synopsys is a leading provider of electronic design automation (EDA) software and intellectual property (IP) solutions. The company&apos;s technology is used to design and develop complex electronic systems, including semiconductors, software, and systems-on-chip (SoCs).</Employerdescription>
      <Employerwebsite>https://careers.synopsys.com</Employerwebsite>
      <Compensationcurrency></Compensationcurrency>
      <Compensationmin></Compensationmin>
      <Compensationmax></Compensationmax>
      <Applyto>https://careers.synopsys.com/job/noida/asic-digital-design-sr-engineer/44408/92188289744</Applyto>
      <Location>Noida, Uttar Pradesh, India</Location>
      <Country></Country>
      <Postedate>2026-03-04</Postedate>
    </job>
  </jobs>
</source>